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Nonreflective, 100 MHz to 44 GHz Silicon SP4T Switch Data Sheet ADRF5042 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Ultrawideband frequency range: 100 MHz to 44 GHz Nonreflective 50 Ω design Low insertion loss 1.8 dB up to 18 GHz 2.8 dB up to 40 GHz 3.2 dB up to 44 GHz High isolation 50 dB up to 18 GHz 39 dB up to 40 GHz 35 dB up to 44 GHz High input linearity P0.1dB: 26 dBm typical IP3: 47 dBm typical High power handling 24 dBm through path 24 dBm terminated path All off state control Logic select control No low frequency spurs Settling time (0.1 dB final RF output): 30 ns 24-terminal, 3 mm × 3 mm land grid array (LGA) package Pin compatible with ADRF5043, low frequency cutoff version
APPLICATIONS
Cellular infrastructure—millimeterwave (mmWave) 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) FUNCTIONAL BLOCK DIAGRAM GND VSS RFC GND DRIVERVDD GND GND RF4 GND GND GND RF1 GND 50Ω 50Ω 50Ω 50Ω 1 19 GND RF2 GND RF3 GND GND GND EN 7LS 23793-001 Figure 1. GENERAL DESCRIPTION The ADRF5042 is a nonreflective SP4T switch manufactured in the silicon on insulator (SOI) process. The ADRF5042 operates from 100 MHz to 44 GHz with an insertion loss of lower than 3.2 dB and an isolation of higher than 35 dB. The device has a RF input power handling capability of 24 dBm for both through and terminated paths. The ADRF5042 requires a dual-supply voltage of +3.3 V and −3.3 V . The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls. The ADRF5042 has enable and logic select controls to feature all off state and port mirroring, respectively. The ADRF5042 is pin compatible with the ADRF5043 low frequency cutoff version, which operates from 9 kHz to 44 GHz. The ADRF5042 comes in a 24-terminal, 3 mm × 3 mm, RoHS compliant, land grid array (LGA) package and can operate from −40°C to +105°C.
Rev. 0 | Page 2 of 12 TABLE OF CONTENTS
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 3 of 12 SPECIFICATIONS Positive supply voltage (VDD) = 3.3 V, negative supply voltage (VSS) = −3.3 V, V1 pin voltage (V1) = 0 V or 3.3 V, V2 pin voltage (V2) = 0 V is the digital control inputs voltage. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE f 100 44,000 MHz INSERTION LOSS Between RFC and RFx (On) 100 MHz to 18 GHz 1.8 dB 18 GHz to 26 GHz 2.2 dB 26 GHz to 35 GHz 2.5 dB 35 GHz to 40 GHz 2.8 dB 40 GHz to 44 GHz 3.2 dB ISOLATION Between RFC and RFx (Off ) 100 MHz to 18 GHz 50 dB
18 GHz to 26 GHz 46 dB
26 GHz to 35 GHz 41 dB
35 GHz to 40 GHz 39 dB
40 GHz to 44 GHz 35 dB
RFC and RFx (On) 100 MHz to 18 GHz 16 dB
18 GHz to 26 GHz 14 dB
26 GHz to 35 GHz 13 dB
35 GHz to 40 GHz 13 dB
40 GHz to 44 GHz 14 dB
RFx (Off ) 100 MHz to 18 GHz 24 dB
18 GHz to 26 GHz 22 dB
26 GHz to 35 GHz 15 dB
35 GHz to 40 GHz 12 dB
40 GHz to 44 GHz 10 dB
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 3 ns On and Off Time tON, tOFF 50% VCTL to 90% of RF output 14 ns Settling Time 0.1 dB 50% VCTL to 0.1 dB of final RF output 30 ns 0.05 dB 50% VCTL to 0.05 dB of final RF output 36 ns INPUT LINEARITY1 0.1 dB Power Compression P0.1dB f = 500 MHz to 40 GHz 26 dBm 1 dB Power Compression P1dB f = 500 MHz to 40 GHz 27 dBm Third-Order Intercept IP3 Two-tone input power = 15 dBm each tone, f = 500 MHz to 40 GHz, Δf = 1 MHz 47 dBm Second-Order Intercept IP2 Two-tone input power = 15 dBm each tone, f = 10 GHz, Δf = 1 MHz 120 dBm VIDEO FEEDTHROUGH2 60 mV p-p SUPPLY CURRENT VDD, VSS pins Positive Supply Current IDD 370 µA Negative Supply Current ISS −100 µA DIGITAL CONTROL INPUTS V1, V2, EN, LS pins Voltage Low VINL 0 0.8 V High VINH 1.2 3.3 V
Rev. 0 | Page 4 of 12 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Current Low IINL 3 µA High IINH 6 µA RECOMMENDED OPERATING CONDITONS Supply Voltage Positive VDD 3.15 3.45 V Negative VSS −3.45 −3.15 V Digital Control Inputs Voltage VCTL 0 VDD V RFx Input Power3 PIN f = 500 MHz to 44 GHz, TCASE = 85°C4 Through Path Average 24 dBm Peak 24 dBm Terminated Path Average 24 dBm Peak 24 dBm Hot Switching Average 24 dBm Peak 24 dBm Case Temperature TCASE −40 +105 °C 1 For input linearity performance over frequency, see Figure 18 to Figure 21. 2 Video feedthrough is the spurious dc transient measured at the RF ports in a 50 Ω test setup, without an RF signal present while switching the control voltage. 3 For power derating over frequency, see Figure 2. 4 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
For recommended operating conditions, see Table 1. 1 Overvoltages at digital control inputs are clamped by internal diodes. Current must be limited to the maximum rating given. 2 For power derating over frequency, see Figure 2.
3 For 105°C operation, the power handling degrades from the TCASE = 85°C
PCB thermal design is required. Table 3. Thermal Resistance operating temperature of 85°C. sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 4. ADRF5042, 24-Terminal LGA Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
13 GND
- THE EXPOSED PAD MUST BE CONNECTED
Figure 3. Pin Configuration (Top View) Table 5. Pin Function Descriptions 1 EN Enable Input. See Table 6 for the truth table. See Figure 5 for the interface schematic. 2 V1 Control Input 1. See Table 6 for the truth table. See Figure 5 for the interface schematic. GND Ground. The GND pins must be connected to the RF and dc ground of the PCB. when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. 6 VSS Negative Supply Voltage. 7 LS Logic Select Input. See Table 6 for the truth table. See Figure 5 for the interface schematic. 8 VDD Positive Supply Voltage. when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. when the RF line potential is equal to 0 V dc. 24 V2 Control Input 2. See Table 6 for the truth table. See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to the RF and dc ground. Figure 4. RFC and RF1 to RF4 Pin Interface Schematic Figure 5. V1, V2, EN, and LS Pin Interface Schematic
VDD pin and a negative supply voltage applied to the VSS pin. 50 Ω. Therefore, external matching networks are not required. V2) that control the state of the RFx paths (see Table 6). design is bidirectional with equal power handling capabilities. ports that are terminated to internal 50 Ω resistors.
- Power up VDD and VSS. Powering up VSS after VDD
avoids current transients on VDD during ramp up.
- Apply a control voltage to the digital control inputs (EN,
- Apply an RF input signal.
Table 6. Control Voltage Truth Table
Rev. 0 | Page 12 of 12 OUTLINE DIMENSIONS 06-11-2020-A PKG-006844 3.10 3.00 SQ 2.90 TOP VIEW BOTTOM VIEW SIDE VIEW 71213 20 24 0.40 BSC 0.248 0.208 0.168 0.808 0.738 0.668 0.250 0.200 0.150 0.325 0.275 0.225
0.530 REF
0.125 REF
1.50 BSC
1.60 REF 2.40 REF PIN 1 INDICA TOR (C0.225 ×0.45°) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. EXPOSED PAD F igure 25. 24-Terminal Land Grid Array [LGA] 3 mm × 3 mm Body and 0.738 mm Package Height (CC-24-12) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Marking Code ADRF5042BCCZN −40°C to +105°C 24-Terminal Land Grid Array [LGA] CC-24-12 042 ADRF5042BCCZN-R7 −40°C to +105°C 24-Terminal Land Grid Array [LGA] CC-24-12 042 ADRF5042-EVALZ E valuation Board 1 Z = RoHS Compliant Part. ©2020 Analog D evices, I nc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D23793-7/20(0)