ADRF5030 AD | Alldatasheet

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Technical content

100 MHz to 20 GHz, Non-Reflective, Silicon SPDT Switch

Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Wideband frequency range, 100 MHz to 20 GHz ►Non-reflective 50 Ω design ►Low insertion loss ►0.7 dB typical between 0.1 GHz to 6 GHz ►0.9 dB typical between 6 GHz to 12 GHz ►1.2 dB typical up to 20 GHz ►High isolation ►55 dB typical between 100 MHz to 6 GHz ►50 dB typical between 6 GHz to 12 GHz ►45 dB typical up to 20 GHz ►High input linearity ►P0.1dB: >36 dBm typical ►IP3: >60 dBm typical ►High RF power handling ►Through path: 36 dBm peak/33 dBm average ►Terminated path: 36 dBm peak/33 dBm average ►Hot switching: 36 dBm peak/33 dBm average ►CMOS/LVTTL compatible ►No low-frequency spur; no negative voltage generator ►RF switching time: 70 ns ►RF settling time (0.1 dB): 95 ns ►Single-supply operation capability (VDD = 3.3 V, VSS = 0 V) ►20-terminal, 3 mm × 3 mm, LGA package ►Pin compatible with ADRF5022 and ADRF5026

APPLICATIONS

►Test instrumentation ►Military radios, radars, electronic counter measures (ECMs) ►Microwave radios and very small aperture terminals (VSATs) FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram handling performance are derated. See Table 2 for more details.

analog.com Rev. 0 | 2 of 13 Input Power Compression and Third-Order Recommendations for Printed Circuit Board

REVISION HISTORY

7/2024—Revision 0: Initial Version

VDD = 3.3 V, VSS = −3.3, VCTRL = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted. RFx refers to RF1 or RF2. Table 1. Electrical Characteristics

6 GHz to 12 GHz 50

12 GHz to 20 GHz 45 dB

Second-Order Intercept IP2 Two-tone input power = 14 dBm each tone, f = 8 GHz.

Table 1. Electrical Characteristics (Continued) 1 For input linearity performance over frequency, see Figure 12 to Figure 15. 2 For power derating over frequency, see the Power Derating Curves section. 3 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB. 4 Peak: ( ≤100 ns pulse duration, 5% duty cycle). 5 Pulse: (>100 ns pulse duration, 15% duty cycle). VDD = 3.3 V, VSS = 0, VCTRL = 0 V or VDD, TCASE = 25°C for 50 Ω system, unless otherwise noted. Table 2. Single-Supply Operational Specifications

For the recommended operating conditions, see Table 1. Table 3. Absolute Maximum Ratings 1 Overvoltages at the digital control input are clamped by internal diodes. Current must be limited to the maximum rating given. 2 For power derating over frequency, see Figure 2.

3 For 105°C operation, the power handling degrades from the TCASE = 85°C

specification by 3 dB for dual supply.

4 Peak: (≤100 ns pulse duration, 5% duty cycle)

ing conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. Table 4. Thermal Resistance Figure 2. Power Derating vs. Frequency, Low-Frequency Detail, TCASE = 85° sitive devices in an ESD-protected area only. Table 5. ADRF5030, 20-Terminal LGA

analog.com Rev. 0 | 6 of 13 ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devi- ces and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration (Top View) Table 6. Pin Function Descriptions GND Ground. These pins must be connected to the RF/DC ground of the PCB. to 0 V DC. See Figure 4 for the interface schematic. DC. See Figure 4 for the interface schematic. 11 VDD Positive Supply Voltage. See Figure 6 for the interface schematic. 12 CTRL Control Input Voltage. See for the truth table. See Figure 5 for the interface schematic. 14 EN Enable Input Voltage. See for the truth table. See Figure 5 for the interface schematic. 15 VSS Negative Supply Voltage. See Figure 7 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to the RF/DC ground of the PCB.

terminated to internal 50 Ω resistors, and RFC becomes reflective. is equal to 0 V. The RF ports are internally matched to 50 Ω.

  1. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

  1. Apply digital control inputs. The relative order of the control

and the control pins are not driven to a valid logic state. Table 7. Control Voltage Truth Table

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A.

0.530 REF

0.222 REF

0.30 REF

1.60 REF

Figure 20. 20-Terminal Land Grid Array [LGA]