ADRF5023 (Rev.A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 12
Technical content
Silicon SPDT Switch, Nonreflective, 9 kHz to 45 GHz Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Ultra-wideband frequency range: 9 kHz to 45 GHz ►Nonreflective design ►Low insertion loss ►0.9 dB typical to 18 GHz ►1.6 dB typical to 40 GHz ►1.7 dB typical to 45 GHz ►High Isolation: 42 dB typical to 45 GHz ►High input linearity ►0.1 dB power compression (P0.1dB): 31 dBm ►Third-order intercept (IP3): 53 dBm ►High power handling at TCASE = 85°C ►30 dBm through path ►24 dBm terminated path ►30 dBm hot switching (RFC port) ►RF settling time (0.1 dB final RF output): 3.5 μs ►No low-frequency spurious signals ►All off state control ►Positive Control Interface: CMOS-/LVTTL-compatible ►20-lead, 3.0 mm × 3.0 mm LGA package
APPLICATIONS
►Test and instrumentation ►Cellular Infrastructure: 5G millimeter wave ►Military radios, radars, and electronic countermeasures (ECMs) ►Microwave radios and very small aperture terminals (VSATs) ►Industrial scanner FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram switch manufactured in the silicon process. (LVTTL)-compatible controls. handling performance is derated. See Table 2 for more details. switching version that operates from 100 MHz to 45 GHz.
analog.com Rev. A | 2 of 12 Input Power Compression and Third-Order
REVISION HISTORY
10/2023—Rev. 0 to Rev. A 1/2023—Revision 0: Initial Version
VDD = 3.3 V, VSS = −3.3 V, CTRL voltage (VCTRL)/EN voltage (VEN) = 0 V or VDD, and TCASE = 25°C, 50 Ω system, unless otherwise noted. Table 1. Electrical Specifications
18 GHz to 26 GHz 20 dB
26 GHz to 35 GHz 18 dB
35 GHz to 40 GHz 18 dB
40 GHz to 45 GHz 18 dB
18 GHz to 26 GHz 21 dB
26 GHz to 35 GHz 16 dB
35 GHz to 40 GHz 13 dB
40 GHz to 45 GHz 12 dB
18 GHz to 26 GHz 55 dB
26 GHz to 35 GHz 55 dB
35 GHz to 40 GHz 50 dB
40 GHz to 45 GHz 49 dB
18 GHz to 26 GHz 56 dB
26 GHz to 35 GHz 48 dB
35 GHz to 40 GHz 44 dB
40 GHz to 45 GHz 42 dB
Table 1. Electrical Specifications (Continued) 1 For input linearity performance over frequency, see Figure 14 to Figure 17. 2 For power derating over frequency, see Figure 2 and Figure 3. 3 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB. VDD = 3.3 V, VSS = 0 V, VCTRL/VEN = 0 V or VDD V, TCASE = 25°C, 50 Ω system, unless otherwise noted. Table 2. Single-Supply Operational Specifications 1 For power derating over frequency, see Figure 2 and Figure 3. 2 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 5. ADRF5023, 20-Terminal LGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
nally and to provide the advantage of a simplified control interface. VDD pin and a negative supply voltage applied to the VSS pin.
- Power up VDD and VSS. Power up VSS after VDD to avoid
current transients on VDD during ramp-up.
- Power up the digital control inputs. Power the digital control
- Apply an RF input signal.
- The ideal power-down sequence is the reverse order of the
and large signal, see Table 1 for more details. matching networks are not required. RFC port becomes reflective open. Table 7. Control Voltage Truth Table
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 22. 20-Terminal Land Grid Array [LGA] Table 8. Evaluation Boards