ADPL62083 AD | Alldatasheet
Document overview
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Technical content
Low-Power, Supervisory Circuit in 3-Lead SOT23 19-101951; Rev 0; 11/24 DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
Low Supply Current: 5µA (typ), 6.8µA (max) at 3.6V Over Temperature (+125°C) Factory-Set Reset Threshold Options from 1.02V to 4.8V in 50mV/100mV Increments Guaranteed Reset Valid to VCC ≥ 1V Open-Drain Reset Output Power-Supply Transient Immunity -40°C to +125°C Operating Temperature Range
APPLICATIONS
Portable/Battery-Powered and Industrial Equipment e-Readers/Tablets Smartphones GENERAL DESCRIPTION The ADPL62083 is a supervisory circuit that monitors voltages from 1.02V to 4.8V using a factory-set reset threshold. The ADPL62083 features an open-drain, active-low reset output. The reset output asserts and remains asserted for the reset timeout period after the monitored voltage exceeds its threshold. The ADPL62083 is available in 3-lead SOT23 package. It operates over the -40°C to +125°C temperature range. SIMPLIFIED APPLICATION DIAGRAM (a) (b) Figure 1. (a) Typical Application Circuit and (b) Functional Block Diagram
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REVISION HISTORY
11/2024 - Rev 0: Initial Release
Table 1. Electrical Characteristics 2 Reset is guaranteed down to VCC = 1V. 3 Guaranteed by design, not production tested.
Figure 2. Reset Timing Diagram TA = 25°C, unless otherwise specified. Table 2. Absolute Maximum Ratings for extended periods may affect product reliability.
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PACKAGE INFORMATION
Table 3. Package Information
3 SOT23
but the drawing pertains to the package regardless of RoHS status. Figure 3. Pin Configuration Table 4. Pin Descriptions
1 GND Ground
2 RESET
low for the reset timeout period after VCC exceeds the reset threshold.
3 VCC
between the VCC and GND pins.
Figure 10. VCC to Reset Output Delay vs. Temperature
output asserts and remains asserted for the reset timeout period after the monitored voltage exceeds its threshold. threshold of VTH. When VCC rises above VTH + VHYST, RESET goes high after the reset timeout period (tRP). See Figure 2. capacitor as close as possible to the device between the VCC and GND pins. allows either device to assert a reset (Figure 11). Figure 11. Interfacing to µP with Bidirectional Reset Pins close as possible to the device between the VCC and GND pins.
Table 5. Ordering Guide +Denotes a lead(Pb)-free/RoHS-compliant package. Figure 12. Selector Guide
3 OPEN-DRAIN
ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY. analog.com Rev 0 10 of 10