ADPL13602 AD | Alldatasheet
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Technical content
3.5V to 36V, 2.4A, High-Efficiency, Synchronous Step-Down DC-DC Converter 19-101823, Rev 0; 12/23 DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
Reduces External Components and Total Cost No Schottky—Synchronous Operation Internal Compensation Components All-Ceramic Capacitors, Compact Layout Reduces the Number of DC-DC Regulators to Stock Wide 3.5V to 36V Input Adjustable Output Voltage Range from 1V up to 90% of VIN Delivers Up to 2.4A Over the Temperature Range 400kHz to 1.5MHz Adjustable Frequency Reduces Power Dissipation Peak Efficiency of 95% Wide 2.4V to 12V Bootstrap Bias Input (EXTVCC) for Improved Efficiency Operates Reliably in Adverse Industrial Environments Hiccup-Mode Overload Protection Adjustable and Monotonic Startup with Prebiased Output Voltage Built-in Output-Voltage Monitoring with RESET Programmable EN/UVLO Threshold Wide Industrial -40°C to +125°C Ambient Operating Temperature Range or -40°C to +150°C Junction Temperature Range GENERAL DESCRIPTION The ADPL13602 is a high -efficiency, synchronous step - down DC -DC converter with integrated MOSFETs operating over an input -voltage range of 3.5V to 36V. It can deliver up to 2.4A current. Output voltage is programmable from 1 V up to 90% of V IN. Built -in compensation across the output -voltage range eliminates the need for external compensation components. The ADPL13602 features a peak -current-mode control architecture. The ADPL13602 can be operated in forced pulse-width modula tion (PWM) or discontinuous - conduction mode (DCM) to enable high efficiency under full-load and light -load conditions. The ADPL13602 offers a low minimum on -time that allows high switching frequencies and a smaller solution size. The feedback-voltage regulation accuracy over -40°C to +125°C is ±1.5%. The device is available in a 16-pin (3mm x 3mm) TQFN -EP package. Simulation models are available.
APPLICATIONS
Industrial Control Power Supplies Distributed Supply Regulation Wall Transformer Regulation High-Voltage, Single-Board Systems SIMPLIFIED APPLICATION DIAGRAM 5V OUTPUT, DCM MODE EFFICIENCY vs. LOAD CURRENT LOAD CURRENT(A) EFFICIENCY (%) VCC SGND SS PGND EXTVCC FB LX BSTVIN EN/UVLO VIN VOUT VOUT ADPL13602 100 0 2.401.801.200.60 VIN = 12V VIN = 24V fSW = 500KHz Figure 1. Simplified Application Diagram and Efficiency vs. Load Current
analog.com Rev. 0 2 of 28
REVISION HISTORY
0 12/23 Initial release —
Table 1. Electrical Characteristics
analog.com Rev. 0 4 of 28 (VIN = VEN/UVLO = 24V, RT = Unconnected (fSW = 500kHz), CVCC = 2.2uF, VMODE = VEXTVCC = VSGND = VPGND = 0, VFB = 0.64V, LX = SS = RESET = Open, VBST to VLX = 1.8V, TA = TJ = -40°C to 125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND unless otherwise noted. (Note 1)) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS POWER MOSFETS High-Side nMOS On- Resistance RDS_ONH ILX = 0.3A, sourcing 0.14 0.27 Ω Low-Side nMOS On-Resistance RDS_ONL ILX = 0.3A, sinking 0.1 0.19 Ω LX Leakage Current ILX_LKG VIN = 36V, TA = +25°C, VLX = (VPGND + 1)V to (VIN -1)V, VEN/UVLO = 0V -2 +2 μA SOFT-START (SS) Charging Current ISS VSS = 0.3V 4.7 5 5.3 μA FEEDBACK (FB) FB Regulation Voltage VFB_REG 0.591 0.600 0.609 V FB Input Bias Current IFB VFB = 1V, TA = +25°C -50 +50 nA MODE SELECTION (MODE) MODE Threshold VM_DCM DCM mode 1.22 V VM_PWM PWM mode 0.66 CURRENT LIMIT Peak Current-Limit Threshold IPEAK_LIMIT 2.8 3.4 4.1 A Valley Current-Limit Threshold IVALLEY_LIMIT DCM Mode 0.1 A PWM Mode -1.8 OSCILLATOR (RT) Programmable Switching Frequency Range fSW 400 1500 kHz Switching Frequency Accuracy -10 +10 %
analog.com Rev. 0 5 of 28 (VIN = VEN/UVLO = 24V, RT = Unconnected (fSW = 500kHz), CVCC = 2.2uF, VMODE = VEXTVCC = VSGND = VPGND = 0, VFB = 0.64V, LX = SS = RESET = Open, VBST to VLX = 1.8V, TA = TJ = -40°C to 125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND unless otherwise noted. (Note 1)) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS VFB Undervoltage Trip Level to Cause Hiccup VFB_HICF 0.375 0.390 0.405 V HICCUP Timeout (Note 2) 32768 Cycles Minimum On-Time tON_MIN 60 90 ns Minimum Off-Time tOFF_MIN 100 150 ns OUTPUT STATUS MONITORING (RESET) RESET Output Level Low VRESETL IRESET = 10mA 0.4 V RESET Output Leakage Current IRESETLKG TA = TJ = +25°C -0.1 +0.1 μA FB Threshold for RESET Deassertion VFB_OKR VFB rising 93.1 95.0 97.0 % of VFB_REG FB Threshold for RESET Assertion VFB_OKF VFB falling 89.8 92.0 93.2 % of VFB_REG RESET Delay After FB Reaches 95% Regulation
1024 Cycles
Threshold Temperature rising 160 °C Thermal-Shutdown Hysteresis 20 °C Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range are guaranteed by design and characterization. See Overcurrent Protection (OCP)/Hiccup Mode section for more details.
TA = 25°C unless otherwise specified. Table 2. Absolute Maximum Ratings Junction temperature greater than +125°C degrades operating lifetimes. conditions for extended periods may affect device reliability.
Table 3. Pin Descriptions
1 EN/UVLO
than VEN_TRUESD) for disabling the device. support the external loading on VCC.
3 SGND Signal Ground
4 MODE
operation. Connect MODE to SGND for constant-frequency PWM operation at all loads. 5 SS Soft-Start Input. Connect a capacitor from SS to SGND to set the soft-start time.
analog.com Rev. 0 8 of 28 8 RESET Open-Drain RESET Output. The RESET output is driven low if FB drops below VFB_OKF. RESET goes high 1024 cycles after FB rises above VFB_OKR.
9 EXTVCC
External Bias Input. Applying a voltage between 2.448V and 12V at EXTVCC will bypass the IN-LDO and improve overall converter efficiency. Connect a buck regulator output to EXTVCC through an RC filter (4.7Ω, 0.1μF) to protect the EXTVCC pin from reaching its absolute maximum rating (-0.3V) during an output short-circuit condition. When EXTVCC is not used, connect it to SGND. 10 BST Bootstrap Capacitor. Connect a 0.1μF ceramic capacitor between BST and LX. 11, 12 LX Switching Node Pins. Connect LX pins to the switching side of the inductor. 13, 14 PGND Power Ground Pins of the Converter. Connect externally to the power ground plane. Refer to the ADPL13602 Evaluation Kit data sheet for a layout example. 15, 16 VIN Power-Supply Input Pins. 3.5V to 36V input-supply range. Decouple to PGND with a minimum 2.2µF capacitor; place the capacitor close to the VIN and PGND pins. See Input Capacitor Selection for more details. — EP Exposed Pad. Always connect EP to the SGND pin of the IC. Also, connect EP to a large plane with several thermal vias for best thermal performance. Refer to the ADPL13602 Evaluation Kit data sheet for an example of the correct method for EP connection and thermal vias.
analog.com Rev. 0 9 of 28 TYPICAL PERFORMANCE CHARACTERISTICS (VEN/UVLO = VIN = 24V, VSGND = VPGND = 0V, CVCC = 2.2μF, CBST = 0.1μF, CSS = 6800pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
analog.com Rev. 0 10 of 28 (VEN/UVLO = VIN = 24V, VSGND = VPGND = 0V, CVCC = 2.2μF, CBST = 0.1μF, CSS = 6800pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
analog.com Rev. 0 11 of 28 (VEN/UVLO = VIN = 24V, VSGND = VPGND = 0V, CVCC = 2.2μF, CBST = 0.1μF, CSS = 6800pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
analog.com Rev. 0 12 of 28 (VEN/UVLO = VIN = 24V, VSGND = VPGND = 0V, CVCC = 2.2μF, CBST = 0.1μF, CSS = 6800pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.) LOAD GAIN GAIN PLOT FIGURE 6 CIRCUIT
analog.com Rev. 0 13 of 28 (VEN/UVLO = VIN = 24V, VSGND = VPGND = 0V, CVCC = 2.2μF, CBST = 0.1μF, CSS = 6800pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.) GAIN
Figure 2. Block Diagram
analog.com Rev. 0 15 of 28 DETAILED DESCRIPTION The ADPL13602 is a high-efficiency, synchronous step-down DC-DC converter with integrated MOSFETs. It can deliver up to 2.4A over an input voltage range of 3.5V to 36V. Built-in compensation across the output-voltage range eliminates the need for external compensation components. The feedback-voltage regulation accuracy over -40°C to +125°C is ±1.5%. The device features a peak-current-mode control architecture. An internal transconductance error amplifier produces an integrated error voltage at an internal node, which sets the duty cycle using a PWM comparator, a high-side current-sense amplifier, and a slope-compensation generator. At each rising edge of the clock, the high- side MOSFET turns on and remains on until either the appropriate or maximum duty cycle is reached, or the peak current limit is detected. During the high-side MOSFET’s on-time, the inductor current ramps up. During the second half of the switching cycle, the high-side MOSFET turns off, and the low-side MOSFET turns on. The inductor releases the stored energy as its current ramps down and provides current to the output. The device features a MODE pin that can be used to operate the device in PWM or DCM mode. The device also features an adjustable-input undervoltage lockout, adjustable soft-start, and output voltage monitoring with open- drain RESET. The ADPL13602 offers a low minimum on time, allowing high switching frequencies and a smaller solution size. Mode Selection (MODE) The ADPL13602 supports forced PWM and DCM modes of operation. The device enters the required mode of operation based on the setting of the MODE pin as detected during power-up after VIN, VCC, and EN/UVLO voltages exceed their respective UVLO rising thresholds (VIN_UVLO_R, VCC_UVR, VENR). If the state of the MODE pin is high (> VM_DCM), the device operates in DCM mode at light loads. If the state of the MODE pin is low (< VM_PWM), the device operates in constant-frequency PWM mode at all loads. See the MODE section in the Specifications table for details. PWM Mode Operation In PWM mode, the inductor current is allowed to go negative. PWM operation provides constant frequency operation at all loads and is useful in applications sensitive to switching frequency. However, the PWM mode of operation gives lower efficiency at light loads than the DCM mode of operation. DCM Mode Operation In the DCM mode of operation, the inductor current can be discontinuous at light loads. The inductor current is not allowed to go negative. Switching pulses are skipped when the buck converter is operated close to no-load condition. DCM operation offers better efficiency performance compared to PWM at light loads. The steady-state output voltage ripple in DCM mode is comparable to that in PWM mode. Linear Regulator (VCC and EXTVCC) The ADPL13602 has two built-in low dropout (LDO) linear regulators that power VCC. One LDO is powered from VIN (IN-LDO), while the other LDO is powered from EXTVCC (EXT LDO). The IN-LDO is enabled either during power-up or when the voltage on the EN/UVLO pin is recycled. Only one of the two LDOs is in operation at a time, depending on the voltage present at EXTVCC. If EXTVCC is greater than 2.4V (typ), VCC is powered by EXT LDO. Powering VCC from EXTVCC increases efficiency at higher input voltages. The typical VCC output voltage is 1.8V. Bypass VCC to SGND with a 2.2μF low-ESR ceramic capacitor. VCC powers the internal blocks and the low-side MOSFET driver. VCC also recharges the external bootstrap capacitor.
65mV (typ) UVLO hysteresis prevents chattering on power-up/power-down. 0.3V) during output short-circuit conditions. Connect EXTVCC pin to SGND when not in use. frequency of 500kHz. See Table 4 for RT resistor values for a few common switching frequencies. Table 4. Switching Frequency vs. RT Resistor
500 Open
analog.com Rev. 0 17 of 28 tOFF_MIN(MAX) = Worst-case minimum switch off-time (150ns) tON_MIN(MAX) = Worst-case minimum switch on-time (90ns) RDS_ONL(MAX) and RDS_ONH(MAX) = Worst-case on-state resistances of low-side and high-side internal MOSFETs, respectively. The maximum slew rate that can be applied on input voltage is 30V/µsec. Overcurrent Protection (OCP)/Hiccup Mode The ADPL13602 features a robust overcurrent-protection (OCP) scheme that protects the device during overload and output short-circuit conditions. The OCP scheme protects the device by using a hysteretic current control during startup. The startup time is the sum of the programmed soft-start time and 2048 programmed switching frequency clock cycles. When the inductor current exceeds IPEAK_LIMIT (3.4A (typ)), the high-side MOSFET is turned off, and the low-side MOSFET is turned on. After the inductor current falls below 0.85 x IPEAK_LIMIT, the low-side MOSFET is turned off, and the high- side MOSFET is turned on at the next clock rising edge. In a steady state, the device operates in a cycle-by-cycle peak current limit that turns off the high-side MOSFET when the inductor current exceeds IPEAK_LIMIT and turns on the low-side MOSFET. The low-side switch is turned off, and the high-side switch is turned on at the next clock rising edge. If the feedback voltage drops below VFB_HICF due to a fault condition any time after startup time is complete, the hiccup mode is triggered. In hiccup mode, the converter is protected by suspending switching for a hiccup timeout period of 32,768 clock cycles of the programmed switching frequency before soft-start is attempted again. During startup time, if feedback voltage does not exceed VFB_HICF, the device continues to operate in hysteretic control. The hiccup mode of operation ensures low average power dissipation under output short-circuit conditions. RESET Output The device includes a RESET comparator to monitor the status of the output voltage. The open- drain RESET output requires an external pullup resistor. RESET goes high (high impedance) 1024 switching cycles after the FB voltage increases above VFB_OKR. RESET goes low when the FB voltage drops to below VFB_OKF. RESET also goes low during thermal shutdown or when the EN/UVLO pin goes below the EN/UVLO falling threshold (VENR - VEN_HYS). Prebiased Output In a prebiased output condition, both the high-side and the low-side switches are turned off so that the converter does not sink current from the output. High-side and low-side switches do not start switching until the PWM comparator commands the first PWM pulse, at which point switching commences. The output voltage is then smoothly ramped up to the target value in alignment with the internal reference. Thermal Shutdown Protection Thermal shutdown protection limits the junction temperature of the device. When the device's junction temperature exceeds +160°C, an on-chip thermal sensor shuts down the device, allowing the device to cool. The device turns on with soft-start after the junction temperature reduces by 20°C. Carefully evaluate the total power dissipation (see the Power Dissipation section) to avoid unwanted triggering of thermal shutdown during normal operation.
analog.com Rev. 0 18 of 28 APPLICATIONS INFORMATION Input Capacitor Selection The input filter capacitor reduces peak currents drawn from the power source, reducing noise and voltage ripple on the input caused by the circuit’s switching. The following equation defines the input capacitor RMS current requirement (IRMS). IRMS = IOUT(MAX) × √VOUT × ( VIN − VOUT ) VIN where, IOUT(MAX) is the maximum load current. IRMS has a maximum value when the input voltage equals twice the output voltage (VIN ≈ 2 x VOUT), so I𝑅𝑀𝑆(𝑀𝐴𝑋) = I𝑂𝑈𝑇(𝑀𝐴𝑋) 2 . Choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal long- term reliability. Use low-ESR ceramic capacitors with high-ripple-current capability at the input. X7R capacitors are recommended in industrial applications for their temperature stability. Calculate the input capacitance using the following equation: CIN = IOUT(MAX) × D × (1 − D) η × fSW × ∆VIN where: D = VOUT/VIN is the duty ratio of the converter fSW = switching frequency ΔVIN = allowable input-voltage ripple η = efficiency In applications where the source is located distant from the device input, an appropriate electrolytic capacitor should be added in parallel to the ceramic capacitor to provide necessary damping for potential oscillations caused by the inductance of the longer input power path and input ceramic capacitor. Inductor Selection Three key inductor parameters must be specified for operation with the device: inductance value (L), inductor saturation current (ISAT) and DC resistance (RDCR). The switching frequency and output voltage determine the inductor value as follows: L = 1.5 × VOUT f𝑆𝑊 where VOUT and fSW are nominal values and fSW is in Hz. Select an inductor whose value is nearest to the value calculated by the previous formula. Select a low-loss inductor closest to the calculated value with acceptable dimensions and having the lowest possible DC resistance. The saturation current rating (ISAT) of the inductor must be high enough to ensure that saturation can occur only above the peak current-limit value of IPEAK_LIMIT.
analog.com Rev. 0 19 of 28 Output Capacitor Selection X7R ceramic output capacitors are preferred due to their stability over temperature in industrial applications. The output capacitors are usually sized to support a step load of 40% of the maximum output current in the application, so output-voltage deviation is contained to 3% of the output-voltage change. The minimum required output capacitance can be calculated as follows: COUT = 1 2 × ISTEP × tRESPONSE ∆VOUT tRESPONSE ≅ 0.33 fC where: ISTEP = Load current step tRESPONSE = Response time of the controller ΔVOUT = Allowable output-voltage deviation fC = Target closed-loop crossover frequency fSW = Switching frequency. Select fC to be 1/9th of fSW if the switching frequency is less than or equal to 900kHz. If the switching frequency is more than 900kHz, select fC to be 100kHz. Actual derating of ceramic capacitors with DC-bias voltage must be considered while selecting the output capacitor. Derating curves are available from all major ceramic capacitor manufacturers. Soft-Start Capacitor Selection The device implements an adjustable soft-start operation to reduce inrush current. A capacitor connected from the SS pin to SGND programs the soft-start time. The selected output capacitance (CSEL) and the output voltage (VOUT) determine the minimum required soft-start capacitor as follows: CSS ≥ 28 × 10−6 × CSEL × VOUT The soft-start time (tSS) is related to the capacitor connected at SS (CSS) by the following equation: tSS = CSS 8.325 × 10−6 For example, to program a 0.82ms soft-start time, a 6.8nF capacitor should be connected from the SS pin to SGND. During startup, the device operates at half the programmed switching frequency until the FB pin voltage rises above 0.44V. Setting the Input Undervoltage-Lockout Level The device offers an adjustable input undervoltage-lockout level. Set the voltage at which the device turns on with a resistive voltage-divider connected from VIN to SGND (See Figure 3). Connect the center node of the divider to EN/UVLO. Choose R1 to be 3.3MΩ and then calculate R2 as follows: R2 = R1 × 1.25 (VINU − 1.25)
analog.com Rev. 0 21 of 28 Power Dissipation At a particular operating condition, the power losses that lead to temperature rise of the part are estimated as follows: PLOSS = (POUT × (1 η − 1)) − (IOUT 2 × RDCR) POUT = VOUT × IOUT where: POUT = Output power η = Efficiency of the converter RDCR = DC resistance of the inductor (see the Typical Performance Characteristics for more information on efficiency at typical operating conditions). For a typical multilayer board, the thermal performance metrics for the package are as follows: θJA = 38°C/W θJC = 4°C/W The junction temperature of the device can be estimated at any given maximum ambient temperature (TA(MAX)) from the following equation: TJ(MAX) = TA(MAX) + (θJA × PLOSS ) If the application has a thermal-management system that ensures that the exposed pad of the device is maintained at a given temperature (TEP(MAX)) by using proper heat sinks, then the junction temperature of the device can be estimated at any given maximum ambient temperature as: TJ(MAX) = TEP(MAX) + (θJC × PLOSS ) Note: Junction temperatures greater than +125°C degrade operating lifetimes. Printed Circuit Board (PCB) Layout Guidelines All connections carrying pulsed currents must be very short and as wide as possible. The inductance of these connections must be kept to an absolute minimum due to the high di/dt of the currents. Since the inductance of a current-carrying loop is proportional to the area enclosed by the loop, if the loop area is made very small, inductance is reduced. Additionally, small-current loop areas reduce radiated Electromagnetic Interference (EMI). A ceramic input filter capacitor should be placed close to the VIN pins of the IC. This eliminates as many trace inductance effects as possible and gives the IC a cleaner voltage supply. A bypass capacitor for the VCC pin should also be placed close to the pin to reduce the effects of trace impedance. When routing the circuitry around the IC, the signal ground and the power ground for switching currents must be kept separate. They should be connected at a point where switching activity is minimal. This helps to keep the signal ground quiet. The power ground plane should be kept continuous (unbroken) as far as possible. No trace carrying a high switching current should be placed directly over any ground plane discontinuity. PCB layout also affects the thermal performance of the design. A number of thermal throughputs or vias that connect to a large plane should be provided under the exposed pad of the device for efficient heat dissipation. For a sample layout that ensures first-pass success, refer to the ADPL13602 evaluation kit layout available at www.analog.com.
Figure 7. 5V Output with 1MHz Switching Frequency
analog.com Rev. 0 24 of 28 OUTLINE DIMENSIONS
analog.com Rev. 0 25 of 28
suffix character, but the drawing pertains to the package regardless of RoHS status. Table 5. Thermal Resistance of 16 TQFN-EP Note 4: Package thermal resistances were obtained using the ADPL13602 Evaluation Kit with no airflow.
analog.com Rev. 0 27 of 28 ORDERING GUIDE PART NUMBER PIN-PACKAGE ADPL13602BATE+ 16 TQFN-EP* (3mm x 3mm) ADPL13602BATE+T 16 TQFN-EP* (3mm x 3mm) + Denotes a lead (Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad.
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