ADPD7008 (Rev.0)

Document overview

  • Manufacturer or author: Analog Devices, Inc.
  • PDF pages: 71

Technical content

Multimodal Sensor Front End Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Optical channel ►4 input channels with multiple operation modes for various sensor measurements ►4-channel processing with simultaneous sampling ►12 programmable time slots for synchronized sensor meas- urements ►Flexible input multiplexing to support single-ended sensor measurements ►8 LED drivers, 2 of which can be driven simultaneously ►Flexible sampling rate from 0.004 Hz to 9 kHz using internal oscillators ►AC ambient light rejection: 78 dB up to 100 Hz ►400 mA total LED peak drive current ►Individual ambient cancellation DAC at TIA input with 9-bit control up to 300 μA ►Individual LED DC cancellation DAC at TIA input with 7-bit control up to 190 μA ►SPI communications supported ►704-byte FIFO

APPLICATIONS

►Wearable health and fitness monitors: heart rate, heart rate variability, and saturation level of pulse oxygen ►Clinical patient monitors: small bed side patient, home portable patient, and small remote patient ►Industrial monitoring: particle, aerosol, and gas detection GENERAL DESCRIPTION The ADPD7008 is a highly integrated analog front end (AFE) designed for measuring various vital signals. The optical channel is designed as an optical transceiver, stimulat- ing up to eight light emitting diodes (LEDs) and measuring the return signal on up to four separate current inputs. The signal chain rejects signal offsets and corruption from asynchronous modulated interference, typically from ambient light, eliminating the need for optical filters or externally controlled DC cancellation circuitry. The data output and functional configuration use a serial port inter- face (SPI) on the ADPD7008. The control circuitry includes flexible LED signaling and synchronous detection, digital filters, digital wave generators, and configurable filters. The ADPD7008 is available in a 2.795 mm × 2.560 mm, 0.40 mm pitch, 36-ball WLCSP.

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REVISION HISTORY

4/2024—Revision 0: Initial Version

Figure 1. Functional Block Diagram

Table 1. Temperature and Power Specifications AVDD = DVDD = IOVDD = 1.8 V, AVDD3 = 3.3 V, and TA = 25°C, unless otherwise noted. Table 2. Performance Specifications

Table 2. Performance Specifications (Continued) IOVDD = 1.7 V to 3.6 V, unless otherwise noted. Table 3. Digital Specifications

Table 4. Timing Specifications Figure 2. SPI Timing Diagram

Table 5. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. junction to case thermal resistance. Table 6. Thermal Resistance 1 The thermal resistance values are defined as per the JESD51-12 standard. sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. are for characterization only. Table 7. ADPD7008, 36-Ball WLCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 3. Pin Configuration, Top View Table 8. Pin Function Descriptions D3 AVDD Power 1.8 V Analog Power Supply. C5 AVDD3 Power 3.3 V Analog Power Supply. F5 AGND Power Analog Ground. D2 DVDD Power 1.8 V Digital Power Supply. D1 DGND Power Digital Ground. C3 IOVDD Power Input and Output Power Supply. E3 VREF1 Analog ADC 1 Reference. F4 VREF2 Analog ADC 2 Reference. F3 VC1 Analog Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus. F1 IN1 Analog Current Input 1. E1 IN2 Analog Current Input 2. F2 IN3 Analog Current Input 3. E2 IN4 Analog Current Input 4. A6 LED1A Analog LED Driver 1A. B5 LED1B Analog LED Driver 1B. C4 LED1C Analog LED Driver 1C. A5 LED1D Analog LED Driver 1D. B4 LED2A Analog LED Driver 2A. A4 LED2B Analog LED Driver 2B. B3 LED2C Analog LED Driver 2C. A3 LED2D Analog LED Driver 2D.

Table 8. Pin Function Descriptions (Continued) A2 CS Digital SPI Chip Select Input. A1 SCLK Digital SPI Clock Input. B1 MISO Digital SPI Controller Input and Target Output. B2 MOSI Digital SPI Controller Output and Target Input. C1 GPIO0 Digital General-Purpose Input and Output 0. C2 GPIO1 Digital General-Purpose Input and Output 1.

optical measurement path (PPG) measurement path. dynamic range in different application scenarios. ment path. The acquisition data can be stored in a 704-byte FIFO. parameters for each time slot are highly configurable. Table 9. Sources of Low Frequency Clock (LFCLK) and Timer Clock1

1 MHz External

3 N/A

Figure 14. Time Slot Allocation

The analog inputs can be driven single-ended or in differential pairs. programmable timing, and block averaging. provide a combined maximum LED current of 400 mA. subtraction, or digital algorithms. reducing the effect of ambient light on the measured signal. ous sampling of four sensors. pair is used as two single-ended inputs or as a differential pair. only support a single-ended input. slots where they are enabled. of a time slot in which the input is selected. Figure 15. Switch Matrix Block Diagram light rejection through an external algorithm. Use the AMBIENT_CANCELLATION_x bits to choose the mode.

first, followed by the Channel 2 data. Figure 17 shows the PPG data format in the FIFO. Figure 17. PPG Data Format 10-bit OSC_960K_FREQ_ADJ bits. by the chip, and the user must not take any additional steps. time slots, such as LED timing and integration times.

32 MHz oscillator is enabled automatically by the low speed state

oscillator calibration routine. enable one of the GPIO inputs using the GPIO_PIN_CFGx bits. it must be kept running continuously for proper device operation.

  1. Set OSC_CAL_ENABLE = 1 to enable the oscillator calibration
  2. Configure a GPIO to support the time stamp input using the

to provide the time stamp using the TIMESTAMP_ GPIO bits.

  1. Configure the ADPD7008 for operation and enable the low
  2. If the TIMESTAMP_SLOT_DELTA function is desired, start the

frequency oscillator calibration.

  1. Set the CAPTURE_TIMESTAMP bit to 1 to enable the capture
  2. The host provides the initial time stamp trigger on the selected

GPIOx at an appropriate time.

  1. The CAPTURE_TIMESTAMP bit is cleared when the timestamp

enabled. Reenable the capture if necessary.

  1. The host provides a subsequent time stamp trigger on the

selected GPIO at an appropriate time.

  1. The number of low frequency oscillator cycles that occurred

determine the arrival time of the samples currently in the FIFO. OSC_960K_FREQ_ADJ value accordingly.

  1. Set OSC_CAL_ENABLE = 1 to enable the oscillator calibration
  2. Write 1 to the OSC_32M_CAL_START bit.
  3. The ADPD7008 automatically powers up the high frequency
  4. The device automatically waits for the high frequency oscillator
  5. An internal counter automatically counts the number of 32 MHz

960 kHz low frequency oscillator.

  1. The OSC_32M_CAL_COUNT bits update with the final count.
  2. The 32 MHz oscillator automatically powers down following

calibration unless time slots are active.

  1. The device resets the OSC_32M_CAL_START bit indicating the

circuitry is disabled by default. operations and is controlled by the OP_MODE bit. Table 11. OP_MODE Bit Setting Descriptions 000 Standby All operations stopped. Time slot actions reset.

001 Go Transitioning to this state from standby mode

starts time slot operations.

Table 11. OP_MODE Bit Setting Descriptions (Continued)

011 ADC test

101 Repeat

OPMODE register (see Register 0x010 in Table 15). ADC, all of the pulse generators, and the state machine. and time slot regions begin. The ADPD7008 uses an SPI to communicate with other devices. status bytes at the end of a FIFO packet. data size for their host needs. exceeds the threshold in the middle of any write of complete data. Instead, the INT_FIFO_TH bit is set at the next write to the FIFO. data to the FIFO. Figure 18 shows the data in the FIFO. Figure 18. FIFO Threshold Interrupt Example until they are either manually or automatically cleared. is automatically cleared when any matching FIFO register is read. manually clear these interrupts. with a wraparound every time the time slot sequence completes.

which can result in the highest achievable SNR levels. Figure 21. Signal Path for Digital Integration Mode integration mode is shown in the timing diagram in Figure 22. two-region digital integration mode is shown in Figure 23. TIA_CONFIG is the TIA configuration. BUF_GAIN is the buffer gain. these bits. The TIA gain setting is independent of these settings. Table 12. Bit Settings for AFE Path in Digital Integration Mode configuration with a buffer gain = 2. automatically calculated in digital integration mode. time is essential for the ambient fine loop update.

Figure 25. Timing of OSRAM FIREFLY CT DBLP31.12 (Green LED) for the analog input interfaces. fully guarded by the ground plane. away from other digital or noisy signals.

Table 15. Register Summary

Table 15. Register Summary (Continued)

Table 16. Register Details underflow, and FIFO threshold interrupt status bits. is not written to the FIFO due to lack of space. is read if the INT_ACLEAR_FIFO bit is set. this field is a status bit and is not sent to interrupt. the number of bytes in the FIFO. Channel 1 TIA saturates during Time Slot L. Channel 1 TIA saturates during Time Slot K. Channel 1 TIA saturates during Time Slot J. Channel 1 TIA saturates during Time Slot I. Channel 1 TIA saturates during Time Slot H. Channel 1 TIA saturates during Time Slot G.

Table 16. Register Details (Continued) Channel 1 TIA saturates during Time Slot F. Channel 1 TIA saturates during Time Slot E. Channel 1 TIA saturates during Time Slot D. Channel 1 TIA saturates during Time Slot C. Channel 1 TIA saturates during Time Slot B. Channel 1 TIA saturates during Time Slot A. Channel 2 TIA saturates during Time Slot L. Channel 2 TIA saturates during Time Slot K. Channel 2 TIA saturates during Time Slot J. Channel 2 TIA saturates during Time Slot I. Channel 2 TIA saturates during Time Slot H. Channel 2 TIA saturates during Time Slot G. Channel 2 TIA saturates during Time Slot F.

Channel 2 TIA saturates during Time Slot E. Channel 2 TIA saturates during Time Slot D. Channel 2 TIA saturates during Time Slot C. Channel 2 TIA saturates during Time Slot B. Channel 2 TIA saturates during Time Slot A. number of bytes in the FIFO exceeds this value. FIFO_TH interrupt each time the FIFO is read.

8 OSC_32M_EFUSE_CTRL Enables the high frequency oscillator frequency

0x00A OSC32M_CAL 15 OSC_32M_CAL_START Start high frequency oscillator calibration cycle.

oscillator calibration cycle. (defaults to GPIO0) causes a time stamp capture. This bit is cleared when the time stamp occurs.

11 OSC_960K_EFUSE_CTRL Enables the frequency oscillator frequency

and high frequency calibration circuits. (timer clock frequency)/(TIMESLOT_PERIOD_x). to match the real clock frequency. kHz). Timer clock also uses this as source.

MHz) from the high frequency oscillator. 00: uses GPIO0 for an alternate clock. 01: uses GPIO1 for an alternate clock. 5 LP_MODE_SLEEP Enable the low power mode during the sleep state. useful for external sample triggers. 0: starts first time slot sequence on go. 1: sleep before first time slot sequence on go.

3 RANDOM_SLEEP Enables random sleep linear feedback shift

up is varied ±7 cycles with the average being 0.

2 TM_CLK_GPIO_SEL Selects low frequency clock between 960 kHz

0001: PPG Time Slot Sequence A. 0010: PPG Time Slot Sequence AB. 0011: PPG Time Slot Sequence ABC. 0100: PPG Time Slot Sequence ABCD.

0101: PPG Time Slot Sequence ABCDE. 0110: PPG Time Slot Sequence ABCDEF. 0111: PPG Time Slot Sequence ABCDEFG. 1000: PPG Time Slot Sequence ABCDEFGH. 1001: PPG Time Slot Sequence ABCDEFGHI. 1010: PPG Time Slot Sequence ABCDEFGHIJ. 1011: PPG Time Slot Sequence ABCDEFGHIJK. 1100: PPG Time Slot Sequence ABCDEFGHIJKL. 001: operate selected time slots. 101: Repeat selected time slots without sleep. sequences without going to sleep between. the Interrupt Channel X function.

14 INTX_EN_FIFO_UFLOW FIFO underflow Interrupt enable for Interrupt

13 INTX_EN_FIFO_OFLOW FIFO overflow interrupt enable for Interrupt

the Interrupt Channel Y function.

14 INTY_EN_FIFO_UFLOW FIFO underflow interrupt enable for Interrupt

13 INTY_EN_FIFO_OFLOW FIFO overflow Interrupt enable for Interrupt

8 ENA_STAT_LEVX Enables Level 0 and Level 1 interrupt status byte

7 ENA_STAT_LEV1 Enables Level 1 interrupt status byte lower. Interrupt 1 for PPG Time Slot A to Time Slot H. 6 ENA_STAT_LEV0 Enables Level 0 interrupt status byte lower. Interrupt 0 for PPG Time Slot A to Time Slot H.

5 ENA_SEQ_NUM Enables the 4-bit sequence number for the time

of differential). Only shorts if PAIR34 is 1. together if configured as differential pair). 0x4: odd connected to Cathode 1. Even floating. 0x8: odd floating. Even connected to Cathode 1. of differential). Only shorts if PAIR12 is 1. together if configured as differential pair). 0x4: odd connected to Cathode 1. Even floating. 0x8: odd floating. Even connected to Cathode 1. 0: cathode set to AVDD during sleep. 1: cathode set to GND during sleep. 10: cathode floating during sleep. 0: uses as two single-ended inputs. 1: uses as a differential pair. 0: uses as two single-ended inputs. 1: used as a differential pair.

000: disabled (tristate, input buffer off). 101: pull-down only—inverted. 000: disabled (tristate, input buffer off). 101: pull-down only—inverted. 0x08: LED1x amplifier enable. 0x09: LED2x amplifier enable. 0x0C: any LED amplifier enable. 0x16: low frequency oscillator output. 0x17: 32 MHz oscillator output.

0x31: Time Slot A LED pulse. 0x32: Time Slot B LED pulse. 0x33: Time Slot C LED pulse. 0x34: Time Slot D LED pulse. 0x35: Time Slot E LED pulse. 0x36: Time Slot F LED pulse. 0x37: Time Slot G LED pulse. 0x38: Time Slot H LED pulse. 0x39: Time Slot I LED pulse. 0x3A: Time Slot J LED pulse. 0x3B: Time Slot K LED pulse. 0x3C: Time Slot L LED pulse. 0x3F: Time Slot x LED pulse. 0x40: Time Slot A modulation pulse. 0x41: Time Slot B modulation pulse. 0x42: Time Slot C modulation pulse. 0x43: Time Slot D modulation pulse. 0x44: Time Slot E modulation pulse. 0x45: Time Slot F modulation pulse. 0x46: Time Slot G modulation pulse. 0x47: Time Slot H modulation pulse. 0x48: Time Slot I modulation pulse. 0x49: Time Slot J modulation pulse. 0x4A: Time Slot K modulation pulse. 0x4B: Time Slot L modulation pulse. 0x4F: Time Slot x modulation pulse. 0x50: output data cycle occurred in Time Slot A. 0x51: output data cycle occurred in Time Slot B. 0x52: output data cycle occurred in Time Slot C. 0x53: output data cycle occurred in Time Slot D. 0x54: output data cycle occurred in Time Slot E. 0x55: output data cycle occurred in Time Slot F. 0x56: output data cycle occurred in Time Slot G. 0x57: output data cycle occurred in Time Slot H. 0x58: output data cycle occurred in Time Slot I.

0x59: output data cycle occurred in Time Slot J. 0x5A: output data cycle occurred in Time Slot K. 0x5B: output data cycle occurred in Time Slot L. 0x5F: output data cycle occurred in any time slot. identical to those described in the GPIOOUT1 bits. 0: time stamp trigger is rising edge. 1: time stamp trigger is falling edge. 00: uses GPIO0 for time stamp (default). 01: uses GPIO1 for time stamp. trigger samples rather than the period counter. 01: uses GPIO1 for external synchronization. and cause shadow registers to update from fuses. The write to this register completes normally.

oscillator operating for eFuse block to operate. 6 LOW_IOVDD_EN Set to 0x0 if a IOVDD of 3 V or higher is used. 3 V because the typical value of IOVDD is 1.8 V. 0x160 TS_CTRL_C 000: multiplexed one region digital integrate mode. 0x180 TS_CTRL_D 001: multiplexed two region digital integrate mode. 0x1A0 TS_CTRL_E 010: one region digital integrate mode. 0x1C0 TS_CTRL_F 011: two region digital integrate mode. 0x1E0 TS_CTRL_G 100: direct sample mode. 0x200 TS_CTRL_H 101: reserved. 0x220 TS_CTRL_I 110: reserved. 0x240 TS_CTRL_J 111: reserved. 0x161 TS_PATH_C 0: disables the ambient cancellation loop. 0x181 TS_PATH_D 1: enables coarse and fine loop. 0x1A1 TS_PATH_E 10: enables coarse loop only. 0x1C1 TS_PATH_F 11: enables MCU control. AFE_INT_C_BUF for the active time slot.

0x241 TS_PATH_J 0x20: TIA, buffer, and ADC (2× TIA gain). 0x261 TS_PATH_K 0x28: TIA buffer, and ADC (1× TIA gain). 0x281 TS_PATH_L 0x35: buffer and ADC. connection between Input 4 and Channel 4. connection between IN3 and Channel 4. connection between IN2 and Channel 4. connection between IN1 and Channel 4. single-ended or differentially based on PAIR34.

single-ended or differentially based on PAIR12. single-ended or differentially based on PAIR12. 0x163 CATHODE_C 000: float inputs. 0x183 CATHODE_D 001: precondition to VC1. 0x1A3 CATHODE_E 010: reserved. 0x1C3 CATHODE_F 011: reserved. 0x1E3 CATHODE_G 100: precondition with TIA input. 0x203 CATHODE_H 101: precondition with TIA_VREF. 0x223 CATHODE_I 110: precondition by shorting differential pair. 1: alternate odd/even time slots. 10: pulse to alternate value using modulate pulse.

1 and also Channel 2 if Channel 2 is enabled. 0x184 AFE_TRIM1_D 0: buffer gain = 1 (RFB/RIN = 200 kΩ/200 kΩ). 0x1A4 AFE_TRIM1_E 1: buffer gain = 2 (RFB/RIN = 200 kΩ/100 kΩ). 0x1C4 AFE_TRIM1_F 10: buffer gain = 1 (RFB/RIN = 100 kΩ/100 kΩ). 0x1E4 AFE_TRIM1_G 11: buffer gain = 2 (RFB/RIN = 100 kΩ/50 kΩ). 0x224 AFE_TRIM1_I 0: no pulsing. 0x244 AFE_TRIM1_J 1: pulse VREF based on modulate pulse. 11: modulate TIA_VREF = 1.265 V.

µA to 300 µA with 0.6 µA/LSB. µA to 300 µA with 0.6 µA/LSB. LED2C, or LED2D output. Set to 0 to disable.

to 200 mA for values between 0x01 and 0x7F. LED1C, or LED1D output. Set to 0 to disable. to 200 mA for values between 0x01 and 0x7F. 0x169 LED_MODE_C 00: drives LED on Output LED2A. 0x189 LED_MODE_D 01: drives LED on Output LED2B. 0x1A9 LED_MODE_E 10: drives LED on Output LED2C. 0x1C9 LED_MODE_F 11: drives LED on Output LED2D. 0x209 LED_MODE_H 00: drives LED on Output LED1A. 0x229 LED_MODE_I 01: drives LED on Output LED1B. 0x249 LED_MODE_J 10: drives LED on Output LED1C. 0x269 LED_MODE_K 11: drives LED on Output LED1D. NUM_INT_x Number of ADC cycles or acquisition width. integration. A setting of 0 is not allowed. setting of 0 is not allowed.

the precondition. No connection modulation. the precondition value between pulses. μA to 300 μA with 0.6 μA/LSB.

μA to 300 μA with 0.6 μA/LSB. THRESH0_SHIFT_x Shift for threshold compare Level Interrupt 0. of four pulses. The LSB maps to the first pulse.

of four pulses. The LSB maps to the first pulse. pulses. The LSB maps to the first pulse. 0x172 THRESH_CFG_C 0: set when less than the threshold. 0x192 THRESH_CFG_D 1: set when more than the threshold. 0x1D2 THRESH_CFG_F 0: off (no comparison). 0x1F2 THRESH_CFG_G 1: compare to signal. 0x212 THRESH_CFG_H 10: compare to lit. 0x232 THRESH_CFG_I 11: compare to dark. 0x292 THRESH_CFG_L 0: set when less than the threshold. 1: set when more than the threshold. from the ADC value for Channel 1.

from the ADC value for Channel 2. 0x157 DECIMATE_B 00: only Channel 1 enabled. 0x177 DECIMATE_C 01: Channel 1 and Channel 2 enabled.

per (SUBSAMPLE_RATIO_x) time slot sequence. sample rate/(SUBSAMPLE_RATIO_x). from the ADC value for Channel 3.

from the ADC value for Channel 4. THRESH1_SHIFT_x Shift for threshold compare Level Interrupt 1.

©2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. 0 | 71 of 71 Package Drawing (Option) Package Type Package Description CB-36-11 WLCSP 36-Ball Wafer Level Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: March 25, 2024 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADPD7008BCBZR7 -40°C to +85°C 36-ball WLCSP (2.795 mm x 2.560 mm x 0.595 mm) Reel, 1500 CB-36-11 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-ADPD7000Z Evaluation Board 1 Z = RoHS-Compliant Part.