DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 34

Technical content

PPG Optical Sensor Module with Integrated Red/IR Emitters and AFE Data Sheet ADPD144RI Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

2.8 mm × 5.0 mm module with integrated optical components 660 nm LED, 880 nm IR LED, and photodiode Fully integrated AFE, ADC, LED drivers, and timing core Custom optical package for use under a glass window Programmable 2-channel, 8.5 mA to 370 mA LED drivers Provision to use external LED emitters Low power Specifically designed for ultralow direct optical reflections Independent AFE settings per channel I2C data and control interface Burst accumulator enabling 20 bits per sample period Sample to sample accumulator enabling up to 27 bits per data read 16-bit or 32-bit register or FIFO readout per channel

APPLICATIONS

Optical heart rate monitoring Reflective SpO2 measurement GENERAL DESCRIPTION The ADPD144RI is a highly integrated, photometric front end optimized for photoplethysmography (PPG) detection of blood oxygenation (SpO2) by synchronous detection in red and infrared wavelengths. Synchronous measurement allows rejection of both dc and ac ambient light interference with extremely low power consumption. The module combines highly efficient, light emitting diode (LED) emitters and a sensitive 4-channel, deep diffusion photodiode (PD1 to PD4) with a custom application specific integrated circuit (ASIC) in a compact package that provides optical isolation between the integrated LED emitters and the detection photodiodes to improve through tissue, signal-to- noise ratio (SNR). The ASIC consists of a 4-channel analog front end (AFE) with two independently configurable datapaths with separate gain and filter settings, a 14-bit analog-to-digital converter (ADC) with a burst accumulator, two flexible, independently configurable, LED drivers, and a digital control block. The digital control block provides AFE and LED timing, signal processing, and communication. Data output and functional configuration occur over a 1.8 V I 2C interface. FUNCTIONAL BLOCK DIAGRAM ANALOG BLOCK TIME SLOT A DATA TIME SLOT B DATAAFE CONFIGURATION, TIME SLOT A AFE CONFIGURATION, TIME SLOT B SDA SCL INT DGND AGND VREF 1µF VDD1 VDD2 ADPD144RI 14-BIT ADC LED2 DRIVER LED2 LEVEL AND TIMING CONTROLLED1 DRIVER LED1 LEVEL AND TIMING CONTROL LGND VLED LEDX2 LEDX1 TIA VBIAS AMBIENT LIGHT REJECTION AFE: SIGNAL CONDITIONING AFE GAIN TIA VBIAS AMBIENT LIGHT REJECTION AFE GAIN TIA VBIAS AMBIENT LIGHT REJECTION AFE GAIN TIA VBIAS AMBIENT LIGHT REJECTION AFE GAIN CH1 CH2 CH3 CH4 PD3 PD1 PD4 PD2 660nm 880nm LEDs DIGITAL INTERFACE AND CONTROL 14060-001 Figure 1.

Rev. A | Page 2 of 34 TABLE OF CONTENTS Mechanical Considerations for Covering the ADPD144RI . 22

REVISION HISTORY

2/2019—Revision A: Initial Version

Rev. A | Page 3 of 34 SPECIFICATIONS The voltage applied at the VDD1 pin and VDD2 pin (VDD) = 1.8 V and TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY CURRENT VDD1, VDD2 = 1.8 V Peak Supply Current IVDD_PEAK 4-channel operation 9.3 mA Standby Mode Current IVDD_STANDBY 3.5 µA Average Supply Current IVDD_AVG See the Calculating the Total Power Consumption section µA Supply Current LED offset = 25 µs, LED period = 19 µs, LED peak current = 25 mA, 4 channels active

1 Pulse 100 Hz data rate, Time Slot A only 106 µA

100 Hz data rate, Time Slot B only 94 µA

100 Hz data rate, Time Slot A and Time Slot B 151 µA

10 Pulses 100 Hz data rate, Time Slot A only 258 µA

100 Hz data rate, Time Slot B only 246 µA

100 Hz data rate, Time Slot A and Time Slot B 455 µA

LED SUPPLY VOLTAGE (VLED) CURRENT Average Supply Current VLED ILED_AVG See the Calculating the Total Power Consumption section VLED Supply Current, Average Peak LED current = 100 mA, LED pulse width = 3 µs

1 Pulse 50 Hz data rate 15 µA

100 Hz data rate 30 µA

200 Hz data rate 60 µA

10 Pulses 50 Hz data rate 150 µA

100 Hz data rate 300 µA

200 Hz data rate 600 µA

Table 2. Parameter Test Conditions/Comments Min Typ Max Unit SATURATION ILLUMINANCE1 Blackbody color temperature (T = 5800 K)2 Direct Illumination Transimpedance amplifier (TIA) gain = 25 kΩ 48 kLux TIA gain = 50 kΩ 24 kLux TIA gain = 100 kΩ 10 kLux TIA gain = 200 kΩ 4 kLux Through Skin TIA gain = 25 kΩ 140 kLux TIA gain = 50 kΩ 70 kLux TIA gain = 100 kΩ 31 kLux TIA gain = 200 kΩ 12 kLux DATA ACQUISITION ADC Resolution Single pulse 14 Bits Sample Width 64 pulses to 255 pulses 20 Bits Output Data Width 64 pulses to 255 pulses, 128 samples averaged 27 Bits Sampling Frequency (fSAMPLE) Lowest Setting Adjustable via Register 0x12 setting (see Table 18) 0.122 Hz Highest Setting Time Slot B only, one pulse per sample, sleep time = 200 µs 3.48 kHz Minimum Sleep Time (tSLEEP_MIN) Minimum sleep time required between samples 200 µs

Rev. A | Page 4 of 34 Parameter Test Conditions/Comments Min Typ Max Unit LEDs LED Peak Current Setting Adjustable via Register 0x23 through Register 0x25 settings (see Table 14) 8.5 370 mA Dominant Wavelength Red LED (LED1) Forward current of the diode (IF) = 20 mA 660 nm Infrared (IR) LED (LED2) IF = 100 mA 880 nm Radiant Flux Red LED, IF = 20 mA at 25°C 9 mW IR LED, IF = 100 mA at 25°C 33 mW PHOTODIODE3 Responsivity Wavelength, λ = 660 nm (Channel 1, Channel 2, Channel 3) 0.36 A/W Wavelength, λ = 660 nm (Channel 4) 0.31 A/W Wavelength, λ = 880 nm (Channel 1, Channel 2, Channel 3) 0.25 A/W Wavelength, λ = 880 nm (Channel 4) 0.28 A/W Active Area Individual Photodiodes Per channel 0.3 mm2 Total Active Area 1.2 mm2 POWER SUPPLY VOLTAGES The ADPD144RI does not require a specific power-up sequence VDD Applied at the VDD1 pin and VDD2 pin 1.7 1.8 1.9 V VLED4, 5 Applied at the VLED pin 3 3.5 4.3 V Power Supply Rejection Ratio (PSRR) VDD = 1.8 V −37 dB OPERATING TEMPERATURE RANGE −40 +85 °C 1 Saturation illuminance refers to the amount of light that saturates the analog signal path. Actual results may vary by factors of up to 2× from the typical specifications. As a point of reference, Air Mass 1.5 (AM1.5) sunlight (brightest sunlight) produces 100 kLux. 2 Blackbody color temperature (T = 5800 K) approximates solar radiation (sunlight). 3 The photodiode layout is shown in Figure 11. 4 VLED must be sufficient to source the maximum IF required and to keep the internal driver and current sink compliance voltage at least 0.2 V above LGND. For the integrated LEDs, this voltage appears at the LEDX1 and LEDX2 pins. 5 See Figure 8 for the current limitation at the minimum VLED. I2C DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS (SCL, SDA) Input Voltage High Level VIH 0.7 × VDD 3.6 V Low Level VIL 0.3 × VDD V Input Current High Level IIH −10 +10 µA Low Level IIL −10 +10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS INT Output Voltage High Level VOH 2 mA high level output current VDD − 0.5 V Low Level VOL 2 mA low level output current 0.5 V SDA Output Low Level Voltage VOL1 2 mA low level output current 0.2 × VDD V Low Level Current IOL VOL1 = 0.6 V 6 mA

Figure 2. I2C Timing Diagram

1 The absolute maximum voltage allowable between VLED and LGND is the

their absolute maximum voltage. PCB thermal design is required. is why a separate θJA is given for each die type in Table 6. Table 6. Thermal Resistance

1 Thermal impedance simulated values are based on JEDEC 2s2p and two

thermal vias. See JEDEC JESD-51. Figure 3. Recommended Soldering Profile Table 7. Recommended Soldering Profile

  1. LEDX1, LEDX2 DO NOT CONNECT TO THESE

PINS UNLESS DRIVING EXTERNAL LEDs. Figure 4. Pin Configuration Table 8. Pin Function Descriptions 2 SDA Digital input and output Serial Address and Data. 3 DGND Supply Digital Ground. 4 AGND Supply Analog Ground. 5 VDD1 Supply 1.8 V Supply Input. 6 VREF Analog reference Voltage Reference. Bypass with a 0.7 µF to 4 µF capacitor to AGND. 7 VLED Supply Integrated LEDs Anode Supply Voltage. 8 LEDX2 Analog output External LED2 Cathode. Do not connect this pin unless driving external LEDs. 9 LEDX1 Analog output External LED1 Cathode. Do not connect this pin unless driving external LEDs. 10 VDD2 Supply 1.8 V Supply Input. 11 INT Digital input and output Interrupt Input and Output. 12 SCL Digital input Serial Clock for I2C Communication.

registers directly or through a first in, first out (FIFO) buffer. different forward voltages required by different LED families.

  1. ALL DIMENSIONS ARE TYPICAL AND SHOWN IN mm.
  2. PHOTODIODE AREA: 1.2mm2 (0.3mm2 PER PD).

Figure 11. Optical Component Locations

wavelength independent calibration. consumption for the application. Register 0x30, Register 0x31, Register 0x35, and Register 0x36. in which these slots are both enabled. Pulse Offset is the delay before the first pulse in each sample. Pulse Count is the total number of pulses within a time slot. pulse energy and place the data on the internal bus. Time Slot B (t2) is fixed at 20 µs. the number of pulses for Time Slot B. Figure 12. Time Slot Timing Diagram Table 9. Recommended AFE and LED Timing Configuration

ALL REGISTER VALUES ARE RETAINED. DEVICE IS FULLY POWERED IN THIS MODE. DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE. Figure 15. State Machine Operation Flowchart the device in standby mode, write 0x0 to Register 0x10, Bits[1:0]. The device powers up in standby mode. write 0x1 to Register 0x10, Bits[1:0]. sample mode, write 0x2 to Register 0x10, Bits[1:0].

  1. LED pulse and sample. The ADPD144RI pulses an LED

where nPULSE is user configurable between 1 and 255.

  1. Intersample averaging. If desired, the logic can average
  2. Data read. The host processor reads the converted results

from the data register or the FIFO.

  1. Repeat. The sequence has a few different loops that enable

close in time relative to each other.

16 BITS

  1. NA AND NB 16 BITS[14 + LOG2(nB)] BITS

14 BITS14 BITS

Figure 16. ADPD144RI Data Flow

Rev. A | Page 13 of 34 ADJUSTABLE SAMPLING FREQUENCY Register 0x12 sets a divider from the 32 kHz clock that determines the sampling frequency of the ADPD144RI. The maximum sampling frequency (fSAMPLE, MAX) is determined by the sample periods for Time Slot A and Time Slot B plus the minimum sleep time. f SAMPLE, MAX = 1/(tA + t1 + tB + t2 + tSLEEP_MIN) (2) where tSLEEP_MIN is the minimum sleep time required between samples. See the Pulse Timing section for the definitions of tA, t1, tB, and t2. If a given time slot is not in use, elements from that time slot do not factor into the calculation. For example, if Time Slot A is not in use, t A and t1 do not add to the sampling period, and the maximum sampling frequency is calculated as follows: fSAMPLE, MAX = 1/(tB + t2 + tSLEEP_MIN) (3) External Sync for Sampling The ADPD144RI provides an option to use an external sync signal to trigger the sampling periods. This external sample sync signal is provided on the INT pin. This functionality is controlled by Register 0x4F, Bits[2:1]. When enabled, a rising edge on the selected input specifies when the next sample cycle occurs. When triggered, there is a delay of one to two internal sampling clock (32 kHz) cycles, and then the normal start-up sequence occurs. This sequence is the same as if the normal sample timer provided the trigger. To enable the external sync signal feature, use the following procedure: 1. Write 0x1 to Register 0x10 to enter program mode. 2. Write 1 to Register 0x4F, Bit 2 to select the external sync using the INT pin. Enable the INT pin input buffer by writing 1 to Register 0x4F, Bit 1. 3. Write 0x4000 to Register 0x38. 4. Write 0x0002 to Register 0x10 to start the sampling operations. 5. Apply the external sync signal on the INT pin at the desired rate (sampling occurs at that rate). As with normal sampling operations, read the data using the FIFO or the data registers. The maximum frequency constraints (f SAMPLE, MAX) still apply when externally triggering the sample function. LED Pulse and Sample At each sampling period, the selected LED driver drives a series of LED pulses in each time slot as shown in Figure 13. The magnitude, duration, and number of pulses are programmable over the I2C interface. Each LED pulse coincides with a sensing period of the AFE. During the AFE sensing period, the charge acquired on the photodiode from ambient light is subtracted from the photodiode charge of the synchronous LED pulse. The combined signals effectively null the contribution of ambient light. During each pulse period, the photodiode output is integrated and converted to a digital value by the 14-bit ADC. Each subsequent conversion within a time slot is summed with the previous result. Up to 255 pulse values from the ADC can be summed in an individual time slot up to a maximum of 20 bits. LED DRIVER OPERATION Integrated LEDs The ADPD144RI features integrated 660 nm (LED1) and 880 nm (LED2) LED emitters optimized for SpO2 measurement. The anodes of the integrated LEDs require connection to a power supply via the VLED pin, which allows flexibility of the supply voltage for the LEDs as well as decoupling. A capacitor (CVLED), placed close to the VLED pin, provides additional pulse current to the LEDs in pulse mode. Without this capacitor, output impedance of the LED supply can adversely affect the pulsed performance of the LEDs. Selection of the correct C VLED value is covered in the Determining CVLED section. The LEDX1 and LEDX2 pins are external connections to the LED drivers and cannot be connected when using the integrated LED emitters. It is not possible to combine integrated and external LEDs.

effectively disables the integrated LED emitters on the ADPD144RI. Figure 17. Connection of External LEDs completely cease proper operation. LEDX2 driver pins is recommended. improve signal noise shaping. the effective sampling rate. used to integrate the noise while maintaining 16-bit resolution. user can select from 2, 4, 8 … up to 128 samples to be averaged. other time slot can be read from the output registers.

Rev. A | Page 17 of 34 READING DATA The ADPD144RI provides multiple methods for accessing the sample data. Each time slot can be independently configured to provide data access using the FIFO or the data registers. Interrupt signaling is also available to simplify timely data access. The FIFO is available to loosen the system timing requirements for data accesses. Reading Data Using the FIFO The ADPD144RI includes a 128-byte FIFO memory buffer that can be configured to store data from either or both time slots. Register 0x11 selects the kind of data from each time slot to be written to the FIFO. Note that both time slots can be enabled to use the FIFO, but only if the output data rate of the time slots is the same. Output Data Rate = f SAMPLE/NX (4) where: NX is the averaging factor for each time slot (NA for Time Slot A and NB for Time Slot B). NA = NB must be true to store data from both time slots in the FIFO. Data packets are written to the FIFO at the output data rate. A data packet for the FIFO consists of a complete sample for each enabled time slot. Data for each photodiode channel can be stored as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of data per sample, depending on the mode and data format. To ensure that data packets are intact, new data is only written to the FIFO if there is sufficient space for a complete packet. Any new data that arrives when there is not enough space is lost. The FIFO continues to store data when sufficient space exists. Always read FIFO data in complete packets to ensure that data packets remain intact. The number of bytes currently stored in the FIFO is available in Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also available and automatically generates when a specified amount of data is written to the FIFO. To read data from the FIFO using an interrupt-based method, use the following procedure: 1. In program mode, configure time slots as required. 2. Set data format for each time slot in Register 0x11. 3. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the interrupt threshold. A recommended value for this is the number of 16-bit words in a data packet, minus 1. Setting FIFO_THRESH generates an interrupt when there is at least one complete packet in the FIFO. 4. Enable the FIFO interrupt by writing a 0 to FIFO_INT_MASK in Register 0x01, Bit 8. Configure the interrupt pin (INT) by writing the appropriate value to the bits in Register 0x02. 5. Enter normal operation mode by setting Register 0x10 to 0x2. 6. When an interrupt occurs, complete the following steps: a. There is no requirement to read the FIFO_SAMPLES register because the interrupt is generated only if there is one or more full packet. Optionally, the interrupt routine can check for the presence of more than one available packet by reading this register. b. Write 1 to FIFO_ACCESS_ENA, Register 0x5F , Bit 0 twice in two consecutive write operations. c. Read a complete packet using one or more multiword accesses using Register 0x60. Reading the FIFO automatically frees the space for new samples. d. Write 0 to FIFO_ACCESS_ENA, Register 0x5F , Bit 0. The interrupt automatically clears when enough data is read from the FIFO to bring the data level below the threshold. To read data from the FIFO in a polling method, use the following procedure: 1. In program mode, set the configuration of the time slots as desired for operation. 2. Write Register 0x11 with the desired data format for each time slot. 3. Enter normal operation mode by setting Register 0x10 to 0x02. Next, begin the polling operations using the following procedure: 1. Wait for the polling interval to expire. 2. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]). 3. If FIFO_SAMPLES ≥ the packet size, read a packet using the following steps: a. Write 1 to FIFO_ACCESS_ENA, Register 0x5F , Bit 0 twice in two consecutive write operations. b. Read a complete packet using one or more multiword accesses via Register 0x60. Reading the FIFO automatically frees the space for new samples. c. Write 0 to FIFO_ACCESS_ENA, Register 0x5F , Bit 0. d. Repeat Step 1. When a mode change is required, or any other disruption to normal sampling is necessary, the FIFO must be cleared. Use the following procedure to clear the state and empty the FIFO: 1. Enter program mode by setting Register 0x10 to 0x1. 2. Write 1 to FIFO_ACCESS_ENA, Register 0x5F , Bit 0 twice in two consecutive write operations. 3. Write 1 to Register 0x00, Bit 15. 4. Write 0 to FIFO_ACCESS_ENA, Register 0x5F , Bit 0.

Rev. A | Page 18 of 34 Reading Data from Registers Using Interrupts The latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. The data value for each photodiode channel is available as a 16-bit value in Register 0x64 through Register 0x67 for Time Slot A, and Register 0x68 through Register 0x6B for Time Slot B. If allowed to reach their maximum value, Register 0x64 through Register 0x6B clip. If Register 0x64 through Register 0x6B saturate, the unsaturated (up to 27 bits) values for each channel are available in Register 0x70 through Register 0x77 for Time Slot A and Register 0x78 through Register 0x7F for Time Slot B. Sample interrupts are available to indicate when the registers are updated and can be read. To use the interrupt for a given time slot, use the following procedure: 1. Enable the sample interrupt by writing a 0 to the appropriate bit in Register 0x01. To enable the interrupt for Time Slot A, write 0 to Bit 5. To enable the interrupt for Time Slot B, write 0 to Bit 6. Either or both interrupts can be set. An interrupt is generated when the data registers are updated. 2. Configure the INT pin by writing the appropriate value to the bits in Register 0x02. 3. The interrupt handler must perform the following: a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm which interrupt has occurred. This step is not required if only one interrupt is in use. b. Read the data registers before the next sample can be written. The system must have an interrupt latency and service time that is short enough to respond before the next data update, based on the output data rate. c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the interrupt. If both time slots are in use, it is possible to use only the Time Slot B interrupt to signal when all registers can be read. It is recommended to use the multiword read to transfer the data from the data registers. Reading Data from Registers Without Interrupts If the system interrupt response is not fast or predictable enough to use the interrupt method, or if the INT pin is not used, it is possible to obtain reliable data access by using the data hold mechanism. To guarantee that the data read from the registers is from the same sample time, it is necessary to prevent the update of samples while reading the current values. The method for performing register reads without interrupt timing is as follows: 1. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD bits, Register 0x5F , Bit 1 and Bit 2, respectively, for the time slot requiring access (both time slots can be accessed). This write prevents sample updates. 2. Read the registers as desired. 3. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_ DATA_HOLD bits, Register 0x5F , Bit 1 and Bit 2, respectively. Sample updates are allowed again. Because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. CLOCKS AND TIMING CALIBRATION The ADPD144RI uses two internal time bases. A 32 kHz clock provides master timing for the state machine, sets the sample timing, and determines the output data rate. A separate 32 MHz clock controls the digital processing engine of the ASIC. Both clocks are internally generated and exhibit device to device variation of approximately 10% (typical). Both clocks can be calibrated to provide accurate timing for applications that require precise timing reference. Calibrating the 32 kHz Clock The 32 kHz clock provides the coarse timing reference for sampling time and output data rate. For applications where an accurate time reference is important, such as heart rate measurements, calibrate the 32 kHz clock. To calibrate the clock, take the following steps: 1. Set the sampling frequency to the highest the system can handle, such as 2000 Hz. Because the 32 kHz clock controls sample timing, its frequency is readily accessible via the INT pin. Configure the interrupt by writing 0xC0FF to Register 0x02 and set the interrupt to occur at the sampling frequency by writing 0 to Register 0x01, Bit 5. Monitor the INT pin. The INT pin then pulses at 1/4 the sample frequency. 2. If the monitored interrupt frequency × 4 is less than the set sampling frequency, increase the CLK32K_ADJUST bits, Register 0x4B, Bits[5:0]. If the monitored interrupt frequency × 4 is larger than the set sampling frequency, decrease the CLK32K_ADJUST bits. Repeat Step 2 until the monitored interrupt signal frequency is close enough to the set sampling frequency. Note that the resolution of the 32 kHz clock adjust is 0.6 kHz per LSB.

supply, and ILED_A VERAGE is also the VLED supply current rating. ILED_PEAK is the peak current setting of the LED. supply must support a dc current of 40 mA. Figure 22. Typical Configuration of a LED Pulse Burst Sequence See the following sections for the definitions of these variables. QPROC is an average charge associated with a processing time. Register 0x24, Bits[3:0], respectively, expressed in mA. LEDx_PERIOD is the pulse period expressed in seconds. PULSE_COUNT is the number of pulses. for that respective time slot. whichever LED is selected for Time Slot A. whichever LED is selected for Time Slot B.

Rev. A | Page 21 of 34 OPTIMIZING SNR PER WATT The ADPD144RI offers a variety of parameters that the user can adjust to achieve the best signal. One of the key goals of system performance is to obtain the best system SNR for the lowest total power, which is often referred to as optimizing SNR per watt. In systems where SNR is the primary design goal and power is a secondary concern, there may be a configuration that achieves the same SNR for an overall lower system power. Optimizing for Peak SNR The first step in optimizing for peak SNR is to find a TIA gain and LED level that gives the best performance where the number of LED pulses remains constant. It is important to note that the SNR improves as a square root of the number of pulses averaged together, whereas LED power consumed is directly proportional to the number of LED pulses. For every doubling of the LED pulse count, there is a doubling of the LED power consumed and a 3 dB SNR improvement. As a result, avoid any change in the gain configuration that provides less than 3 dB of improvement for a 2× power penalty. Any TIA gain configuration that provides more than 3 dB of improvement for a 2× power penalty is recommended. If peak SNR is the goal and there is no issue saturating the photodiode with LED current at any gain, the 50,000 TIA gain setting is an optimal choice. After the SNR per pulse per channel is optimized, the user can then increase the number of pulses to achieve the desired system SNR. Optimizing SNR per Watt in a Signal Limited System In practice, optimizing for peak SNR is not always practical. One scenario in which the PPG signal has a poor SNR is the signal limited regime. In this scenario, the LED current reaches an upper limit before the desired dc return level is achieved. Tuning in this case starts where the peak SNR tuning stops. The starting point is nominally a 50,000 gain, as long as the lowest LED current setting of 8 mA does not saturate the photodiode and the 50,000 gain provides enough protection against intense background light. In these cases, use a 25,000 gain as the starting point. The goal of the tuning process is to bring the dc return signal to a specific ADC range, such as 50% or 60%. The ADC range choice is a function of the margin of headroom needed to prevent saturation as the dc level fluctuates over time. The SNR of the PPG waveform is always some percentage of the dc level. If the target level cannot be achieved at the base gain, increase the gain and repeat the procedure. The tuning system may need to place an upper limit on the gain to prevent saturation from ambient signals. Tuning the Pulse Count After the LED peak current and TIA gain are optimized, increasing the number of pulses per sample increases the SNR by the square root of the number of pulses. There are two ways to increase the pulse count. The pulse count registers (Register 0x31, Bits[15:8], and Register 0x36, Bits[15:8]) change the number of pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8], controls the number of internal samples that are averaged together before the data is sent to the output. Therefore, the number of pulses per sample is the pulse count register multiplied by the number of subsequent samples being averaged. In general, the internal sampling rate increases as the number of internal sample averages increase to maintain the desired output data rate. The SNR per watt is most optimal with pulse count values of 16 or less. Above pulse count values of 16, the square root relationship does not hold in the pulse count register. However, this relationship continues to hold when averaged between samples using Register 0x15. Note that increasing the LED peak current increases SNR almost directly proportional to LED power, whereas increasing the number of pulses by a factor of n PULSE results in only a nominal √(nPULSE) increase in SNR. When using the sample sum and average function (Register 0x15), the output data rate decreases by the number of summed samples. To maintain a static output data rate, increase the sample frequency (Register 0x12) by the same factor as that selected in Register 0x15. For example, for a 100 Hz output data rate and a sample sum and average of four samples, set the sample frequency to 400 Hz. TIA ADC Mode The device can be placed in TIA ADC mode, which ties the TIA directly to the ADC, bypassing the analog ambient light rejection block. TIA ADC mode provides a relative measure of the amount of background light present at the input of the device. This mode only measures dc light and does not measure the light returned from the LED pulse. To enter TIA ADC mode, write 0xB065 to Register 0x45 and write 0x0000 to the ADC offset registers, Register 0x18 through Register 0x21. Increasing light causes a decrease in the output values because the TIA is an inverting stage. The data registers then read a relative amount of dc light. On this device, use TIA ADC mode only as a relative measurement. This test looks for devices that have a high resistance between inputs due to solder flux because this resistance manifests itself as an elevated dc current.

Table 13. Register Map

Rev. A | Page 24 of 34 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W1 0x34 LED_DISABLE [15:8] Reserved SLOTB_ LED_DIS SLOTA_ LED_DIS 0x0000 R/W [7:0] Reserved 0x35 SLOTB_ LEDMODE [15:8] SLOTB_LEDMODE[15:8] 0x0320 R/W [7:0] SLOTB_LEDMODE[7:0] 0x36 SLOTB_ NUMPULSES [15:8] SLOTB_NUMPULSES 0x0818 R/W [7:0] Reserved (write 0x13) 0x38 EXT_SYNC_ STARTUP [15:8] Reserved EXT_SYNC_ENA Reserved 0x0000 R/W [7:0] Reserved 0x39 SLOTA_ AFEMODE [15:8] SLOTA_AFEMODE[15:8] 0x22FC R/W [7:0] SLOTA_AFEMODE[7:0] 0x3B SLOTB_ AFEMODE [15:8] SLOTB_AFEMODE[15:8] 0x22FC R/W [7:0] SLOTB_AFEMODE[7:0] 0x42 SLOTA_GAIN [15:8] Reserved 0x1C38 R/W [7:0] Reserved SLOTA_TIA_ IND_EN Reserved (write 0x03) Reserved (write 0x1) SLOTA_TIA_GAIN 0x43 SLOTA_AFE_CON [15:8] SLOTA_AFE_CON[15:8] 0xADA5 R/W [7:0] SLOTA_AFE_CON[7:0] 0x44 SLOTB_GAIN [15:8] Reserved 0x1C38 R/W [7:0] Reserved SLOTB_TIA_ IND_EN Reserved (write 0x03) Reserved (write 0x1) SLOTB_TIA_GAIN 0x45 SLOTB_AFE_CON [15:8] SLOTB_AFE_CON[15:8] 0xADA5 R/W [7:0] SLOTB_AFE_CON[7:0] 0x4B SAMPLE_CLK [15:8] Reserved 0x2612 R/W [7:0] CLK32K_ EN Reserved CLK32K_ADJUST 0x4D CLK32M_ADJUST [15:8] Reserved 0x425E R/W [7:0] CLK32M_ADJUST 0x4E ADC_TIMING [15:8] ADC_TIMING[15:8] 0x0060 R/W [7:0] ADC_TIMING[7:0] 0x4F EXT_SYNC_SEL [15:8] Reserved 0x2090 R/W [7:0] Reserved EXT_ SYNC_SEL INT_IE Reserved 0x50 CLK32M_CAL_EN [15:8] Reserved 0x0000 R/W [7:0] Reserved CLK32M_ CAL_EN Reserved 0x55 TIA_INDEP_GAIN [15:8] Reserved SLOTB_TIA_GAIN_4 SLOTB_TIA_GAIN_3 0x0000 R/W [7:0] SLOTB_TIA_GAIN_2 SLOTA_TIA_GAIN_4 SLOTA_TIA_GAIN_3 SLOTA_TIA_GAIN_2 0x5F DATA_ACCESS_ CTL [15:8] Reserved 0x0000 R/W [7:0] Reserved SLOTB_ DATA_ HOLD SLOTA_ DATA_ HOLD FIFO_ ACCESS_ ENA 0x60 FIFO_ACCESS [15:8] FIFO_DATA[15:8] 0x0000 R [7:0] FIFO_DATA[7:0] 0x64 SLOTA_PD1_16BIT [15:8] SLOTA_PD1_16BIT [15:8] 0x0000 R [7:0] SLOTA_PD1_16BIT [7:0] 0x65 SLOTA_PD2_16BIT [15:8] SLOTA_PD2_16BIT [15:8] 0x0000 R [7:0] SLOTA_PD2_16BIT [7:0] 0x66 SLOTA_PD3_16BIT [15:8] SLOTA_PD3_16BIT [15:8] 0x0000 R [7:0] SLOTA_PD3_16BIT [7:0] 0x67 SLOTA_PD4_16BIT [15:8] SLOTA_PD4_16BIT [15:8] 0x0000 R [7:0] SLOTA_PD4_16BIT [7:0] 0x68 SLOTB_PD1_16BIT [15:8] SLOTB_PD1_16BIT [15:8] 0x0000 R [7:0] SLOTB_PD1_16BIT [7:0] 0x69 SLOTB_PD2_16BIT [15:8] SLOTB_PD2_16BIT [15:8] 0x0000 R [7:0] SLOTB_PD2_16BIT [7:0]

Rev. A | Page 25 of 34 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W1 0x6A SLOTB_PD3_16BIT [15:8] SLOTB_PD3_16BIT [15:8] 0x0000 R [7:0] SLOTB_PD3_16BIT [7:0] 0x6B SLOTB_PD4_16BIT [15:8] SLOTB_PD4_16BIT [15:8] 0x0000 R [7:0] SLOTB_PD4_16BIT [7:0] 0x70 A_PD1_LOW [15:8] SLOTA_PD1_LOW[15:8] 0x0000 R [7:0] SLOTA_PD1_LOW[7:0] 0x71 A_PD2_LOW [15:8] SLOTA_PD2_LOW[15:8] 0x0000 R [7:0] SLOTA_PD2_LOW[7:0] 0x72 A_PD3_LOW [15:8] SLOTA_PD3_LOW[15:8] 0x0000 R [7:0] SLOTA_PD3_LOW[7:0] 0x73 A_PD4_LOW [15:8] SLOTA_PD4_LOW[15:8] 0x0000 R [7:0] SLOTA_PD4_LOW[7:0] 0x74 A_PD1_HIGH [15:8] SLOTA_PD1_HIGH[15:8] 0x0000 R [7:0] SLOTA_PD1_HIGH[7:0] 0x75 A_PD2_HIGH [15:8] SLOTA_PD2_HIGH[15:8] 0x0000 R [7:0] SLOTA_PD2_HIGH[7:0] 0x76 A_PD3_HIGH [15:8] SLOTA_PD3_HIGH[15:8] 0x0000 R [7:0] SLOTA_PD3_HIGH[7:0] 0x77 A_PD4_HIGH [15:8] SLOTA_PD4_HIGH[15:8] 0x0000 R [7:0] SLOTA_PD4_HIGH[7:0] 0x78 B_PD1_LOW [15:8] SLOTB_PD1_LOW[15:8] 0x0000 R [7:0] SLOTB_PD1_LOW[7:0] 0x79 B_PD2_LOW [15:8] SLOTB_PD2_LOW[15:8] 0x0000 R [7:0] SLOTB_PD2_LOW[7:0] 0x7A B_PD3_LOW [15:8] SLOTB_PD3_LOW[15:8] 0x0000 R [7:0] SLOTB_PD3_LOW[7:0] 0x7B B_PD4_LOW [15:8] SLOTB_PD4_LOW[15:8] 0x0000 R [7:0] SLOTB_PD4_LOW[7:0] 0x7C B_PD1_HIGH [15:8] SLOTB_PD1_HIGH[15:8] 0x0000 R [7:0] SLOTB_PD1_HIGH[7:0] 0x7D B_PD2_HIGH [15:8] SLOTB_PD2_HIGH[15:8] 0x0000 R [7:0] SLOTB_PD2_HIGH[7:0] 0x7E B_PD3_HIGH [15:8] SLOTB_PD3_HIGH[15:8] 0x0000 R [7:0] SLOTB_PD3_HIGH[7:0] 0x7F B_PD4_HIGH [15:8] SLOTB_PD4_HIGH[15:8] 0x0000 R [7:0] SLOTB_PD4_HIGH[7:0] 1 RW1C means write 1 to clear.

Rev. A | Page 27 of 34 Address Data Bit Default Value Access Name Description 0x24 [15:14] 0x0 R/W Reserved 13 0x1 R/W ILED2_SCALE LED2 current scale factor. 1: 100% strength. 0: 40% strength (recommended operation setting). LED2 Current Scale = 0.4 + 0.6 × (Register 0x24, Bit 13) 12 0x1 R/W Reserved [11:4] 0x0 R/W Reserved Write 0x03. [3:0] 0x0 R/W ILED2_COARSE LED2 coarse current setting. Coarse current sink target value of LED2 in standard operation. See Register 0x23, Bits[3:0] for values. LED2PEAK = LED2COARSE × LED2FINE × LED2SCALE where: LED2PEAK is the LED2 peak target value (mA). LED2COARSE = 28 + 15.5 × (Register 0x24, Bits[3:0]). LED2FINE = 0.71 + 0.024 × (Register 0x25, Bits[10:6]). LED2SCALE = 0.4 + 0.6 × (Register 0x24, Bit 13). 0x25 [15:11] 0xC R/W Reserved [10:6] 0xC R/W ILED2_FINE LED2 fine adjust. Current adjust multiplier for LED2. LED2 Fine Adjust = 0.71 + 0.024 × (Register 0x25, Bits[10:6]) See Register 0x24, Bits[3:0], for the full LED2 formula. 5 0x0 R/W Reserved [4:0] 0xC R/W ILED1_FINE LEDX1 fine adjust. Current adjust multiplier for LEDX1. LEDX1 Fine Adjust = 0.71 + 0.024 × (Register 0x25, Bits[4:0]) See Register 0x23, Bits[3:0], for the full LEDX1 formula. 0x30 [15:0] 0x0320 R/W SLOTA_LEDMODE LED configuration for Time Slot A. Recommended setting: write 0x0319. 0x31 [15:8] 0x08 R/W SLOTA_NUMPULSES LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A, typically LEDX1. A setting of six pulses (0x06) is typical. [7:0] 0x18 R/W Reserved (write 0x13) Write 0x13. 0x34 [15:10] 0x00 R/W Reserved 9 0x0 R/W SLOTB_LED_DIS Time Slot B LED disable. 1: disables the LED that is assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not the LED only. 8 0x0 R/W SLOTA_LED_DIS Time Slot A LED disable. 1: disables the LED that is assigned to Time Slot A. Use Register 0x11 instead to enable or disable the actual time slot usage and not the LED only. [7:0] 0x00 R/W Reserved 0x35 [15:0] 0x0320 R/W SLOTB_LEDMODE LED configuration for Time Slot B. Recommended setting: write 0x0319. 0x36 [15:8] 0x08 R/W SLOTB_NUMPULSES LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B, typically LED2. A setting of six pulses (0x06) is typical. [7:0] 0x18 R/W Reserved (write 0x13) Write 0x13.

Table 15. AFE Configuration Registers, Time Slot A 0x39 [15:0] 0x22FC R/W SLOTA_AFEMODE AFE configuration for Time Slot A. Recommended setting: write 0x21F4. Channel 2 to Channel 4 receive the settings from Register 0x55, Bits[5:0]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. [5:4] 0x3 R/W Reserved Write 0x03. [3:2] 0x2 R/W Reserved Write 0x1. disabled, it is for all four Time Slot A channel TIA gain settings. 0x43 [15:0] 0xADA5 R/W SLOTA_AFE_CON AFE connection in Time Slot A. 0xADA5: analog full path mode. [11:10] 0x0 R/W SLOTB_TIA_GAIN_4 TIA gain for Time Slot B Channel 4. [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 TIA gain for Time Slot B Channel 3. [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 TIA gain for Time Slot B Channel 2. [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 TIA gain for Time Slot A Channel 4. [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 TIA gain for Time Slot A Channel 3.

[1:0] 0x0 R/W SLOTA_TIA_GAIN_2 TIA gain for Time Slot A Channel 2. Table 16. AFE Configuration Registers, Time Slot B 0x3B [15:0] 0x22FC R/W SLOTB_AFEMODE AFE configuration for Time Slot B. Recommended setting: write 0x21F4. Channel 2 to Channel 4 receive the settings from Register 0x55, Bits[11:6]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. [5:4] 0x3 R/W Reserved Write 0x03. [3:2] 0x2 R/W Reserved Write 0x1. disabled, it is for all four Time Slot B Channel TIA gain settings. 0x45 [15:0] 0xADA5 R/W SLOTB_AFE_CON AFE connection in Time Slot B. 0xADA5: analog full path mode. Table 17. System Registers bit set, write 1 to Bit 15 of FIFO_SAMPLES to clear the contents of the FIFO. register goes to 0. Writing a 0 to this register has no effect. register goes to 0. Writing a 0 to this register has no effect.

Rev. A | Page 30 of 34 Address Data Bit Default Access Name Description 0x01 [15:9] 0x00 R/W Reserved 8 0x00 R/W FIFO_INT_MASK Sends an interrupt when the FIFO data length has exceeded the FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. 7 0x1 R/W Reserved 6 0x1 R/W SLOTB_INT_MASK Sends an interrupt on the Time Slot B sample. A 0 enables the interrupt. 5 0x1 R/W SLOTA_INT_MASK Sends an interrupt on the Time Slot A sample. A 0 enables the interrupt. [4:0] 0x1F R/W Reserved 0x02 [15:3] 0x0000 R/W Reserved 2 0x0 R/W INT_ENA INT enable. 0: disable the INT pin. The INT pin floats regardless of interrupt status. The status register (Address 0x00) remains active. 1: enable the INT pin. 1 0x0 R/W INT_DRV INT drive. 0: the INT pin is always driven. 1: the INT pin is driven when the interrupt is asserted. Otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open-drain). Use this setting if multiple devices need to share the INT pin. 0 0x0 R/W INT_POL INT polarity. 0: the INT pin is active high. 1: the INT pin is active low. 0x06 [15:14] 0x0 R/W Reserved [13:8] 0x00 R/W FIFO_THRESH FIFO length threshold. An interrupt is generated when the number of data words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin automatically deasserts when the number of data words available in the FIFO no longer exceeds the value in FIFO_THRESH. [7:0] 0x00 R/W Reserved 0x08 [15:0] 0x0416 R DEV_ID Device ID. 0x0A [15:12] 0x0 R Reserved [11:0] 0x000 R CLK_RATIO When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. 0x10 [15:2] 0x000 R/W Reserved [1:0] 0x0 R/W Mode Determines the operating mode of the ADPD144RI. 0x0: standby. 0x1: program. 0x2: sample. 0x11 [15:14] 0x1 R/W Reserved 13 0x0 R/W RDOUT_MODE Readback data mode for extended data registers. 0x0: block sum of N samples. 0x1: block average of N samples. 12 0x1 R/W FIFO_OVRN_PREVENT 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). [11:9] 0x0 R/W Reserved

Rev. A | Page 31 of 34 Address Data Bit Default Access Name Description [8:6] 0x0 R/W SLOTB_FIFO_MODE Time Slot B FIFO data format. 0: no data to FIFO. 1: 16-bit sum of all 4 channels. 2: 32-bit sum of all 4 channels. 4: 4 channels of 16-bit sample data. 6: 4 channels of 32-bit extended sample. Others: reserved. The selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, NSAMPLE (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). 5 0x0 R/W SLOTB_EN Time Slot B enable. 1: enables Time Slot B. [4:2] 0x0 R/W SLOTA_FIFO_MODE Time Slot A FIFO data format. 0: no data to FIFO. 1: 16-bit sum of all 4 channels. 2: 32-bit sum of all 4 channels. 4: 4 channels of 16-bit sample data. 6: 4 channels of 32-bit extended sample. Others: reserved. 1 0x0 R/W Reserved Write 0x0. 0 0x0 R/W SLOTA_EN Time Slot A enable. 1: enables Time Slot A. 0x38 15 0x0 R/W Reserved 14 0x0 R/W EXT_SYNC_ENA Write 0x1 when EXT_SYNC_SEL (Register 0x4F, Bit 2) is set to 1. Otherwise, write 0x0. [13:0] 0x0 R/W Reserved 0x4B [15:8] 0x26 R/W Reserved 7 0x0 R/W CLK32K_EN Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x1: normal operation. 6 0x0 R/W Reserved [5:0] 0x12 R/W CLK32K_ADJUST Data sampling (32 kHz) clock frequency adjust. This register calibrates the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. Note that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. 0x4D [15:8] 0x42 R/W Reserved [7:0] 0x5E R/W CLK32M_ADJUST Internal timing (32 MHz) clock frequency adjust. This register calibrates the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and Timing Calibration section for more information on clock adjustment. 0000 0000: minimum frequency. 0101 1110: default frequency. 1111 1111: maximum frequency. 0x4E [15:0] 0x0060 R/W ADC_TIMING Write 0x0040.

2 0x0 R/W EXT_SYNC_SEL Sample sync select. 0: use the internal 32 kHz clock with FSAMPLE to select sample timings. 1: use the INT pin to trigger the sample cycle. 1 0x0 R/W INT_IE INT pin input enable. 0 0x0 R/W Reserved Write 0x0. CLK_RATIO bits in Register 0x0A. Reset this bit to 0 prior to reinitiating the calculation. Table 18. ADC Registers 0x12 [15:0] 0x0028 R/W FSAMPLE Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] × 4). after the ADC. Register 0x70 to Register 0x7F hold the data sum. data average, which can increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. Time Slot A. See description in Register 0x15, Bits[10:8]. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical. ADC value. A value of 0x2000 is typical.

Table 19. Data Registers

2 R/W SLOTB_DATA_HOLD Setting this bit prevents an update of the data registers

contiguous set of data from all four photodiode channels.

1 R/W SLOTA_DATA_HOLD Setting this bit prevents an update of the data registers

contiguous set of data from all four photodiode channels. the 32 MHz clock so that calibration can occur. this bit to 0 when the FIFO access sequence is complete. 0x64 [15:0] R SLOTA_PD1_16BIT 16-bit value of Photodiode 1 in Time Slot A. 0x65 [15:0] R SLOTA_PD2_16BIT 16-bit value of Photodiode 2 in Time Slot A. 0x66 [15:0] R SLOTA_PD3_16BIT 16-bit value of Photodiode 3 in Time Slot A. 0x67 [15:0] R SLOTA_PD4_16BIT 16-bit value of Photodiode 4 in Time Slot A. 0x68 [15:0] R SLOTB_PD1_16BIT 16-bit value of Photodiode 1 in Time Slot B. 0x69 [15:0] R SLOTB_PD2_16BIT 16-bit value of Photodiode 2 in Time Slot B. 0x6A [15:0] R SLOTB_PD3_16BIT 16-bit value of Photodiode 3 in Time Slot B. 0x6B [15:0] R SLOTB_PD4_16BIT 16-bit value of Photodiode 4 in Time Slot B. 0x70 [15:0] R SLOTA_PD1_LOW Low data-word for Photodiode 1 in Time Slot A. 0x71 [15:0] R SLOTA_PD2_LOW Low data-word for Photodiode 2 in Time Slot A. 0x72 [15:0] R SLOTA_PD3_LOW Low data-word for Photodiode 3 in Time Slot A. 0x73 [15:0] R SLOTA_PD4_LOW Low data-word for Photodiode 4 in Time Slot A. 0x74 [15:0] R SLOTA_PD1_HIGH High data-word for Photodiode 1 in Time Slot A. 0x75 [15:0] R SLOTA_PD2_HIGH High data-word for Photodiode 2 in Time Slot A. 0x76 [15:0] R SLOTA_PD3_HIGH High data-word for Photodiode 3 in Time Slot A. 0x77 [15:0] R SLOTA_PD4_HIGH High data-word for Photodiode 4 in Time Slot A. 0x78 [15:0] R SLOTB_PD1_LOW Low data-word for Photodiode 1 in Time Slot B. 0x79 [15:0] R SLOTB_PD2_LOW Low data-word for Photodiode 2 in Time Slot B. 0x7A [15:0] R SLOTB_PD3_LOW Low data-word for Photodiode 3 in Time Slot B. 0x7B [15:0] R SLOTB_PD4_LOW Low data-word for Photodiode 4 in Time Slot B. 0x7C [15:0] R SLOTB_PD1_HIGH High data-word for Photodiode 1 in Time Slot B. 0x7D [15:0] R SLOTB_PD2_HIGH High data-word for Photodiode 2 in Time Slot B. 0x7E [15:0] R SLOTB_PD3_HIGH High data-word for Photodiode 3 in Time Slot B. 0x7F [15:0] R SLOTB_PD4_HIGH High data-word for Photodiode 4 in Time Slot B.

1.71 BSC

1.25 BSC

2.24 REF

1.86 BSC

1.05 REF

0.93 REF

Figure 24. 12-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] 2 To use the EVAL-ADPD144RIZ-SF, the EVAL-ADPDUCZ microcontroller board must also be used. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). registered trademarks are the prop erty of their respective owners.