ADPD103

ADPD103 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 52

Technical content

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Tel: 781.329.4700 © 2015–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Multifunction photometric front end Fully integrated AFE, ADC, LED drivers, and timing core Usable in a broad range of optical measurement applications, including photoplethysmography Enables best-in-class ambient light rejection capability without the need for photodiode optical filters Three 8 mA to 250 mA LED drivers Separate data registers for each LED/photodiode combination 1 to 8 optical inputs Flexible, multiple, short LED pulses per optical sample 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator, enabling up to 27 bits per data read Low power operation I2C interface and 1.8 V analog/digital core Flexible sampling frequency ranging from 0.122 Hz to 3.820 kHz FIFO data operation

APPLICATIONS

Body worn health and fitness monitors, for example, heart rate monitoring Clinical measurements, for example, SpO2 Industrial monitoring Background light measurements GENERAL DESCRIPTION The ADPD103 is a highly efficient photometric front end with an integrated 14-bit analog-to-digital converter (ADC) and a 20-bit burst accumulator that works in concert with flexible light emitting diode (LED) drivers. It is designed to stimulate an LED and measure the corresponding optical return signal. The data output and functional configuration occur over a 1.8 V I2C interface. The control circuitry includes flexible LED signaling and synchronous detection. The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. Couple the ADPD103 with a low capacitance photodiode of <100 pF for optimal performance. The ADPD103 can be used with any LED.

Rev. B | Page 2 of 52 TABLE OF CONTENTS

REVISION HISTORY

2/16—Revision B: Initial Version

Rev. B | Page 3 of 52 FUNCTIONAL BLOCK DIAGRAM LED3 DRIVER LED2 DRIVER ANALOG BLOCK TIME SLOT A DATA TIME SLOT B DATA DIGITAL DATAPATH AND INTERFACE CONTROL LED3 LEVEL AND TIMING CONTROL LED2 LEVEL AND TIMING CONTROL LED1 DRIVER LED1 LEVEL AND TIMING CONTROL SDA SCL INT DGND AGND VREF 1µF AVDD DVDD ADPD103 14-BIT ADC TIA TIA TIA TIA AFE: SIGNAL CONDITIONING AFE: SIGNAL CONDITIONING AFE: SIGNAL CONDITIONING AFE: SIGNAL CONDITIONING PDC TIME SLOT SWITCH PD1 PD8 PD5 PD2 PD6 PD3 PD7 PD4 LEDX1 LEDX2 LEDX3 LGND VLED PDSO LED1 LED2 LED3 VBIAS BPF ±1 INTEGRATOR VBIAS BPF ±1 INTEGRATOR VBIAS BPF ±1 INTEGRATOR VBIAS BPF ±1 INTEGRATOR 12722-001 B A SLOT SELECT AFE CONFIGURATION Fig ure 1. Typical Functional Block Diagram

Table 1. Operating Conditions AVDD = DVDD = 1.8 V , ambient temperature, unless otherwise noted. Table 2. Current Consumption1, 2

1 Pulse 100 Hz d ata rate; Time Slot A only 106 µA

100 Hz data rate; both Time Slot A and Time Slot B 151 µA

10 Pulses 10 0 Hz data rate; Time Slot A only 258 µA

100 Hz data rate; both Time Slot A and Time Slot B 455 µA

1 Pulse 50 H z data rate 15 µA

100 Hz data rate 30 µA

200 Hz data rate 60 µA

10 Pulses 50 H z data rate 150 µA

100 Hz data rate 300 µA

200 Hz data rate 600 µA

1 LEDA or LEDB is one of LED1, LED2, or LED3. VLEDA or VLEDB is one of VLED1, VLED2, or VLED3. 2 VDD is the voltage applied at the AVDD and DVDD pins.

Rev. B | Page 5 of 52 PERFORMANCE SPECIFICATIONS AVDD = DVDD = 1.8 V , TA = full operating temperature range, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DATA AQUISITION Resolution Single pulse 1 4 Bi ts Resolution/Sample 64 to 255 pulses 2 0 Bi ts Resolution/Data Read 64 to 255 pulses and sample average = 128 27 Bits LED DRIVER LED Current Slew Rate1 Rise Slew rate control setting = 0; TA = 25°C; ILED = 70 mA 2 40 m A/µs S lew rate control setting = 7; TA = 25°C; ILED = 70 mA 1 400 m A/µs Fall Slew rate control setting = 0, 1, 2; TA = 25°C; ILED = 70 mA 3 200 m A/µs Slew rate control setting = 6, 7; TA = 25°C; ILED = 70 mA 4500 mA/µs LED Peak Current LED pulse enabled 8 25 0 mA Driver Compliance Voltage Voltage above ground required for LED driver operation 0.2 V LED PERIOD AFE width = 4 µs 19 µs AF E width = 3 µs 17 µs Sampling Frequency2 Time Slot A only; normal mode; 1 pulse; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 3 230 Hz Time Slot B only; normal mode; 1 pulse; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 3820 Hz B oth time slots; normal mode; 1 pulse; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 1 750 Hz T ime Slot A only; normal mode; 8 pulses; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 2 257 Hz T ime Slot B only; normal mode; 8 pulses; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 2 531 Hz Both time slots; normal mode; 8 pulses; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 11 93 Hz CATHODE PIN (PDC) VOLTAGE During All Sampling Periods Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 13 1.8 V R egister 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 1 .3 V During Slot A Sampling Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x03 1 .8 V R egister 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1 1 .3 V R egister 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2 1 .55 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x34 0 V During Slot B Sampling Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x03 1 .8 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1 1.3 V R egister 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2 1 .55 V R egister 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x34 0 V During Sleep Periods Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 1.8 V Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 1.3 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0 1.8 V R egister 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x1 1 .3 V R egister 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x2 1 .55 V R egister 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x3 0 V PHOTODIODE INPUT PINS/ ANODE VOLTAGE During All Sampling Periods 1.3 V During Sleep Periods C athode voltage V 1 LED inductance is negligible for these values. The effective slew rate slows with increased inductance. 2 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the actual output data rate of the device 3 This mode may induce additional noise and is not recommended unless absolutely necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode of the magnitude C × dV/dt. 4 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode.

Rev. B | Page 6 of 52 ANALOG SPECIFICATIONS AVDD = DVDD = 1.8 V , TA = full operating temperature range, unless otherwise noted. Compensation of the AFE offset is explained in the AFE Operation section. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit INPUT CAPACITANCE 100 pF PULSED SIGNAL CONVERSIONS, 3 μs WIDE LED PULSE1 4 μs wide AFE integration; normal operation, Register 0x43 (Time Slot A) and Register 0x45 (Time Slot B) = 0xADA5 ADC Resolution2 Transimpedance amplifier (TIA) feedback resistor 25 k Ω 1. 64 nA/ LSB 50 kΩ 0.82 nA/LSB 100 k Ω 0. 41 nA/ LSB 200 k Ω 0. 2 nA/ LSB ADC Saturation Level TIA feedback resistor 25 k Ω 13. 4 μA 50 k Ω 6. 7 μA 100 k Ω 3. 35 μA 200 k Ω 1. 67 μA Ambient Signal Headroom on Pulsed Signal TIA feedback resistor 25 kΩ 37 μA 50 k Ω 18. 5 μA 100 k Ω 9. 25 μA 200 k Ω 4. 63 μA PULSED SIGNAL CONVERSIONS, 2 μs WIDE LED PULSE1 3 μs wide AFE integration; normal operation, Register 0x43 (Time Slot A) and Register 0x45 (Time Slot B) = 0xADA5 ADC Resolution2 TIA feedback resistor 25 kΩ 2.31 nA/LSB 50 k Ω 1. 15 nA/ LSB 100 k Ω 0. 58 nA/ LSB 200 k Ω 0. 29 nA/ LSB ADC Saturation Level TIA feedback resistor 25 kΩ 18.9 μA 50 k Ω 9. 46 μA 100 k Ω 4. 73 μA 200 k Ω 2. 37 μA Ambient Signal Headroom on Pulsed Signal TIA feedback resistor 25 k Ω 31. 5 μA 50 k Ω 15. 7 μA 100 k Ω 7. 87 μA 200 kΩ 3.93 μA FULL SIGNAL CONVERSIONS3 TIA Saturation Level of Pulsed Signal and Ambient Level TIA feedback resistor 25 k Ω 50. 4 μA 50 k Ω 25. 2 μA 100 k Ω 12. 6 μA 200 k Ω 6. 3 μA

Rev. B | Page 7 of 52 Parameter Test Conditions/Comments Min Typ Max Unit SYSTEM PERFORMANCE Total Output Noise Floor Normal mode; per pulse; per channel; no LED; CPD = 70 pF 25 k Ω; referred to ADC input 2. 0 L SB rms 25 k Ω; referred to peak input signal for 2 µs LED pulse 4. 6 nA rms 25 k Ω; referred to peak input signal for 3 µs LED pulse 3. 3 nA rms 25 kΩ; saturation signal-to-noise ratio (SNR) per pulse per channel4 72.3 dB 50 k Ω; referred to ADC input 2. 4 L SB rms 50 k Ω; referred to peak input signal for 2 µs LED pulse 2. 8 nA rms 50 k Ω; referred to peak input signal for 3 µs LED pulse 2. 0 nA rms 50 k Ω; saturation SNR per pulse per channel4 70. 6 dB 100 k Ω; referred to ADC input 3. 4 L SB rms 100 k Ω; referred to peak input signal for 2 µs LED pulse 1. 9 nA rms 100 k Ω; referred to peak input signal for 3 µs LED pulse 1. 4 nA rms 100 kΩ; saturation SNR per pulse per channel4 67.6 dB 200 k Ω; referred to ADC input 5. 5 L SB rms 200 k Ω; referred to peak input signal for 2 µs LED pulse 1. 6 nA rms 200 k Ω; referred to peak input signal for 3 µs LED pulse 1. 1 nA rms 200 k Ω; saturation SNR per pulse per channel4 63. 5 dB DC Power Supply Rejection Ratio (DC PSRR) − 37 dB 1 This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage. 2 ADC resolution is listed per pulse when the AFE offset is correctly compensated per the AFE Operation section. If using multiple pulses, divide by the number of pulses. 3 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal. 4 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself. DIGITAL SPECIFICATIONS DVDD = 1.7 V to 1.9 V, unless otherwise noted. Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS (SCL, SDA) Input Voltage Level High VIH 0. 7 × DVDD 3. 6 V Low VIL 0. 3 × DVDD V Input Current Level High IIH − 10 + 10 µA Low IIL − 10 + 10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS INT Output Voltage Level High VOH 2 mA high level output current DVDD − 0.5 V Low VOL 2 mA low level output current 0.5 V PDSO Output Voltage Level High VOH 2 mA high level output current DVDD − 0.5 V Low VOL 2 mA low level output current 0. 5 V SDA Output Voltage Level Low VOL1 2 mA low level output current 0. 2 × DVDD V SDA Output Current Level Low IOL VOL1 = 0.6 V 6 mA

Table 6. I2C Timing Specifications

Table 8. Thermal Resistance Table 9. Recommended Soldering Profile

1. NIC = NONBONDED PAD, CAN BE GROUNDED.
2. EXPOSED PAD (DIGITAL GROUND). CONNECT THE

Table 10. 28-Lead LFCSP Pin Function Descriptions 2 PDSO DO Power-Down Status Output. 3 DVDD S 1.8 V Digital Supply. 5 VREF REF Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND. 6 AVDD S 1.8 V Analog Supply. 7 PD1 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 8 PD2 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 9 PD3 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 10 PD4 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 11 PDC AO Photodiode Common Cathode Bias. 12 PD5 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 13 PD6 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 14 PD7 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 15 PD8 AI Photodiode Current Input (Anode). If not in use, leave this pin floating. 16 to 22 NIC R Not Internally Connected (Nonbonded Pad). This pin can be grounded. 23 LEDX1 AO LED Driver 1 Current Sink. If not in use, leave this pin floating. 24 LEDX3 AO LED Driver 3 Current Sink. If not in use, leave this pin floating. 25 LEDX2 AO LED Driver 2 Current Sink. If not in use, leave this pin floating. 26 LGND S LED Driver Ground. 28 SDA DIO I2C Data Input/Output. E PAD (DGND) S Exposed Pad (Digital Ground). Connect the exposed pad to ground. and DIO means digital input/output.

Table 11. 16-Ball WLCSP Pin Function Descriptions A1 LGND S LED Driver Ground. A2 LEDX2 AO LED Driver 2 Current Sink. If not in use, leave this pin floating. B1 LEDX3 AO LED Driver 3 Current Sink. If not in use, leave this pin floating. B2 LEDX1 AO LED Driver 1 Current Sink. If not in use, leave this pin floating. B3 SDA DIO I2C Data Input/Output. C3 DVDD S 1.8 V Digital Supply. E1 PDSO DO Power-Down Status Output. E2 VREF REF Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND. E3 AVDD S 1.8 V Analog Supply. F1 PD5-8 AI Photodiode Combined Current Input of PD5 to PD8. If not in use, leave this pin floating. F2 PDC AO Photodiode Common Cathode Bias. F3 PD1-4 AI Photodiode Combined Current Input of PD1 to PD4. If not in use, leave this pin floating. 1 S means supply, AO means analog output, DIO means digital input/output, DO means digital output, REF means voltage reference, and AI means analog input.

the effect of ambient light on the measured signal. in sequence for every sampling period, as shown in Figure 10. Table 12. LED Timing and Sample Timing Parameters 1 Setting the SLOTx_LED_OFFSET below the specified minimum value may cause failure of ambient light rejection for large photodiodes. 2 Setting the SLOTx_LED_PERIOD below the specified minimum value can cause invalid data captures.

Rev. B | Page 14 of 52 TIME SLOT SWITCH Up to eight photodiodes (PD1 to PD8) can be connected to the ADPD103. The photodiode anodes are connected to the PD1 to PD8 input pins; the photodiode cathodes are connected to the cathode pin, PDC. The anodes are assigned in three different configurations depending on the settings of Register 0x14 (see Figure 11, Figure 12, and Figure 13). A switch sets which photodiode group is connected during Time Slot A and Time Slot B. See Table 13 for the time slot switch registers. When using less than eight photodiodes, it is important to leave the unused inputs floating for proper operation of the device. The photodiode inputs are current inputs and as such, these pins are also considered to be voltage outputs. Tying these inputs to a voltage may saturate the analog block. Register 0x14, PD1 to PD8 Input Configurations CH1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 5 REGISTER 0x14[7:4] = 5 CH2 CH3 CH4 12722-109 F igure 11. PD1 to PD4 Connection INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 4 REGISTER 0x14[7:4] = 4 CH1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 CH2 CH3 CH4 12722-110 F igure 12. PD5 to PD8 Connection INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 1 REGISTER 0x14[7:4] = 1 CH1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 CH2 CH3 CH4 12722-111 F igure 13. 2-to-1 PD Current Summation

Table 13. Time Slot Switch (Register 0x14) 0x 0: inputs are floating in Time Slot B. 0x 1: all PDx pins (PD1 to PD8) are connected during Time Slot B. 0x 4: PD5 to PD8 are connected during Time Slot B. 0x 5: PD1 to PD4 are connected during Time Slot B. 0x 0: inputs are floating in Time Slot A. 0x 1: All PDx pins (PD1 to PD8) are connected during Time Slot A. 0x 4: PD5 to PD8 are connected during Time Slot A. 0x 5: PD1 to PD4 are connected during Time Slot A. definitions of tA, t1, tB, and t2.

1. Write 0x1 to Register 0x10 to enter program mode.
2. Write the appropriate value to Register 0x4F, Bits[3:2] to

Register 0x4F , Bit 5, for the PDSO pin.

1. Write b1 to EXT_SYNC_ENA, Register 0x38, Bit 14 to

enable the external sampling trigger.

1. Write 0x2 to Register 0x10 to start the sampling operations.

The maximum frequency constraints also apply in this case.

1. Drive the PDSO pin to a valid logic level or with the

input. Do not leave the pin floating prior to enabling it.

1. Wr ite b1 to Register 0x4F, Bit 5 to enable the PDSO pin as
2. Write b11 to register 0x4B, Bit 7 and Bit 8 (CLK32K_EN

use an external 32 kHz clock.

1. Write 0x1 to Register 0x10 to enter program mode.
2. Write additional control registers in any order while the
3. Write 0x2 to Register 0x10 to start the normal samplin

sequence, shown in Figure 14. ALL REGISTER VALUES ARE RETAINED. DEVICE IS FULLY POWERED IN THIS MODE. DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE. program, and normal sampling mode. Bits[1:0]. The device powers up in standby mode. write 0x1 to Register 0x10, Bits[1:0]. mode, write 0x2 to Register 0x10, Bits[1:0].

1. LED pulse and sample.The ADPD103 pulses external LEDs.

is user configurable between 1 and 255.

1. Intersample averaging. If desired, the logic can average n
2. Data read. The host processor reads the converted results

from the data register or the FIFO.

1. Repeat. The sequence has a few different loops that enable

lose in time relative to each other.

16 BITS

1. nA AND nB = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B.
2. NA AND NB = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B. 16 BITS[14 + LOG2(nB)] BITS

14 BITS14 BITS

Figure 15. ADPD103 Datapath

Rev. B | Page 17 of 52 LED Pulse and Sample At each sampling period, the selected LED driver drives a series of LED pulses, as shown in Figure 16. The magnitude, duration, and number of pulses are programmable over the I2C interface. Each LED pulse coincides with a sensing period so that the sensed value represents the total charge acquired on the photodiode in response to only the corresponding LED pulse. Charge, such as ambient light, that does not correspond to the LED pulse is rejected. After each LED pulse, the photodiode output relating the pulsed LED signal is sampled and converted to a digital value by the 14-bit ADC. Each subsequent conversion within a sampling period is summed with the previous result. Up to 255 pulse values from the ADC can be summed in an individual sampling period. There is a 20-bit maximum range for each sampling period. Averaging The ADPD103 offers sample accumulation and averaging functionality to increase signal resolution. Within a sampling period, the AFE can sum up to 256 sequential pulses. As shown in Figure 15, samples acquired by the AFE are clipped to 20 bits at the output of the AFE. Additional resolution, up to 27 bits, can be achieved by averaging between sampling periods. This accumulated data of N samples is stored as 27-bit values and can be read out directly by using the 32-bit output registers or the 32-bit FIFO configuration. When using the averaging feature set up by the register, subsequent pulses can be averaged by powers of 2. The user can select from 2, 4, 8 … up to 128 samples to be averaged. Pulse data is still acquired by the AFE at the sampling frequency, fSAMPLE (Register 0x12), but new data is written to the registers at the rate of fSAMPLE/N every Nth sample. This new data consists of the sum of the previous N samples. The full 32-bit sum is stored in the 32-bit registers. However, before sending this data to the FIFO, a divide by N operation occurs. This divide operation maintains bit depth to prevent clipping on the FIFO. Use this between sample averaging to lower the noise while maintaining 16-bit resolution. If the pulse count registers are kept to 8 or less, the 16-bit width is never exceeded. Therefore, when using Register 0x15 to average subsequent pulses, many pulses can be accumulated without exceeding the 16-bit word width. This can reduce the number of FIFO reads required by the host processor. Data Read The host processor reads output data from the ADPD103, via the I2C protocol, from the data registers or from the FIFO. New output data is made available every N samples, where N is the user configured averaging factor. The averaging factors for Time Slot A and Time Slot B are configurable independently of each other. If they are the same, both time slots can be configured to save data to the FIFO. If the two averaging factors are different, only one time slot can save data to the FIFO; data from the other time slot can be read from the output registers. The data read operations are described in more detail in the Reading Data section. TIME (s) OPTICAL SAMPLING LOCATIONS NUMBER OF LED PULSES (nA OR nB) LED CURRENT (ILED) SHOWN WITH fSAMPLE = 10 Hz 12722-010 F igure 16. Example of a Photoplethysmography (PPG) Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample

Rev. B | Page 18 of 52 AFE OPERATION The timing within each pulse burst is important for optimizing the operation of the ADPD103. Figure 17 shows the timing wave- forms for a single time slot as an LED pulse response propagates through the analog block of the AFE. The first graph, shown in green, shows the ideal LED pulsed output. The filtered LED response, shown in blue, shows the output of the analog integrator. The third graph, shown in orange, illustrates an optimally placed integration window. When programmed to the optimized value, the full signal of the filtered LED response can be integrated. The AFE integration window is then applied to the output of the band- pass filter (BPF) and the result is sent to the ADC and summed for N pulses. If the AFE window is not correctly sized or located, all of the receive signal is not properly reported and system perfor- mance is not optimal; therefore, it is important to verify proper AFE position for every new hardware design or the LED width. AFE INTEGRATION OFFSET ADJUSTMENT The AFE integration width must be equal or larger than the LED width. As AFE width increases, the output noise increases and the ability to suppress high frequency content from the environ- ment decreases. It is therefore desirable to keep the AFE integration width small. However, if the AFE width is too small, the LED signal is attenuated. With most hardware selections, the AFE width produces the optimal SNR at 1 μs more than the LED width. After setting LED width, LED offset, and AFE width, the ADC offset can then be optimized. The AFE offset must be manually set such that the falling edge of the first segment of the integration window matches the zero crossing of the filtered LED response. F igure 17. AFE Operation Diagram

not need to be optimized further. by Bits[10:0] of Register 0x39 and Register 0x3B, respectively. Each LSB represents one cycle of the 32 MHz clock, or 31.25 ns. to represent 1 µs steps and Bits[4:0] to represent 31.25 ns steps. Table 14 lists some typical LED and AFE values after optimization. calibrated prior to sweeping the AFE. Table 14. AFE Window Settings

Table 16. Typical Photodiode Anode to Input Channel Connections 1 NC means do not connect under the conditions provided in Table 16. Leave all unused inputs floating.

0.2 V of compliance above ground to maintain the programmed

(CVLED) and the supply voltages of the LEDs (VLEDx). ILED_PEAK is peak current setting of the LED. supply must support a dc current of 40 mA. forward-biased voltage, VFB_LED_MAX, of the LED in operation. Figure 26. In this example, 250 mA of current through two green constraints on the VLEDx supply. less than the forward bias on the LED. tLED_PULSE is the LED pulse width. used in operating the device. VLED_MIN is the lowest voltage from the VLEDx supply with no load. the LED to achieve ILED_PEAK.

voltage of the LED operating at the maximum current is satisfied. Table 3. Even at the lowest setting, careful consideration must be on the LEDXx pins during the slew portion of the LED pulse.

3.6 V may damage the device.

In addition, a negative spike <−0.3 V may also damage the device. particular power-up sequence.

1. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the

transition as defined by Register 0x10.

1. Write 0x1 to Register 0x10 to force the device into program

state transition does not occur until both steps occur.

1. W rite additional control registers in any order while the
2. Write 0x2 to Register 0x10 to start normal sampling
3. Write 0x1 to Register 0x10 to force the device into program
4. Write to the registers in any order while the device is in
5. Write 0x00FF to Register 0x00 to clear all interrupts. If
6. Write 0x0 to Register 0x10 to force the device into standby
7. Optionally, stop the 32 kHz clock by resetting the CLK32K_

32 kHz clock running after it is turned on. to loosen the system timing requirements for data accesses. can be configured to store data from either or both time slots.

Rev. B | Page 25 of 52 written to the FIFO. Note that both time slots can be enabled to use the FIFO, but only if their output data rate is the same. Output data rate = fSAMPLE/N where: fSAMPLE is the sampling frequency. N is the averaging factor for each time slot (NA for Time Slot A and NB for Time Slot B). In other words, NA = NB must be true to store data from both time slots in the FIFO. Data packets are written to the FIFO at the output data rate. A data packet for the FIFO consists of a complete sample for each enabled time slot. Data for each photodiode channel can be stored as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of data per sample, depending on the mode and data format. To ensure that data packets are intact, new data is only written to the FIFO if there is sufficient space for a complete packet. Any new data that arrives when there is not enough space is lost. The FIFO continues to store data when sufficient space exists. Always read FIFO data in complete packets to ensure that data packets remain intact. The number of bytes currently stored in the FIFO is available in Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also available and automatically generates when a specified amount of data is written to the FIFO. Interrupt-Based Method To read data from the FIFO using an interrupt-based method, use the following procedure: 1. In program mode, set the configuration of the time slots as d esired for operation. 2. Write Register 0x11 with the desired data format for each time slot. 3. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the interrupt threshold. A good value for this is the number of 16-bit words in a data packet, minus 1. This causes an interrupt to generate when there is at least one complet e p acket in the FIFO. 4. Enable the FIFO interrupt by writing a 0 to the FIFO_ INT_MASK in Register 0x01, Bit 8. Also, configure the interrupt pin (INT) by writing the appropriate value to the b its in Register 0x02. 5. Enter normal operation mode by setting Register 0x10 to 0x2. 6. When an interrupt occurs a. There is no requirement to read the FIFO_SAMPLES register, because the interrupt is generated only if there is one or more full packets. Optionally, the interrupt routine can check for the presence of more than one available packet by reading this register. b. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bi t 0) twice in two consecutive write operations. c. Read a complete packet using one or more multiword accesses using Register 0x60. Reading the FIFO a utomatically frees the space for new samples. d. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F , Bit 0). The interrupt automatically clears when enough data is read from the FIFO to bring the data level below the threshold. Polling Method To read data from the FIFO in a polling method, use the following procedure: 1. In program mode, set the configuration of the time slots as d esired for operation. 2. Write Register 0x11 with the desired data format for each time slot. 3. Enter normal operation mode by setting Register 0x10 to 2. Next, begin the polling operations. 1. Wait for the polling interval to expire. 2. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]). . I f FIFO_SAMPLES ≥ the packet size, read a packet using the following steps: a. W rite 1 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bi t 0) twice in two consecutive write operations. b. Read a complete packet using one or more multiword a ccesses using Register 0x60. Reading the FIFO a utomatically frees the space for new samples. c. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F , Bit 0). d. Repeat Step 1. When a mode change is required, or any other disruption to normal sampling is necessary, the FIFO must be cleared. Use the following procedure to clear the state and empty the FIFO: 1. Enter program mode by setting Register 0x10 to 0x1. 2. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F Bi t 0) twice in two consecutive write operations. 3. Write 1 to Register 0x00, Bit 15. 4. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0). Reading Data from Registers Using Interrupts The latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. The data value for each photodiode channel is available as a 16-bit value in Regis- ter 0x64 through Register 0x67 for Time Slot A, and Register 0x68 through Register 0x6B for Time Slot B. If allowed to reach their maximum value, Register 0x64 through Register 0x6B clip. If Register 0x64 through Register 0x6B saturate, the unsaturated (up to 27 bits) values for each channel are available in Register 0x70 through Register 0x77 for Time Slot A and Register 0x78 through Register 0x7F for Time Slot B. Sample interrupts are available to

Rev. B | Page 26 of 52 indicate when the registers are updated and can be read. To use the interrupt for a given time slot, use the following procedure: 1. Enable the sample interrupt by writing a 0 to the appropriate bit in Register 0x01. To enable the interrupt for Time Slot A, write 0 to Bit 5. To enable the interrupt for Time Slot B, write 0 to Bit 6. Either or both interrupts can be set. 2. Configure the interrupt pin by writing the appropriate value to the bits in Register 0x02. 3. An interrupt generates when the data registers are updated. 4. The interrupt handler must perform the following: a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm which interrupt has occurred. This step is not required if only one interrupt is in use. b. Read the data registers before the next sample can b e w ritten. The system must have interrupt latency and service time short enough to respond before the next data update, based on the output data rate. c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the interrupt. If both time slots are in use, it is possible to use only the Time Slot B interrupt to signal when all registers can be read. It is recommended to use the multiword read to transfer the data from the data registers. Reading Data from Registers Without Interrupts If the system interrupt response is not fast or predictable enough to use the interrupt method, or if the interrupt pin is not used, it is possible to get reliable data access by using the data hold mechanism. To guarantee that the data read from the registers is from the same sample time, it is necessary to prevent the update of samples while reading the current values. The method for doing register reads without interrupt timing is as follows: 1. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the time slot requiring access (both time slots can be accessed). This prevents sample updates. 2. Read the registers as desired. 3. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively p reviously set. Sample updates are allowed again. Because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. CLOCKS AND TIMING CALIBRATION The ADPD103 operates using two internal time bases: a 32 kHz clock sets the sample timing, and a 32 MHz clock controls the timing of the internal functions such as LED pulsing and data capture. Both clocks are internally generated and exhibit device- to-device variation of approximately 10% (typical). Heart rate monitoring applications require an accurate time base to achieve an accurate count of beats per minute. The ADPD103 provides a simple calibration procedure for both clocks. 1. Calibrating the 32 kHz clock. This calibrates items associated with the output data rate. Calibration of this clock is important for applications where an accurate data rate is important, such as heart rate measurements. a. Set the sampling frequency to the highest the system can handle, such as 2000 Hz. Because the 32 kHz clock c ontrols sample timing, its frequency is readily accessible via the INT pin. Configure the interrupt by writing the appropriate value to the bits in Register 0x02 and set the interrupt to occur at the sampling frequency by writing 0 t o Register 0x01, Bit 5 or Bit 6. Monitor the INT pin. The interrupt frequency must match the set sample frequency. b. If the monitored interrupt frequency is less than the set sampling frequency, increase the CLK32K_ADJUST bit (Register 0x4B, Bits[5:0]). If the monitored interrupt f requency is larger than the set sampling frequency, decrease the CLK32K_ADJUST bits. c. Repeat Step b until the monitored interrupt signal f requency is close enough to the set sampling frequency. 2. Calibrate the 32 MHz clock. This calibrates items associated with the fine timing within a sample period, such as LED pulse width and spacing, assuming that the 32 kHz clock h as been calibrated. a. Wri te 0x1 to Register 0x5F , Bit 0. b. Enable the CLK_RATIO calculation by writing 0x1 to Register 0x50, Bit 5. This function counts the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. With this function enabled, this cycle value is stored in Register 0xA, Bits[11:0] and nominally this ratio is 2000 (0x7D0). c. C alculate the 32 MHz clock error as follows: Clock Error = 32 MHz × (1 − CLK_RATIO/2000) d. Adjust the frequency by setting Bits[7:0] in Register 0x4D per the following equation: CLK32M_ADJUST = Clock Error/109 kHz e. Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO function. Repeat Step 2b through Step 2e until the desired accuracy is achieved. Write 0x0 to Register 0x5F, Bit 0. Also, set the INT pin back to the mode desired for normal operation.

Rev. B | Page 27 of 52 CALCULATING CURRENT CONSUMPTION The current consumption of the ADPD103 depends on the user selected operating configuration, as described in the following equations. Total Power Consumption To calculate the total power consumption, use Equation 4. LEDBAVGLEDB LEDAAVGLEDADDAVGVDD VI VI VIPowerTotal + ×+ ×= (4) Average VDD Supply Current To calculate the average VDD supply current, use Equation 5. STANDBYVDDPROC SLOTBBAFES LOTAAAFEAVG VDD I Q t I t IDRI ___ )( )(( + + × + × × = (5) w here: DR = the data rate in Hz. IVDD_STANDBY = 3.5 × 10−3 mA. QPROC is an average charge associated with a processing time, as follows:

• Only Time Slot A enabled: QPROC = 0.64 × 10−3 mC
• Only Time Slot B enabled: QPROC = 0.51 × 10−3 mC
• Time Slot A and Time Slot B enabled: QPROC = 0.69 × 10−3 mC 225 / ) 25( +× + = PEAK xAFE LEDx CHANNELSNUMI (6) COUNTPULSE PERIODLEDxOFFSETLEDxtSLOTx __(sec) ×+= (7 ) where: NUM_CHANNELS is the number of active channels. LEDxPEAK is the peak LED current expressed in mA. LEDx_OFFSET is the pulse start time offset expressed in seconds. LEDx_PERIOD is the pulse period expressed in seconds. PULSE_COUNT is the number of pulses. Note that if either Time Slot A or Time Slot B are disabled, IAFE_x = 0 for that respective time slot. Additionally, if operating in digital integrate mode, power savings can be realized by setting Register 0x3C, Bits[8:3] = b010010. This setting disables the band-pass filters that are bypassed in digital integrate mode, changing the AFE power contribution calculation to: 225 / ) 25( +× + = PEAK xAFE LEDx CHANNELSNUMI Average VLEDA Supply Current To calculate the average VLEDA supply current, use Equation 8. ILED_AVG_A = (SLOTA_LED_WIDTH/1 × 106) × LEDAPEAK × DR × PULSE_COUNT (8) where LEDAPEAK is LED1PEAK, LED2PEAK, or LED3PEAK, expressed in mA, for whichever LED is selected for Time Slot A. Average VLEDB Supply Current To calculate the average VLEDB supply current, use Equation 9. ILED_AVG_B = (SLOTB_LED_WIDTH/1 × 106) × LEDBPEAK × DR × PULSE_COUNT (9) where LEDBPEAK is LED1PEAK, LED2PEAK, or LED3PEAK, expressed in mA, for whichever LED is selected for Time Slot B. OPTIMIZING SNR PER WATT The ADPD103 offers a variety of parameters that the user can adjust to achieve the best signal. One of the key goals of system performance is to obtain the best system SNR for the lowest total power. This is often referred to as optimizing SNR/watt. Even in systems where only the SNR matters and power is a secondary concern, there may be a lower power or a high power means of achieving the same SNR. Optimizing for Peak SNR The first step in optimizing for peak SNR is to find a TIA gain and LED level that gives the best performance where the number of LED pulses remains constant. If peak SNR is the goal, the noise section of Table 3 can be used as a guide. It is important to note that the SNR improves as a square root of the number of pulses averaged together, whereas the increase in the LED power consumed is directly proportional to the number of LED pulses. In other words, for every doubling of the LED pulse count, there is a doubling of the LED power consumed and a 3 dB SNR improvement. As a result, avoid any change in the gain configuration that provides less than 3 dB of improvement for a 2× power penalty; any TIA gain configuration that provides more than 3 dB of improvement for a 2× power penalty is a good choice. If peak SNR is the goal and there is no issue saturating the photodiode with LED current at any gain, the 50k TIA gain setting is an optimal choice. After the SNR per pulse per channel is optimized, the user can then increase the number of pulses to achieve the desired system SNR. Optimizing SNR per Watt in a Signal Limited System In practice, optimizing for peak SNR is not always practical. One scenario in which the photoplethysmography (PPG) signal has a poor SNR is the signal limited regime. In this scenario, the LED current reaches an upper limit before the desired dc return level is achieved. Tuning in this case starts where the peak SNR tuning stops. The starting point is nominally a 50k gain, as long as the lowest LED current setting of 8 mA does not saturate the photodiode and the 50k gain provides enough protection against intense back- ground light. In these cases, use a 25k gain as the starting point. The goal of the tuning process is to bring the dc return signal to a specific ADC range, such as 50% or 60%. The ADC range

Rev. B | Page 28 of 52 choice is a function of the margin of headroom needed to prevent saturation as the dc level fluctuates over time. The SNR of the PPG waveform is always some percentage of the dc level. If the target level cannot be achieved at the base gain, increase the gain and repeat the procedure. The tuning system may need to place an upper limit on the gain to prevent saturation from ambient signals. Tuning the Pulse Count After the LED peak current and TIA gain are optimized, increasing the number of pulses per sample increases the SNR by the square root of the number of pulses. There are two ways to increase the pulse count. The pulse count registers (Register 0x31, Bits[15:8], and Register 0x36, Bits[15:8]) change the number of pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8], controls the number of internal samples that are averaged together before the data is sent to the output. Therefore, the number of pulses per sample is the pulse count register multiplied by the number of subsequent samples being averaged. In general, the internal sampling rate increases as the number of internal sample averages increase to maintain the desired output data rate. The SNR/watt is most optimal with pulse count values of 16 or less. Above pulse count values of 16, the square root relationship does not hold in the pulse count register. However, this relationship continues to hold when averaged between samples using Register 0x15. Note that increasing LED peak current increases SNR almost directly proportional to LED power, whereas increasing the number of pulses by a factor of n results in only a nominal√(n) increase in SNR. When using the sample sum/average function (Register 0x15), the output data rate decreases by the number of summed samples. To maintain a static output data rate, increase the sample frequency (Register 0x12) by the same factor as that selected in Register 0x15. For example, for a 100 Hz output data rate and a sample sum/average of four samples, set the sample frequency to 400 Hz. SINGLE AFE CHANNEL MODE When using a single photodiode in an application, and that photodiode is connected to a single AFE channel (see Table 16), the ADPD103 has an option to power down Channel 2, Channel 3, and Channel 4, which places the device in single AFE channel mode. Because three of the four AFE channels are turned off in this mode, the power consumption is considerably reduced. It is important to leave the unused input channels floating for proper device operation. To r un t he device in single AFE channel mode, write 0x38 to Register 0x3C, Bits[8:3]. If it is not required to run the device in single AFE channel mode, leave Register 0x3C, Bits[8:3] at 0x00. TIA_ADC MODE There is a way to put the device into a mode that effectively runs the TIA directly in the ADC without using the analog band-pass filter and integrator. This mode is referred to as TIA_ADC mode. There are two basic applications of TIA_ADC mode. In normal operation, all of the background light is blocked from the signal chain, and therefore cannot be measured. TIA_ADC mode can be used to measure the amount of background/ambient light. This mode can also be used to measure other dc input currents, such as leakage resistance. When the device is in TIA_ADC mode, the band-pass filter and the integrator stage are bypassed. This effectively wires the TIA directly into the ADC. At the set sampling frequency, the ADC samples Channel 1 through Channel 4 (or Channel 5 through Channel 8) in sequential order, and each sample is taken at 1 µs intervals. The TIA is in an inverting configuration; therefore, the signal drops as more light hits the photodiode. Zero light or dark conditions result in approximately 13,000 LSBs from the ADC. To put the ADPD103 in TIA_ADC mode during Time Slot A, write 0xB065 to Register 0x43 to bypass the band-pass filter and integrator. Similarly, to place the ADPD103 in TIA_ADC mode during Time Slot B, write 0xB065 to Register 0x45. One way to monitor dc and pulsed signal at the same time is to operate TIA_ADC mode in one time slot and pulse mode in the other time slot. In TIA_ADC mode, increasing light level causes a decrease in ADC codes because the TIA stage is inverting. Protecting Against TIA Saturation in Normal Operation One of the reasons to monitor TIA_ADC mode is to protect against environments that may cause saturation. One concern when operating in high light conditions, especially with larger photodiodes, is that the TIA stage may become saturated and the ADPD103 continues to communicate data. The resulting saturation is not typical. The TIA, based on its settings, can only handle a certain level of photodiode current. Based on the way the ADPD103 is configured, if there is a current level from the photodiode that is larger than the TIA can handle, the TIA output during the LED pulse effectively extends the current pulse, making it wider. The AFE timing is then violated because the positive portion of the band-pass filter output extends into the negative section of the integration window. Thus, the photosignal is subtracted from itself, causing the output signal to decrease when the effective light signal increases. To measure the response from the TIA and verify that this stage is not saturating, place the device in TIA_ADC mode and slightly modify the timing. Specifically, sweep SLOTx_AFE_OFFSET until two or three of the four channels reach a minimum value (note that TIA is in an inverting configuration). All four channels do not reach this minimum value because, typically, 3 µs LED pulse widths are used and the ADC samples the four channels sequentially at 1 µs intervals. This procedure aligns the ADC

If this minimum value is above 0 LSB, the TIA is not saturated. return the same value, regardless of whether the LED is on or off. baseline LSB value that coincides with a zero signal input. significantly through added noise or decreased dynamic range. TIA_ADC mode can be used to screen for these assembly issues. by the difference of the ADC result after converting it to a current. in identifying gross failures. Table 17. Analog Specifications for TIA_ADC and Digital Integrate Modes

Rev. B | Page 30 of 52 Measuring TIA Input Shunt Resistance Another problem that can occur is for a resistance to develop between the TIA input and another supply or ground on the PCB. These resistances can force the TIA into saturation prematurely. This, in turn, takes away dynamic range from the device in operation and adds a Johnson noise component to the input. To measure these resistances, place the device in TIA_ADC mode in the dark and start by measuring the TIA_ADC offset level with the photodiode inputs disconnected (Register 0x14, Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0). From this, subtract the value of TIA_ADC mode with the darkened photodiode connected and convert the difference into a current. If the value is positive, and the ADC signal decreased, the resistance is to a voltage higher than 1.3 V , such as VDD. Current entering the TIA causes the output to drop. If the output difference is negative due to an increase of codes at the ADC, current is being pulled out of the TIA and there is a shunt resistance to a lower potential than 1.3 V , such as ground. DIGITAL INTEGRATE MODE Digital integrate mode is built into the ADPD103 and allows the device to accommodate longer LED/AFE pulse widths and different types of sensors at the input. The analog integration mode described in the AFE Operation section is ideally suited for applications requiring a large LED duty cycle, or applications that require customization of the sampling scheme. Digital integrate mode allows the integration function to be performed after the ADC in the digital domain. This mode enables the device to handle a much wider range of sensors at the input. In digital integrate mode, the ADC performs a conversion every 1 µs during the integration window. During the integration window, the digital engine either adds to or subtracts from the previous sample. The band-pass filter is bypassed and the integrator is converted to a voltage buffer, allowing the digital engine to perform the integration function. In this mode, after the timing is optimized, the output of the ADC increases as the light level on the photodiode increases. The integration window is a combination of negative and positive windows where the duration of these windows is set by SLOTx_ AFE_WIDTH. At the end of the digital integration window, the resulting sum is sent to the decimate unit as the sample for that LED pulse. There is one sample per time slot for every sample cycle. Table 18 lists the registers required for placing the device in digital integrate mode. There may also be changes needed in the SLOTx_AFE_OFFSET registers and FIFO configuration register (0x11). To read the final value through the FIFO, set the appropriate values in Regis- ter 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. Alternatively, the final output is also available through the data registers; Register 0x64, Register 0x70, and Register 0x74 for Time Slot A, and Register 0x68, Register 0x78, and Register 0x7C for Time Slot B. To put the ADPD103 into digital integration mode during Time Slot A, write 0x1 to Register 0x58, Bit 12. To put the ADPD103 into digital integration mode in Time Slot B, write 0x1 to Register 0x58, Bit 13. The other writes required to switch to digital integration mode are listed in Table 18. When using digital integrate mode, up to two photodiodes can be connected to the ADPD103 inputs; one photodiode per PDx input group (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8). Never connect the same photodiode across the two PDx groups. In digital integrate mode, there are options to connect the photodiode to all four AFE channels (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8), or just a single AFE channel (PD1 or PD5). When connecting to a single AFE channel, write 0x1 to Register 0x54, Bit 14 for Time Slot A, or, for Time Slot B, write 0x1 to Register 0x54, Bit 15. When c onnecting to a single AFE channel, there is also an option to turn off Channel 2, Channel 3, and Channel 4 (and to save power) by writing 0x7 to Register 0x55, Bits[15:13]. When connecting to all four channels (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8), write 0x0 (default)to Register 0x54, Bit 14 for Time Slot A, or write 0x0 (default) to Register 0x54, Bit 15 for Time Slot B. Ensure that all AFE channels are powered up by writing 0x0 to Register 0x55, Bits[15:13]. Connecting the single photodiode to a single AFE channel offers the best SNR performance in cases where signal is limited, whereas connecting the single photodiode to all four AFE channels offers the best dynamic range in cases where signal is large. Digital Integration Sampling Modes There are two sampling modes that can be used while the device is in digital integration mode. These modes are single- sample pair mode and double-sample pair mode. In single-sample pair mode, there is a single negative sample region and a single positive sample region, shown in Figure 29 and Figure 30. To us e single-sample pair mode, write 0x1 to Register 5A, Bit 5 for Time Slot A, or Register 5A, Bit 6 for Time Slot B. The negative sample region starts at SLOTx_AFE_ OFFSET + 9 and its duration (the number of samples taken) is set by SLOTx_AFE_WIDTH. The positive sample region starts at SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH, and its duration is also set by SLOTx_AFE_WIDTH. Set the timing such that the negative sample region falls entirely in the flat (dark) portion of the LED response, whereas the positive sample region falls in the pulsed region of the LED response. Placing the LED pulse offset, SLOTx_LED_OFFSET, at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH achieves this timing. The output is the difference of the signals in the two regions.

Rev. B | Page 31 of 52 Double-sample pair mode is another way to sample. In this mode, there are two negative sample regions and one long positive sample region (see Figure 27 and Figure 28). To us e double-sample pair mode, write 0x0 to Register 0x5A, Bit 5 for Time Slot A, or Bit 6 for Time Slot B. The first negative sample region starts at SLOTx_AFE_OFFSET + 9 and its duration is set by SLOTx_AFE_WIDTH. The positive sample region starts at SLOTx_AFE_OFFSET + 9+ SLOTx_AFE_WIDTH and its duration is twice the SLOTx_AFE_WIDTH. After this, there is another negative sample region that starts at SLOTx_AFE_OFFSET + 9+ 3 × SLOTx_AFE_WIDTH, and its duration is SLOTx_AFE_ WIDTH. Set the timing such that both of the negative sample regions fall in the flat (dark) portion of the LED response and the positive sample region falls in the pulsed portion of the LED response. Placing the LED pulse offset, SLOTx_LED_OFFSET at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_ WIDTH achieves this timing. The output is calculated by summing the response of all the regions in a negative/positive/ negative manner. The double-sample pair mode is useful for cases when the background light is not constant because it has better background rejection, but it also uses more power than single- sample pair mode. Sample Timing Modes There are two options for timing the sample regions: gapped mode and continuous mode. In gapped timing mode, there is a space between the negative and positive sample regions. The width of this region is specified by SLOTA_AFE_FOFFSET for Time Slot A and SLOTB_AFE_ FOFFSET for Time Slot B in microseconds. To enable this feature, write 0x1 to Register 0x5A, Bit 7. This bit enables gapped timing for the time slot (or time slots) that are in digital integrate mode. This mode is helpful when there are unwanted transients in the LED response that must be ignored for an accurate output. If there are no concerns about LED response transients, select continuous timing mode. In this mode, there is no space between the negative and positive sample regions. Write 0x0 to Register 0x5A, Bit 7 for continuous timing of the sample regions. Both gapped and continuous sample timing modes can be used with single-sample pair or double-sample pair mode. Some example timing diagrams are shown in Figure 27, Figure 28, Figure 29, and Figure 30. Background Values In digital integrate mode, the digital integration background value, DI_BACKGROUND, or dark values are also stored and available as output data. This is in addition to the output value during the LED pulse, DI_OUTPUT, which has the dark value subtracted. DI_BACKGROUND is the sum of the negative region samples. To include these values in the FIFO, set Register 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. For 16-bit data, set this value to 0x3; for 32-bit data, set this value to 0x04. These settings are also available through the data registers; Register 0x65, Register 0x71, and Register 0x75 for Time Slot A, and Register 0x69, Register 0x79, and Register 0x7D for Time Slot B. It is recommended that the channel offsets (Register 0x18 to Register 0x21) be set to 0x1F00 when including the background values in the FIFO in digital integration mode. These channel offsets do not affect the sample values, but do provide more headroom for the background values. Saturation Detection in Digital Integrate Mode In normal operation, when using the band-pass filter and the integrator, the ADC almost always saturates before the TIA. Unlike in normal operation, saturation of the TIA or the ADC cannot be detected solely by looking at the signal value where the signal value is the positive sample region minus the reference region in digital integrate mode. This is because the integrated value does not by itself contain any information indicating if one of the ADC conversions during the integration period exceeded the ADC output range. As a result, the real- time output may have saturated only for a fraction of the ADC conversions within a sample and the final accumulated sum may not reflect this. To detect TIA saturation in digital integration mode, both the background values, DI_BACKGROUND, and the signal values, DI_OUTPUT, must be collected. Refer to the Background Values section for the correct settings for Register 0x11 that provide these values. For single-sample pair mode, saturation has occurred when (DI_OUTPUT/(min(LED_WIDTH, AFE_WIDTH)) + DI_BACKGROUND/AFE_WIDTH)/NUM_PULSES > 0x3FFF For double-sample pair mode, saturation has occurred when (DI_OUTPUT/(min(LED_WIDTH, 2 × AFE_WIDTH)) + DI_BACKGROUND/(2 × AFE_WIDTH))/NUM_PULSES > 0x3FFF

Rev. B | Page 32 of 52 SLOTx_AFE_OFFSET + 9 SUB SUBADD LED SAMPLE 12722-021 F igure 27. Digital Integration Mode in Double-Sample Pair Mode with Continuous Sample Timing SLOTx_AFE_OFFSET + 9 AFE_FOFFSET AFE_FOFFSET SUB SUBADD LED SAMPLE 12722-022 F igure 28. Digital Integration Mode in Double-Sample Pair Mode with Gapped Sample Timing 12722-023 SLOTx_AFE_OFFSET + 9 SUB ADD LED SAMPLE AFE_FOFFSET F igure 29. Digital Integration Mode in Single-Sample Pair Mode with Gapped Sample Timing 12722-024 SLOTx_AFE_OFFSET + 9 SUB ADD LED SAMPLE F igure 30. Digital Integration Mode in Single-Sample Pair Mode with Continuous Sample Timing

Table 18. Configuration Registers to Switch Between the Normal Sample Mode, TIA_ADC Mode, and Digital Integration Mode configures the integrator block as a buffer. 0x43 [15:0] SLOTA_AFE_CFG 0xADA5 0xB065 0xAE65 Time Slot A AFE connection. 0 xAE65 bypasses the band-pass filter. configures the integrator block as a buffer. 0x45 [15:0] SLOTB_AFE_CFG 0xADA5 0xB065 0xAE65 Time Slot B AFE connection. 0 xAE65 bypasses the band-pass filter. 0 xB065 bypasses the BPF and the integrator. Not applicable 0x0040 Set ADC Clock to 1 MHz in TIA_ADC mode. 0x58 13 SLOTB_DIGITAL_INT_EN 0x0 0x0 0x1 Digital integrate mode enable Time Slot B. 12 S LOTA_DIGITAL_INT_EN 0x0 0x0 0x1 Digital integrate mode enable Time Slot A.

Table 19. Numeric Register Listing1

Rev. B | Page 35 of 52 Hex Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x22 ILED3_ COARSE [15:8] Reserved[15:14] ILED3_ SCALE Reserved[12:8] 0x3000 R/W [7:0] Reserved ILED3_SLEW[6:4] ILED3_COARSE[3:0] 0x23 ILED1_ COARSE [15:8] Reserved[15:14] ILED1_ SCALE Reserved[12:8] 0x3000 R/W [7:0] Reserved ILED1_SLEW[6:4] ILED1_COARSE[3:0] 0x24 ILED2_ COARSE [15:8] Reserved[15:14] ILED2_ SCALE Reserved[12:8] 0x3000 R/W [ 7:0] Reserved ILED2_SLEW[6:4] ILED2_COARSE[3:0] 0x25 ILED_ FINE [15:8] ILED3_FINE[15:11] ILED2_FINE[10:8] 0x630C R/W [7:0] ILED2_FINE[7:6] Reserved ILED1_FINE[4:0] 0x30 SLOTA_ LED_ PULSE [15:8] Reserved[15:13] SLOTA_LED_WIDTH[12:8] 0x0320 R/W [ 7:0] SLOTA_LED_OFFSET[7:0] 0x31 SLOTA_ NUM- PULSES [15:8] SLOTA_LED_NUMBER[15:8] 0x0818 R/W [ 7:0] SLOTA_LED_PERIOD[7:0] 0x34 LED_ DISABLE [15:8] Reserved[15:10] SLOTB_LED_ DIS SLOTA_ LED_DIS 0x0000 R/W [7:0] Reserved[7:0] 0x35 SLOTB_ LED_ PULSE [15:8] Reserved[15:13] SLOTB_LED_WIDTH[12:8] 0x0320 R/W [ 7:0] SLOTB_LED_OFFSET[7:0] 0x36 SLOTB_ NUM- PULSES [15:8] SLOTB_LED_NUMBER[15:8] 0x0818 R/W [ 7:0] SLOTB_LED_PERIOD[7:0] 0x38 TIMING_ CFG [15:8] Reserved EXT_SYNC_ ENA Reserved[13:8] 0x000 R/W [ 7:0] Reserved[7:0] 0x39 SLOTA_ AFE_ WINDOW [15:8] SLOTA_AFE_WIDTH[15:11] SLOTA_AFE_OFFSET[10:8] 0x22FC R/W [ 7:0] SLOTA_AFE_OFFSET[10:5] SLOTA_AFE_FOFFSET[4:0] 0x3B SLOTB_ AFE_ WINDOW [15:8] SLOTB_AFE_WIDTH[15:11] SLOTB_AFE_OFFSET[10:8] 0x22FC R/W [ 7:0] SLOTB_AFE_OFFSET[10:5] SLOTB_AFE_FOFFSET[4:0] 0x3C AFE_PWR _CFG1 [15:8] Reserved[15:14] Reserved[13:11] Reserved V_ CATHODE AFE_ POWER-DOWN 0x3006 R/W [7:0] AFE_POWERDOWN[7:3] Reserved[2:0] 0x42 SLOTA_ TIA_CFG [15:8] SLOTA_AFE_MODE[15:8] 0x1C38 R/W [ 7:0] Reserved SLOTA_ TIA_ IND_EN Reserved[5:2] (write 0xD) SLOTA_TIA_GAIN[1:0] 0x43 SLOTA_ AFE_CFG [15:8] SLOTA_AFE_CFG[15:8] 0xADA5 R/W [7:0] SLOTA_AFE_CFG[7:0] 0x44 SLOTB_ TIA_CFG [15:8] SLOTB_AFE_MODE[15:8] 0x1C38 R/W [ 7:0] Reserved SLOTB_ TIA_ IND_EN Reserved[5:2] (write 0xD) SLOTB_TIA_GAIN[1:0] 0x45 SLOTB_ AFE_CFG [15:8] SLOTB_AFE_CFG[15:8] 0xADA5 R/W [7:0] SLOTB_AFE_CFG[7:0] 0x4B SAMPLE_ CLK [15:8] Reserved[15:8] 0x2612 R/W [7:0] CLK32K_EN Reserved CLK32K_ADJUST[5:0] 0x4D CLK32M_ ADJUST [15:8] RESERVED[15:8] 0x425E R/W [ 7:0] CLK32M_ADJUST[7:0] 0x4E ADC_ CLOCK [15:8] ADC_CLOCK[15:8] 0x0060 R/W [7:0] ADC_CLOCK[7:0] 0x4F EXT_ SYNC_SEL [15:8] Reserved[15:8] 0x2090 R/W [7:0] Reserved PDSO_ OE PDSO_IE Reserved EXT_SYNC_SEL[3:2] INT_IE Reserved

Rev. B | Page 36 of 52 Hex Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x50 CLK32M_ CAL_EN [15:8] Reserved[15:8] 0x0000 R/W [7:0] Reserved PDSO_ CTRL CLK32M_ CAL_EN Reserved[4:0] 0x54 AFE_PWR _CFG2 [15:8] SLOTB_SIN- GLE_CH_ DIG_INT SLOTA_ SINGLE_ CH_DIG_ INT SLEEP_V_CATHODE[13:12] SLOTB_V_ CATHODE[11:10] SLOTA_V_CATHODE[9:8] 0x0020 R/W [7:0] REG54_VCAT_ ENABLE Reserved[6:0] 0x55 TIA_IN- DEP_ GAIN [15:8] DIGINT_POWER[15:13] Reserved SLOTB_TIA_GAIN_4 [11:10] SLOTB_TIA_GAIN_3[9:8] 0x0000 R/W [7:0] SLOTB_TIA_GAIN_2[7:6] SLOTA_TIA_GAIN_4[5:4] SLOTA_TIA_GAIN_3[3:2] SLOTA_TIA_GAIN_2[1:0] 0x58 DIGITAL_ INT_EN [15:8] Reserved[15:14] SLOTB_ DIGITAL_ INT_EN SLOTA_ DIGITAL_INT_ EN Reserved[11:8] 0x0000 R/W [7:0] Reserved[7:0] 0x5A DIG_INT_ CFG [15:8] Reserved[15:8] 0x0000 R/W [7:0] DIG_INT_ GAPMODE SLOTB_ DIG_INT_ SAMPLE- MODE SLOTA_ DIG_INT_ SAMPLE- MODE Reserved[4:0] 0x5F DATA_AC CESS_ CTL [15:8] Reserved[15:8] 0x0000 R/W [ 7:0] Reserved[7:3] SLOTB_ DATA_ HOLD SLOTA_DAT A_HOLD DIGITAL_ CLOCK_ENA 0x60 FIFO_ ACCESS [15:8] FIFO_DATA[15:8] 0x0000 R [7:0] FIFO_DATA[7:0] 0x64 SLOTA_ PD1_ 16BIT [15:8] SLOTA_CH1_16BIT[15:8] 0x0000 R [ 7:0] SLOTA_CH1_16BIT[7:0] 0x65 SLOTA_ PD2_ 16BIT [15:8] SLOTA_CH2_16BIT[15:8] 0x0000 R [ 7:0] SLOTA_CH2_16BIT[7:0] 0x66 SLOTA_ PD3_ 16BIT [15:8] SLOTA_CH3_16BIT[15:8] 0x0000 R [7:0] SLOTA_CH3_16BIT[7:0] 0x67 SLOTA_ PD4_ 16BIT [15:8] SLOTA_CH4_16BIT[15:8] 0x0000 R [ 7:0] SLOTA_CH4_16BIT[7:0] 0x68 SLOTB_ PD1_ 16BIT [15:8] SLOTB_CH1_16BIT[15:8] 0x0000 R [ 7:0] SLOTB_CH1_16BIT[7:0] 0x69 SLOTB_ PD2_ 16BIT [15:8] SLOTB_CH2_16BIT[15:8] 0x0000 R [ 7:0] SLOTB_CH2_16BIT[7:0] 0x6A SLOTB_ PD3_ 16BIT [15:8] SLOTB_CH3_16BIT[15:8] 0x0000 R [ 7:0] SLOTB_CH3_16BIT[7:0] 0x6B SLOTB_ PD4_ 16BIT [15:8] SLOTB_CH4_16BIT[15:8] 0x0000 R [ 7:0] SLOTB_CH4_16BIT[7:0] 0x70 A_PD1_ LOW [15:8] SLOTA_CH1_LOW[15:8] 0x0000 R [ 7:0] SLOTA_CH1_LOW[7:0] 0x71 A_PD2_ LOW [15:8] SLOTA_CH2_LOW[15:8] 0x0000 R [7:0] SLOTA_CH2_LOW[7:0] 0x72 A_PD3_ LOW [15:8] SLOTA_CH3_LOW[15:8] 0x0000 R [ 7:0] SLOTA_CH3_LOW[7:0] 0x73 A_PD4_ LOW [15:8] SLOTA_CH4_LOW[15:8] 0x0000 R [ 7:0] SLOTA_CH4_LOW[7:0] 0x74 A_PD1_ HIGH [15:8] SLOTA_CH1_HIGH[15:8] 0x0000 R [ 7:0] SLOTA_CH1_HIGH[7:0]

Rev. B | Page 37 of 52 Hex Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x75 A_PD2_ HIGH [15:8] SLOTA_CH2_HIGH[15:8] 0x0000 R [7:0] SLOTA_CH2_HIGH[7:0] 0x76 A_PD3_ HIGH [15:8] SLOTA_CH3_HIGH[15:8] 0x0000 R [ 7:0] SLOTA_CH3_HIGH[7:0] 0x77 A_PD4_ HIGH [15:8] SLOTA_CH4_HIGH[15:8] 0x0000 R [ 7:0] SLOTA_CH4_HIGH[7:0] 0x78 B_PD1_ LOW [15:8] SLOTB_CH1_LOW[15:8] 0x0000 R [ 7:0] SLOTB_CH1_LOW[7:0] 0x79 B_PD2_ LOW [15:8] SLOTB_CH2_LOW[15:8] 0x0000 R [ 7:0] SLOTB_CH2_LOW[7:0] 0x7A B_PD3_ LOW [15:8] SLOTB_CH3_LOW[15:8] 0x0000 R [ 7:0] SLOTB_CH3_LOW[7:0] 0x7B B_PD4_ LOW [15:8] SLOTB_CH4_LOW[15:8] 0x0000 R [ 7:0] SLOTB_CH4_LOW[7:0] 0x7C B_PD1_ HIGH [15:8] SLOTB_CH1_HIGH[15:8] 0x0000 R [7:0] SLOTB_CH1_HIGH[7:0] 0x7D B_PD2_ HIGH [15:8] SLOTB_CH2_HIGH[15:8] 0x0000 R [ 7:0] SLOTB_CH2_HIGH[7:0] 0x7E B_PD3_ HIGH [15:8] SLOTB_CH3_HIGH[15:8] 0x0000 R [7:0] SLOTB_CH3_HIGH[7:0] 0x7F B_PD4_ HIGH [15:8] SLOTB_CH4_HIGH[15:8] 0x0000 R [ 7:0] SLOTB_CH4_HIGH[7:0] 1 Recommended values not shown. Only power-on reset values are in Table 19. The recommended values are largely dependent on use case. See Table 20 to Table 26 for the recommended values.

Table 20. LED Control Registers 0x14 [15:12] 0x0 R/W Reserved Write 0x0 to these bits for proper operation. [ 11:8] 0x5 R/W SLOTB_PD_SEL PDx connection selection for Time Slot B. See Figure 13. 0x1: All photodiode inputs are connected during Time Slot B. 0x 4: PD5/PD6/PD7/PD8 are connected during Time Slot B. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot B. [7:4] 0x4 R/W SLOTA_PD_SEL PDx connection selection for Time Slot A. See Figure 13. 0x 1: All photodiode inputs are connected during Time Slot A. 0 x4: PD5/PD6/PD7/PD8 are connected during Time Slot A. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot A. associated with Time Slot B. 0x 1: LEDX1 pulses during Time Slot B. 0x 2: LEDX2 pulses during Time Slot B. 0x3: LEDX3 pulses during Time Slot B. associated with Time Slot A. 0x1: LEDX1 pulses during Time Slot A. 0x 2: LEDX2 pulses during Time Slot A. 0x3: LEDX3 pulses during Time Slot A. 0x22 [15:14] 0x0 R/W Reserved Write 0x0. 13 0x 1 R/W ILED3_SCALE LEDX3 current scale factor. 0 : 40% strength; sets the LEDX3 driver in low power mode. LE DX3 Current Scale = 0.4 + 0.6 × (Register 0x22, Bit 13). 12 0x 1 R/W Reserved Write 0x1. [ 11:7] 0x0 R/W Reserved Write 0x0. LEDX3 in standard operation. LED3PEAK is the LEDX3 peak target value (mA).

Rev. B | Page 39 of 52 Address Data Bit Default Value Access Name Description 0x23 [15:14] 0x0 R/W Reserved Write 0x0. 13 0x 1 R/W ILED1_SCALE LEDX1 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX1 driver in low power mode. LE DX1 Current Scale = 0.4 + 0.6 × (Register 0x23, Bit 13). 12 0x 1 R/W Reserved Write 0x1. [ 11:7] 0x0 R/W Reserved Write 0x0. [6:4] 0x0 R/W ILED1_SLEW LEDX1 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0 : the slowest slew rate. 7 : the fastest slew rate. [ 3:0] 0x0 R/W ILED1_COARSE LEDX1 coarse current setting. Coarse current sink target value of LEDX1 in standard operation. 0: 25 mA. 1: 40 mA. 2: 55 mA. 15: 250 mA. LED1PEAK = LED1COARSE × LED1FINE × LED1SCALE w here: LED1PEAK is the LEDX1 peak target value (mA). LED1COARSE = 28 + 15.46 × (Register 0x23, Bits[3:0]). LED1FINE = 0.71 + 0.024 × (Register 0x25, Bits[4:0]). LED1SCALE = 0.4 + 0.6 × (Register 0x23, Bit 13). 0x24 [15:14] 0x0 R/W Reserved Write 0x0. 13 0x 1 R/W ILED2_SCALE LEDX2 current scale factor. 1: 100% strength. 0 : 40% strength; sets the LEDX2 driver in low power mode. LED2 Current Scale = 0.4 + 0.6 × (Register 0x24, Bit 13) 12 0x 1 R/W Reserved Write 0x1. [ 11:7] 0x0 R/W Reserved Write 0x0. [ 6:4] 0x0 R/W ILED2_SLEW LEDX2 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0 : the slowest slew rate. 7: the fastest slew rate. [3:0] 0x0 R/W ILED2_COARSE LEDX2 coarse current setting. Coarse current sink target value of LED2 in standard operation. See Register 0x23, Bits[3:0] for values. L ED2PEAK = LED2COARSE × LED2FINE × LED2SCALE w here: LED2PEAK is the LEDX2 peak target value (mA). LED2COARSE = 28 + 15.46 × (Register 0x24, Bits[3:0]). LED2FINE = 0.71 + 0.024 × (Register 0x25, Bits[10:6]). LED2SCALE = 0.4 + 0.6 × (Register 0x24, Bit 13).

Rev. B | Page 40 of 52 Address Data Bit Default Value Access Name Description 0x25 [15:11] 0xC R/W ILED3_FINE LEDX3 fine adjust. Current adjust multiplier for LED3. L EDX3 fine adjust = 0.71 + 0.024 × (Register 0x25, Bits[15:11]). S ee Register 0x22, Bits[3:0], for the full LED3 formula. [ 10:6] 0xC R/W ILED2_FINE LEDX2 fine adjust. Current adjust multiplier for LED2. L EDX2 fine adjust = 0.71 + 0.024 × (Register 0x25, Bits[10:6]). S ee Register 0x24, Bits[3:0], for the full LED2 formula. 5 0x 0 R/W Reserved Write 0x0. [ 4:0] 0xC R/W ILED1_FINE LEDX1 fine adjust. Current adjust multiplier for LED1. LEDX1 fine adjust = 0.71 + 0.024 × (Register 0x25, Bits[4:0]). S ee Register 0x23, Bits[3:0], for the full LED1 formula. 0x30 [15:13] 0x0 R/W Reserved Write 0x0. [ 12:8] 0x3 R/W SLOTA_LED_WIDTH LED pulse width (in 1 μs step) for Time Slot A. [7:0] 0x20 R/W SLOTA_LED_OFFSET LED offset width (in 1 μs step) for Time Slot A. 0x31 [15:8] 0x08 R/W SLOTA_LED_NUMBER LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A. This is typically LED1. Adjust in the application. A setting of six pulses (0x06) is typical. [ 7:0] 0x18 R/W SLOTA_LED_PERIOD LED Time Slot A pulse period (in 1 μs step). 0x34 [15:10] 0x00 R/W Reserved Write 0x0. 9 0x0 R/W SLOTB_LED_DIS Time Slot B LED disable. 1: disables the LED assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. 8 0x 0 R/W SLOTA_LED_DIS Time Slot A LED disable. 1: disables the LED assigned to Time Slot A. Us e Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. [ 7:0] 0x00 R/W Reserved Write 0x00. 0x35 [15:13] 0x0 R/W Reserved Write 0x0. [ 12:8] 0x3 S LOTB_LED_WIDTH LED pulse width (in 1 μs step) for Time Slot B. [ 7:0] 0x20 SL OTB_LED_OFFSET LED offset width (in 1 μs step) for Time Slot B. 0x36 [15:8] 0x08 R/W SLOTB_LED_NUMBER LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B. This is typically LED2. A setting of six pulses (0x06) is typical. [ 7:0] 0x18 R/W SLOTB_LED_PERIOD LED Time Slot B pulse period (in 1 μs step). 0x3C [15:14] 0x0 R/W RESERVED Write 0x0. [ 13:11] 0x6 R/W RESERVED Write 0x6. 10 0x0 R/ W Reserved Write 0x0. 9 0x0 R/ W V_CATHODE 0x0: 1.3 V (identical to anode voltage); recommended setting. 0 x1: 1.8 V (reverse bias photodiode by 550 mV; this setting may add noise). [ 8:3] 0x0 R/W AFE_POWERDOWN AFE channels power-down select. 0 x38: powers down AFE Channel 2, Channel 3, and Channel 4. 0 x0: keeps all channels on. [ 2:0] 0x6 R/W Reserved Write 0x6.

Table 21. AFE Global Configuration Registers 0x3C [15:14] 0x0 R/W RESERVED Write 0x0. [ 13:11] 0x6 R/W RESERVED Write 0x6. 10 0x 0 R/W Reserved Write 0x0. [8:3] 0x0 R/W AFE_POWERDOWN AFE channels power-down select. 0 x0: keeps all channels on. [ 2:0] 0x6 R/W Reserved Write 0x6. integration. This limits connection to PD1 or PD5. integration. This limits connection to PD1 or PD5. always set to the cathode voltage in sleep mode. voltage is always 1.3 V in Time Slot B mode. 0 x3: 0.0 V (this forward biases a diode at the input). voltage is always 1.3 V in Time Slot A mode. 0 x3: 0.0 V (this forward biases a diode at the input). defined by Register 0x54, Bits[13:8]. [ 6:0] 0x20 R/W Reserved Write 0x20.

Rev. B | Page 42 of 52 Address Data Bit Default Value Access Name Description 0x58 [15:14] 0x0 R/W Reserved Write 0x0. 13 0x0 R/ W SLOTB_DIGITAL_INT_EN 0x0: Time Slot B operating in normal mode. 0x1: Time Slot B operating in digital integration mode. 12 0x0 R/ W SLOTA_DIGITAL_INT_EN 0x0: Time Slot A operating in normal mode. 0x1: Time Slot A operating in digital integration mode. [11 :0] 0x000 R/W Reserved Write 0x000. 0x5A [15:8] 0x00 R/W Reserved Write 0x00. 7 0x0 R/ W DIG_INT_GAPMODE Digital integrate gapped mode enable. 0: n o gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in μs. 6 0x0 R/ W SLOTB_DIG_INT_SAMPLE_MODE Digital integrate single sample pair mode for Time Slot B. 0: double sample pair mode. 1: s ingle sampled pair mode. 5 0x0 R/ W SLOTA_DIG_INT_SAMPLE_MODE Digital integrate single sample pair mode for Time Slot A. 0: d ouble sample pair mode. 1: single sampled pair mode. [4:0] 0x00 R/W Reserved Write 0x00. Ta ble 22. AFE Configuration Registers, Time Slot A Address Data Bit Default Value Access Name Description 0x39 [15:11] 0x4 R/W SLOTA_AFE_WIDTH AFE integration window width (in 1 μs step) for Time Slot A. [10: 5] 0x17 R/W SLOTA_AFE_OFFSET AFE integration window coarse offset (in 1 μs step) for Time Slot A. [4:0] 0x1C R/W SLOTA_AFE_FOFFSET AFE integration window fine offset (in 31.25 ns step) for Time Slot A. 0x42 [15:8] 0x1C R/W SLOTA_AFE_MODE 0x1C: Time Slot A AFE setting for normal mode. All four blocks of the signal chain are in use during normal mode (the TIA, the BPF , followed by the integrator (INT), and finally the ADC). 0x1D: Time Slot A AFE setting for digital integrate mode. 7 0x0 R/ W Reserved Write 0x0. 6 0x0 R/ W SLOTA_TIA_IND_EN Enable Time Slot A TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[5:0]. 0: d isable TIA gain individual setting. 1: ena ble TIA gain individual setting. [5: 2] 0xE R/W Reserved Reserved. Write 0xD. [1: 0] 0x0 R/W SLOTA_TIA_GAIN Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA gain settings. 0: 200 k Ω. 1: 100 kΩ. 2: 50 k Ω. 3: 25 k Ω.

Rev. B | Page 43 of 52 Address Data Bit Default Value Access Name Description 0x43 [15:0] 0xADA5 R/W SLOTA_AFE_CFG AFE connection in Time Slot A. 0x ADA5: analog full path mode (TIA_BPF_INT_ADC). 0xB065: TIA_ADC mode. 0xA E65: digital integration mode. Ot hers: reserved. 0x55 [15:13] 0x0 R/W DIGINT_POWER Power-down for Channel 2, Channel 3, and Channel 4 in digital integration mode. 0: k eep all channels powered up. 7: powers down Channel 2, Channel 3, and Channel 4. 12 0x0 R/ W Reserved Write 0x0. [1 1:10] 0x0 R/W SLOTB_TIA_GAIN_4 TIA gain for Time Slot B, Channel 4 (PD4). 0: 200 kΩ 1: 100 k Ω. 2: 50 k Ω. 3: 25 kΩ. [9: 8] 0x0 R/W SLOTB_TIA_GAIN_3 TIA gain for Time Slot B, Channel 3 (PD3). 0: 200 kΩ 1: 100 k Ω. 2: 50 kΩ. 3: 25 k Ω. [7: 6] 0x0 R/W SLOTB_TIA_GAIN_2 TIA gain for Time Slot B, Channel 2 (PD2). 0: 200 k Ω 1: 100 kΩ. 2: 50 k Ω. 3: 25 k Ω. [5: 4] 0x0 R/W SLOTA_TIA_GAIN_4 TIA gain for Time Slot A, Channel 4 (PD4). 0: 200 kΩ 1: 100 k Ω. 2: 50 kΩ. 3: 25 k Ω. [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 TIA gain for Time Slot A, Channel 3 (PD3). 0: 200 k Ω 1: 100 kΩ. 2: 50 kΩ. 3: 25 k Ω. [1: 0] 0x0 R/W SLOTA_TIA_GAIN_2 TIA gain for Time Slot A, Channel 2 (PD2). 0: 200 k Ω 1: 100 k Ω. 2: 50 k Ω. 3: 25 kΩ.

Rev. B | Page 44 of 52 Address Data Bit Default Value Access Name Description 0x5A [15:8] 0x0 R/W Reserved Write 0x0. 7 0x0 R/ W DIG_INT_GAPMODE Digital integration gapped mode enable. 0: n o gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in μs. 6 0x0 R/W SLOTB_DIG_INT_SAMPLEMODE Digital integration single-sample pair mode for Time Slot B. 0: do uble sample pair mode. 1: si ngle-sampled pair mode. 5 0x0 R/ W SLOTA_DIG_INT_SAMPLEMODE Digital integration single-sample pair mode for Time Slot A. 0: double sample pair mode. 1: si ngle-sampled pair mode. [4: 0] 0x0 R/W Reserved Write 0x0. Ta ble 23. AFE Configuration Registers, Time Slot B Address Data Bit Default Value Access Name Description 0x3B [15:11] 0x4 R/W SLOTB_AFE_WIDTH AFE integration window width (in 1 μs step) for Time Slot B. [10: 5] 0x17 R/W SLOTB_AFE_OFFSET AFE integration window coarse offset (in 1 μs step) for Time Slot B. [4: 0] 0x1C R/W SLOTB_AFE_FOFFSET AFE integration window fine offset (in 31.25 ns step) for Time Slot B. 0x44 [15:8] 0x1C R/W SLOTB_AFE_MODE 0x1C: Time Slot B AFE setting for normal mode (TIA_BPF_INT_ADC). 0x1D: Time Slot B AFE setting for digital integrate mode. 7 0x0 R/ W Reserved Write 0x0. 6 0x0 R/W SLOTB_TIA_IND_EN Enable Time Slot B TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[11:6]. 0: d isable TIA gain individual setting. 1: en able TIA gain individual setting. [5: 2] 0xE R/W Reserved Write 0xD. [1: 0] 0x0 R/W SLOTB_TIA_GAIN Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 k Ω. 1: 100 k Ω. 2: 50 k Ω. 3: 25 k Ω. 0x45 [15:0] 0xADA5 R/W SLOTB_AFE_CFG AFE connection in Time Slot B. 0x ADA5: analog full path mode (TIA_BPF_INT_ADC). 0xB 065: TIA_ADC mode. 0x AE65: digital integration mode. Others: reserved.

Rev. B | Page 45 of 52 Address Data Bit Default Value Access Name Description 0x58 [15:14] 0x0 R/W Reserved Write 0x0. 13 0x0 R/ W DIG_INT_EN_B Digital integration mode, enable Time Slot B. 0: disable. 1: en able. 12 0x0 R/ W DIG_INT_EN_A Digital integration mode, enable Time Slot A. 0: d isable. 1: en able. [1 1:0] 0x0000 R/W Reserved Write 0x0000.

Table 24. System Registers is in words, where one word = two bytes. clear the contents of the FIFO. 7 0x0 R/W Reserved Write 0x1 to clear this bit to 0x0. to this register has no effect. [4: 0] 0x00 R/W Reserved Write 0x1F to clear these bits to 0x00. length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. 7 0x1 R/W R eserved Write 0x1. interrupt. Write a 0 to enable the interrupt. interrupt. Write a 0 to enable the interrupt. [4: 0] 0x1F R/W Reserved Write 0x1F. 2 0x0 R/ W INT_ENA INT pin enable. 0: d isable the INT pin. The INT pin floats regardless of interrupt status. The status register (Address 0x00) remains active. 1 0x0 R/ W INT_DRV INT drive. 0: t he INT pin is always driven. 0 0x0 R/W INT_POL INT polarity. 0: t he INT pin is active high. 1: t he INT pin is active low. 0x06 [15:14] 0x0 R/W Reserved Write 0x0. FIFO no longer exceeds the value in FIFO_THRESH. [7: 0] 0x00 R/W Reserved Write 0x00. 0x08 [15:8] 0x04 R REV_NUM Revision number. [7: 0] 0x16 R DEV_ID Device ID.

Rev. B | Page 47 of 52 Address Data Bit Default Access Name Description 0x09 [15:8] 0x0 W ADDRESS_WRITE_KEY Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access. [7: 1] 0x64 R/W SLAVE_ADDRESS I2C slave address. 0 0x0 R Reserved Do not access. 0x0A [15:12] 0x0 R Reserved Reserved. Read only. [1 1:0] 0x000 R CLK_RATIO When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. 0x0D [15:0] 0x0 R/W SLAVE_ADDRESS_KEY Enable changing the I2C address using Register 0x09. 0x0 4AD: enable address change always. 0x4 4AD: enable address change if INT is high. 0x8 4AD: enable address change if PDSO is high. 0xC 4AD: enable address change if both INT and PDSO are high. 0x0F [15:1] 0x0000 R Reserved Reserved. Read only. 0 0x0 R/W SW_RESET Software reset. Write 0x1 to reset the device. This bit clears itself after a reset. This command does not return an acknowledge because the command is instantaneous. 0x10 [15:2] 0x000 R/W Reserved Write 0x000. [1: 0] 0x0 R/W Mode Determines the operating mode of the ADPD103. 0x0: standby. 0x 1: program. 0x 2: normal operation. 0x11 [15:14] 0x0 R/W Reserved Write 0x0. 13 0x0 R/ W RDOUT_MODE Readback data mode for extended data registers 0x0: Block sum of N samples 0x1: Block average of N samples 12 0x1 R/ W FIFO_OVRN_PREVENT 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). [1 1:9] 0x0 R/W Reserved Write 0x0. [8: 6] 0x0 R/W SLOTB_FIFO_MODE Time Slot B FIFO data format. 0: no data to FIFO. 1: 16 -bit sample in digital integration mode or 16-bit sum of all 4 channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all 4 channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode 4: 32 -bit sample and 32-bit background value in digital integration mode or 4 channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: 4 c hannels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Ot hers: reserved. Th e selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). 5 0x0 R/ W SLOTB_EN Time Slot B enable. 1: enables Time Slot B.

Rev. B | Page 48 of 52 Address Data Bit Default Access Name Description [4:2] 0x 0 R/W SLOTA_FIFO_MODE Time Slot A FIFO data format. 0: no data to FIFO. 1: 16 -bit sample in digital integration mode or 16-bit sum of all 4 channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all 4 channels when not in digital integration mode. 3: 16-b it sample and 16-bit background value in digital integration mode 4: 32-bit sample and 32-bit background value in digital integration mode or 4 channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: 4 channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Ot hers: reserved. 1 0x0 R/ W Reserved Write 0x0. 0 0x0 R/ W SLOTA_EN Time Slot A enable. 1: enables Time Slot A. 0x38 15 0x0 R/W Reserved Write 0x0. 14 0x0 R/ W EXT_SYNC_ENA Enables external sampling trigger. 0x 0: samples triggered internally. 0x 1: samples triggered externally. Must be set to 1 if EXT_SYNC_SEL is b01 or b10. [13: 0] 0x0 R/W Reserved Write 0x0. 0x4B [15:9] 0x13 R/W Reserved Write 0x13. 8 0x0 R/ W CLK32K_BYP Bypass internal 32 kHz clock oscillator. 0x0: normal operation. 0x1 : use an external clock on the PDSO pin. 7 0x0 R/ W CLK32K_EN Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x 1: normal operation. 6 0x0 R/ W Reserved Write 0x0. [5: 0] 0x12 R/W CLK32K_ADJUST Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. No te that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. 0x4D [15:8] 0x42 R/W Reserved Write 0x42. [7: 0] 0x5E R/W CLK32M_ADJUST Internal timing (32 MHz) clock frequency adjust. This register is used to calibrate the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See t he Clocks and Timing Calibration section for more information regarding clock adjustment. 00 00 0000: minimum frequency. 0101 1110: default frequency. 11 11 1111: maximum frequency. 0x4E1 [15:0] 0x0060 R/W ADC_TIMING1 0x0040: ADC clock speed = 1 MHz. 0x00 60: ADC clock speed = 500 kHz.

Rev. B | Page 49 of 52 Address Data Bit Default Access Name Description 0x4F [15:7] 0x41 R/W Reserved Write 0x41. 6 0x0 R/ W PDSO_OE PDSO pin output enable. 5 0x0 R/ W PDSO_IE PDSO pin input enable. 4 0x1 R/ W Reserved Write 0x1. [3: 2] 0x0 R/W EXT_SYNC_SEL Sample sync select. 00: us e the internal 32 kHz clock with FSAMPLE to select sample timings. 01: us e the INT pin to trigger sample cycle. 10: us e the PDSO pin to trigger sample cycle. 11: reserved. 1 0x0 R/ W INT_IE INT pin input enable. 0 0x0 R/W Reserved Write 0x0. 0x50 [15:7] 0x000 R/W Reserved Write 0x000. 6 0x0 R/ W PDSO_CTRL Controls the PDSO output when the PDSO output is enabled (PDSO_OE = 0x1). 0x0 : PDSO output driven low. 0x1: PDSO output driven by the AFE power-down signal. 5 0x0 R/ W CLK32M_CAL_EN As part of the 32 MHz clock calibration routine, write 1 to begin the clock ratio calculation. Read the result of this calculation from the CLK_RATIO bits in Register 0x0A. Res et this bit to 0 prior to reinitiating the calculation. [4:0] 0x0 R/W Reserved Write 0x0. 0x5F [15:3] 0x0000 R/W Reserved Write 0x0000. 2 0x0 R/ W SLOTB_DATA_HOLD Setting this bit prevents the update of the data registers corresponding to Time Slot B. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: h old data registers for Time Slot B. 0: allow data register update. 1 0x0 R/ W SLOTA_DATA_HOLD Setting this bit prevents the update of the data registers corresponding to Time Slot A. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: h old data registers for Time Slot A. 0: allow data register update. 0 0x0 R/ W FIFO_ACCESS_ENA Set to 1 twice to enable FIFO access. It is necessary to write 1 to the FIFO_ACCESS_ENA bit in two consecutive write operations in order to read data from the FIFO. During clock calibration, set to 1 to force the 32 MHz clock to run. For power savings, reset to 0 when the previously described operations are complete. 1 Clock speed setting is only relevant during digital integrate mode.

Table 25. ADC Registers 0x12 [15:0] 0x0028 R/W FSAMPLE Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] × 4). 0x15 [15:11] 0x0 R/W Reserved Write 0x0. which can be used to increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. 7 0x 0 R/W Reserved Write 0x0. Time Slot A. See description in Register 0x15, Bits[10:8]. [ 3:0] 0x0 R/W Reserved Write 0x0. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical. value. A value of 0x2000 is typical.

Table 26. Data Registers Bit 0). Reset this bit to 0 when the FIFO access sequence is complete. 0x64 [15:0] R SLOTA_CH1_16BIT 16-bit value of Channel1 in Time Slot A. 0x65 [15:0] R SLOTA_CH2_16BIT 16-bit value of Channel 2 in Time Slot A. 0x66 [15:0] R SLOTA_CH3_16BIT 16-bit value of Channel 3 in Time Slot A. 0x67 [15:0] R SLOTA_ CH4_16BIT 16-bit value of Channel 4 in Time Slot A. 0x68 [15:0] R SLOTB_ CH1_16BIT 16-bit value of Channel 1 in Time Slot B. 0x69 [15:0] R SLOTB_CH2_16BIT 16-bit value of Channel 2 in Time Slot B. 0x6A [15:0] R SLOTB_CH3_16BIT 16-bit value of Channel 3 in Time Slot B. 0x6B [15:0] R SLOTB_CH4_16BIT 16-bit value of Channel 4 in Time Slot B. 0x70 [15:0] R SLOTA_CH1_LOW Low data-word for Channel 1 in Time Slot A. 0x71 [15:0] R SLOTA_CH2_LOW Low data-word for Channel 2 in Time Slot A. 0x72 [15:0] R SLOTA_CH3_LOW Low data-word for Channel 3 in Time Slot A. 0x73 [15:0] R SLOTA_CH4_LOW Low data-word for Channel 4 in Time Slot A. 0x74 [15:0] R SLOTA_CH1_HIGH High data-word for Channel 1 in Time Slot A. 0x75 [15:0] R SLOTA_CH2_HIGH High data-word for Channel 2 in Time Slot A. 0x76 [15:0] R SLOTA_CH3_HIGH High data-word for Channel 3 in Time Slot A. 0x77 [15:0] R SLOTA_CH4_HIGH High data-word for Channel 4 in Time Slot A. 0x78 [15:0] R SLOTB_CH1_LOW Low data-word for Channel 1 in Time Slot B. 0x79 [15:0] R SLOTB_CH2_LOW Low data-word for Channel 2 in Time Slot B. 0x7A [15:0] R SLOTB_CH3_LOW Low data-word for Channel 3 in Time Slot B. 0x7B [15:0] R SLOTB_CH4_LOW Low data-word for Channel 4 in Time Slot B. 0x7C [15:0] R SLOTB_CH1_HIGH High data-word for Channel 1 in Time Slot B. 0x7D [15:0] R SLOTB_CH2_HIGH High data-word for Channel 2 in Time Slot B. 0x7E [15:0] R SLOTB_CH3_HIGH High data-word for Channel 3 in Time Slot B. 0x7F [15:0] R SLOTB_CH4_HIGH High data-word for Channel 4 in Time Slot B. Table 27. Required Start-Up Load Sequence 1 0x4B, Bit 7 Write to 0x1 to enable the clock that drives the state machine. 2 0x10 Write 0x0001 to enter program mode. 3 Other registers Register order is not important while the device is in program mode. 4 0x10 Write 0x0002 to start normal sampling operation.

Rev. B | Page 52 of 52 OUTLINE DIMENSIONS 2.70 2.60 SQ 2.50 0.80 0.75 0.70 TOP VIEW EXPOSED PAD BOTTOM VIEW PKG-003523 10.40 BSC 814 PIN 1 INDICATOR 0.45 0.40 0.35SEATING PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.08 PIN 1 INDICATOR 0.25 0.20 0.15 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TOJEDEC STANDARDS MO-220-WGGE. 4.10 4.00 SQ 3.90 06-23-2015-B

0.20 MIN

ure 31. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-28-5) Dimensions shown in millimeters BOTTOM VIEW (BALL SIDE UP) A B C D E F 0.560 0.500 0.440 1.44 1.40 1.36 2.50 2.46 2.42 123 0.300 0.260 0.220 0.40 BSC 0.300 0.225 0.235 2.00 REF BALL A1 IDENTIFIER 02-03-2015-B SEATING PLANE 0.230 0.200 0.170 0.330 0.300 0.270 COPLANARITY 0.05 TOP VIEW (BALL SIDE DOWN) END VIEW PKG-004659 Fig ure 32. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-18) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADPD103BCPZ −40°C to +85°C 28-Lead LFCSP_WQ CP-28-5 ADPD103BCPZRL −40°C to +85°C 28-Lead LFCSP_WQ CP-28-5 ADPD103BCBZRL7 −40°C to +85°C 16-Ball WLCSP CB-16-18 EVAL-ADPD103Z-GEN Ge neric ADPD103 Evaluation Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12722-0-2/16(B)