ADPA9002

ADPA9002 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 19

Technical content

GaAs, pHEMT, MMIC, Single Positive Supply, DC to 10 GHz Power Amplifier Data Sheet ADPA9002 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

OP1dB: 29 dBm typical Gain: up to 15 dB typical OIP3: up to 43 dBm typical Self biased at VDD = 12 V at 385 mA typical with an optional bias control on VGG1 for IDQ adjustment 50 Ω matched input/output 32-lead, 5 mm × 5 mm LFCSP

APPLICATIONS

18 NIC

19 NIC

20 GND

21 RFOUT/VDD

22 GND

23 NIC

24 GND

25 GND

26 NIC

27 NIC

28 NIC

29 ACG2

30 ACG1

31 NIC

32 GND

Figure 1. GENERAL DESCRIPTION The ADPA9002 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), power amplifier that operates between dc and 10 GHz. The amplifier provides 15 dB of gain, 42 dBm of OIP3, and 31.5 dBm of saturated output power (P SAT) while requiring 385 mA from a 12 V supply. The ADPA9002 is self biased in normal operation and has an optional bias control for supply quiescent current (IDQ) adjustment. The amplifier is ideal for military and space and test equipment applications. The ADPA9002 also features inputs and outputs that are internally matched to 50 Ω, housed in a RoHS compliant, 5 mm × 5 mm LFCSP premolded cavity package, making it compatible with high volume surface-mount technology (SMT) assembly equipment. Note that throughout this data sheet, multifunction pins, such as RFOUT/V DD, are referred to either by the entire pin name or by a single function of the pin, for example, VDD, when only that function is relevant.

Rev. 0 | Page 2 of 19 TABLE OF CONTENTS

REVISION HISTORY

10/2019—Revision 0: Initial Version

Rev. 0 | Page 3 of 19 SPECIFICATIONS DC TO 2 GHz TA = 25°C, VDD = 12 V, IDQ = 385 mA, VGG1= GND for nominal self biased operation, and frequency range = dc to 2 GHz, with a 50 Ω matched input and output, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE DC 2 GHz GAIN 12.5 14.5 dB Gain Variation Over Temperature ±0.01 dB/°C NOISE FIGURE 5 dB RETURN LOSS Input 18 dB Output 14 dB OUTPUT Output Power for 1 dB Compression OP1dB 27 29 dBm Saturated Output Power PSAT 31 dBm Output Third-Order Intercept OIP3 43 dBm Measurement taken at output power (POUT) per tone = 14 dBm SUPPLY Quiescent Current IDQ 385 mA For external bias control, adjust VGG1 between −2 V and +0.5 V to achieve the desired IDQ Drain Voltage VDD 10 12 15 V

2 GHz TO 5 GHz

TA = 25°C, VDD = 12 V , IDQ = 385 mA, VGG1 = GND for nominal self biased operation, and frequency range = 2 GHz to 5 GHz, unless otherwise noted. 50 Ω matched input/output. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 2 5 GHz GAIN 13 15 dB Gain Variation Over Temperature ±0.008 dB/°C NOISE FIGURE 3 dB RETURN LOSS Input 14 dB Output 15 dB OUTPUT Output Power for 1 dB Compression OP1dB 27 29 dBm Saturated Output Power PSAT 31.5 dBm Output Third-Order Intercept OIP3 42 dBm Measurement taken at POUT per tone = 14 dBm SUPPLY Quiescent Current IDQ 385 mA For external bias control, adjust VGG1 between −2 V and +0.5 V to achieve the desired IDQ Drain Voltage VDD 10 12 15 V

Rev. 0 | Page 4 of 19

5 GHz TO 10 GHz

TA = 25°C, VDD = 12 V , IDQ = 385 mA, VGG1 = GND for nominal self biased operation, and frequency range = 5 GHz to 10 GHz, with a 50 Ω matched input and output, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 5 10 GHz GAIN 13.5 15.5 dB Gain Variation Over Temperature ±0.016 dB/°C NOISE FIGURE 4 dB RETURN LOSS Input 19 dB Output 13 dB OUTPUT Output Power for 1 dB Compression OP1dB 25 28 dBm Saturated Output Power PSAT 31 dBm Output Third-Order Intercept OIP3 40.5 dBm Measurement taken at POUT/tone = 14 dBm SUPPLY Quiescent Current IDQ 385 mA For external bias control, adjust VGG1 between −2 V and +0.5 V to achieve the desired IDQ Drain Voltage VDD 10 12 15 V

Table 5. Thermal Resistance

1. NIC = NOT INTERNALLY CONNECTED. THESE PINS

MUST BE CONNECTED TO RF AND DC GROUND.

1. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED TO RF AND DC GROUND. Figure 2. Pin Configuration Table 6. Pin Function Descriptions GND Ground. These pins must be connected to RF and dc ground. NIC Not Internally Connected. These pins must be connected to RF and dc ground. 5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. (see Figure 62). See Figure 7 for the interface schematic. capacitor required (see Figure 62). See Figure 4 and Figure 5 for the interface schematics. 21 RFOUT/VDD RF Output for the Amplifier (RFOUT). Drain Voltage (VDD). Connect the VDD network to provide the drain current (IDD) (see Figure 62). See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.

transmission line interconnecting the drains of the upper FETs. Figure 61. Simplified Schematic of the Cascode Distributed Amplifier schematic of this architecture is shown in Figure 61. drain currents from 250 mA to 450 mA can be obtained. bias, requiring an RF choke through which dc bias is applied.

200 MHz, allowing the flattest possible gain response to be

obtained over various frequencies.

Figure 62. Both the RFIN and RFOUT/VDD pins are dc-coupled. Use of an external dc blocking capacitor at RFIN is recommended. use across the entire frequency range of the application. VGG1 pin within −2 V to +0.5 V to set the target drain.

1. Connect the VGG1 pin to ground and ground all GND pins.
2. Apply the RF signal to the RFIN pin.
3. Turn off the RFIN signal.
4. Connect all GND pins to ground.
5. Set the VGG1 pin to − 2 V.
6. Increase the VGG1 pin to achieve the IDQ.
7. Apply the RF signal to the RFIN pin.
8. Turn off the RFIN signal.
9. Decrease the VGG1 pin to −2 V to achieve a typical IDQ of 0 mA.

Absolute Maximum Ratings section. capacitors if the device is operated below 200 MHz.

21 RFOUT

1. DRAIN VOLTAGE (VDD) MUST BE APPLIED THROUGH AN ETERNAL BIAS TEE CONNECTED

AT THE RFOUT/VDD PIN AND AN EXTERNAL DC BLOCK MUST BE CONNECTED AT THE RFIN PIN.

1. USE OPTIONAL CAPACITORS IF THE DEVICE IS OPERATED BELOW 200MHz.

Figure 62. Typical Application Circuit

3.50 REF

0.035 NOM

0.203 REF

0.60 REF

Figure 63. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV] 2 See the Absolute Maximum Ratings section for additional information. 3 The lead finish of the ADPA9002ACGZN and the ADPA9002ACGZN-R7 is nickel palladium gold (NiPdAu). registered trademarks are the property of their respective owners.