ADPA7008 AD | Alldatasheet

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Technical content

20 GHz to 54 GHz, GaAs, pHEMT, MMIC, 31 dBm (1 W) Power Amplifier

Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.

FEATURES

► Output P1dB: 30 dBm typical at 22 GHz to 40 GHz ► PSAT: 31 dBm typical at 22 GHz to 40 GHz ► Gain: 17.5 dB typical at 22 GHz to 40 GHz ► Input return loss: 12 dB typical at 22 GHz to 40 GHz ► Output return loss: 9.5 dB typical at 22 GHz to 40 GHz ► Output IP3: 37 dBm typical at 22 GHz to 40 GHz ► Supply voltage: 5 V typical at 1500 mA ► 50 Ω matched input and output ► 18-terminal, 7 mm × 7 mm, ceramic leadless chip carrier with heat sink [LCC_HS] ► Integrated power detector

APPLICATIONS

► Aerospace and defense ► Test instrumentation ► Communications GENERAL DESCRIPTION The ADPA7008 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrat- ed circuit (MMIC), 31 dBm saturated output power (PSAT, 1 W) distributed power amplifier with an integrated temperature compen- sated on-chip power detector that operates from 20 GHz to 54 GHz. The amplifier provides 17.5 dB of small signal gain, an output power for 1 dB compression (P1dB) of 30 dBm with an excellent IP3 of 37 dBm typical from 22 GHz to 40 GHz. The ADPA7008 is ideal for linear applications such as electronic countermeasure and instrumentation applications requiring 31 dBm of efficient PSAT. The ADPA7008 requires 1500 mA from a 5 V supply voltage (VDD). The RF input and outputs are internally matched and dc blocked for ease of integration into higher level assemblies. The ADPA7008 is housed in a 7 mm × 7 mm, ceramic leadless package with heat sink [LCC_HS] that exhibits low thermal resistance and is compatible with surface-mount manufacturing techniques. FUNCTIONAL BLOCK DIAGRAM Figure 1.

analog.com Rev. 0 | 2 of 28 Biasing the ADPA7008 with the Low Noise Limiting VGATE for the ADPA7008 VGGx Constant Drain Current Biasing vs.

REVISION HISTORY

7/2021—Revision 0: Initial Version

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20 GHZ TO 22 GHZ FREQUENCY RANGE

TA = 25°C, VDD = 5 V, quiescent supply current (IDQ) = 1500 mA, and 50 Ω matched input and output, unless otherwise noted. Adjust VGG1 from −1.5 V to −0.4 V to achieve IDQ = 1500 mA typical. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 20 22 GHz GAIN 14.5 17 dB Gain Flatness ±0.3 dB Gain Variation Over Temperature 0.022 dB/°C NOISE FIGURE 8 dB RETURN LOSS Input 14 dB Output 12 dB OUTPUT Output Power for 1 dB Compression P1dB 26.5 29 dBm Saturated Output Power PSAT 30 dBm Output Third-Order Intercept IP3 34 dBm Output power (POUT) per tone = 14 dBm with 1 MHz tone spacing POWER ADDED EFFICIENCY PAE 10 % Measured at PSAT SUPPLY Quiescent Current IDQ 1500 mA Adjust VGG1, from −1.5 V up to −0.4 V to achieve the desired IDQ, VGGx = −0.63 V typical to achieve IDQ= 1500 mA Voltage VDD 4 5 V

22 GHZ TO 40 GHZ FREQUENCY RANGE

TA = 25°C, VDD = 5 V, IDQ = 1500 mA, and 50 Ω matched input and output, unless otherwise noted. Adjust VGG1 from −1.5 V to −0.4 V to achieve IDQ = 1500 mA typical. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 22 40 GHz GAIN 15 17.5 dB Gain Flatness ±1.2 dB Gain Variation Over Temperature 0.022 dB/°C NOISE FIGURE 7.0 dB RETURN LOSS Input 12 dB Output 9.5 dB OUTPUT Output Power for 1 dB Compression P1dB 27.5 30 dBm Saturated Output Power PSAT 31 dBm Output Third-Order Intercept IP3 37 dBm POUT per tone = 14 dBm with 1 MHz tone spacing POWER ADDED EFFICIENCY PAE 11.5 % Measured at PSAT SUPPLY Quiescent Current IDQ 1500 mA Adjust VGG1, from −1.5 V up to −0.4 V to achieve the desired IDQ, VGGx = −0.63 V typical to achieve IDQ= 1500 mA Voltage VDD 4 5 V

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40 GHZ TO 50 GHZ FREQUENCY RANGE

TA = 25°C, VDD = 5 V, IDQ = 1500 mA, and 50 Ω matched input and output, unless otherwise noted. Adjust VGG1 from −1.5 V to −0.4 V to achieve IDQ = 1500 mA typical. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 40 50 GHz GAIN 16 dB Gain Flatness ±1.1 dB Gain Variation Over Temperature 0.039 dB/°C NOISE FIGURE 7 dB RETURN LOSS Input 15 dB Output 13 dB OUTPUT Output Power for 1 dB Compression P1dB 27.5 dBm Saturated Output Power PSAT 29 dBm Output Third-Order Intercept IP3 36 dBm POUT per tone = 14 dBm with 1 MHz tone spacing POWER ADDED EFFICIENCY PAE 7 % Measured at PSAT SUPPLY Quiescent Current IDQ 1500 mA Adjust VGG1, from −1.5 V up to −0.4 V to achieve the desired IDQ, VGGx = −0.63 V typical to achieve IDQ= 1500 mA Voltage VDD 4 5 V

50 GHZ TO 54 GHZ FREQUENCY RANGE

TA = 25°C, VDD = 5 V, IDQ = 1500 mA, and 50 Ω matched input and output, unless otherwise noted. Adjust VGG1 from −1.5 V to −0.4 V to achieve IDQ = 1500 mA typical. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 50 54 GHz GAIN 15.5 dB Gain Flatness ±1.0 dB Gain Variation Over Temperature 0.049 dB/°C RETURN LOSS Input 10 dB Output 9 dB OUTPUT Output Power for 1 dB Compression P1dB 24.5 dBm Saturated Output Power PSAT 27 dBm Output Third-Order Intercept IP3 35 dBm POUT per tone = 14 dBm with 1 MHz tone spacing POWER ADDED EFFICIENCY PAE 4 % Measured at PSAT SUPPLY Quiescent Current IDQ 1500 mA Adjust VGG1, from −1.5 V up to −0.4 V to achieve the desired IDQ, VGGx = −0.63 V typical to achieve IDQ = 1500 mA Voltage VDD 4 5 V

ing conditions for extended periods may affect product reliability. PCB thermal design is required. exposed metal ground pad on the underside of the device). Table 6. Thermal Resistance 1 The thermal resistance varies with operating conditions. 2 The worst case across all specified operating conditions. sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 7. ADPA7008, 18-Terminal LCC_HS damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 52. Detector Voltage (VREF − VDET) vs. Frequency

amplifiers operating in quadrature between six 90° hybrids. signal that is proportional to the RF output (see Figure 67). Figure 67. ADPA7008 Architecture

Figure 69. Basic Connections for Operation with the South Side Gate Voltage Biasing

BIASING THE ADPA7008 WITH THE LOW NOISE LTM8063 analog.com Rev. 0 | 23 of 28 To ensure clean circuit turn off when VIN (Figure 73) turns off, the ADP196-01 load switch with quick output discharge has been add- ed to the drain voltage generation path. The ADP196-01 ensures that VDD turns off fully when VIN is around 8.5 V before VGG turns off when VIN is at 2.54 V. The ADP196-01 has a very small package (1 mm × 1.5 mm WLCSP) and requires no external components, resulting in a minimal increase in PCB area.

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 85. 18-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HC] 2 For the ADPA7008AEHZ and the ADPA7008AEHZ-R7, the MSL Rating is MSL3.