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Technical content
GaAs, pHEMT, MMIC,1/2 W,
20 GHz to 44 GHz, Power Amplifier
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FEATURES
Output P1dB: 28 dBm (typical at 34 GHz to 44 GHz) PSAT: 30 dBm (typical at 20 GHz to 34 GHz) Gain: 15 dB (typical at 34 GHz to 44 GHz) IP3: 40 dBm (typical) Supply voltage: 5 V at 600 mA Die size: 2.75 mm × 1.805 mm × 0.1 mm
APPLICATIONS
F igure 1. GENERAL DESCRIPTION The ADPA7002CHIP is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), distributed power amplifier that operates from 20 GHz to 44 GHz. The amplifier provides 15 dB of small signal gain, 28 dBm output power at 1 dB gain compression (P1dB), and a typical output third-order intercept (IP3) of 40 dBm. The amplifier requires 600 mA from a 5 V supply on VDD2A, VDD2B, and VDD1. The ADPA7002CHIP also features inputs/outputs (I/Os) that are internally matched to 50 Ω, and facilitates integration into multichip modules (MCMs). All data is taken with the on substrate chip connected via two wire bonds that are 0.025 mm (1 mil) wide and 0.31 mm (12 mils) long. RFOUTRFIN ADPA7002CHIP GND VDET VREF VDD2AVGG1 VDD2B VDD1 17236-001
Rev. 0 | Page 2 of 23 TABLE OF CONTENTS Mounting and Bonding Techniques for Millimeter Wave
REVISION HISTORY
2/2019—Revision 0: Initial Version
Rev. 0 | Page 3 of 23 SPECIFICATIONS FREQUENCY RANGE: 20 GHz TO 34 GHz TA = 25°C, VDD = 5 V, quiescent drain supply current (IDQ) = 600 mA, for nominal operation, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 20 34 GHz GAIN 15 17 dB Gain Flatness ±0.5 dB Gain Variation over Temperature 0.012 dB/°C NOISE FIGURE 6 dB RETURN LOSS Input 20 dB Output 20 dB OUTPUT Output Power for 1 dB Compression P1dB 26 28.5 dBm Saturated Output Power PSAT 30 dBm Output Third-Order Intercept IP3 40 dBm Measurement taken at saturated output power (POUT) per tone = 14 dBm SUPPLY Quiescent Drain Supply Current IDQ 600 mA Adjust the gate bias voltage (VGG1) between −2 V to 0 V to achieve the desired IDQ Voltage VDD 4 5 V FREQUENCY RANGE: 34 GHz TO 44 GHz TA = 25°C, VDD = 5 V, IDQ = 600 mA, for nominal operation, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 34 44 GHz GAIN 12 15 dB Gain Flatness ±0.7 dB Gain Variation over Temperature 0.024 dB/°C NOISE FIGURE 5 dB RETURN LOSS Input 25 dB Output 16 dB OUTPUT Output Power for 1 dB Compression P1dB 25 28 dBm Saturated Output Power PSAT 28.5 dBm Output Third-Order Intercept IP3 40 dBm Measurement taken at POUT per tone = 14 dBm SUPPLY Quiescent Drain Supply Current IDQ 600 mA Adjust the gate bias voltage (VGG1) between −2 V to 0 V to achieve the desired IDQ Voltage VDD 4 5 V
Rev. 0 | Page 4 of 23 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Drain Bias Voltage (VDD) 6.0 V Gate Bias Voltage (VGG1) −1.5 to 0 V Radio Frequency Input Power (RFIN) 25 dBm Continuous Power Dissipation (PDISS), T = 85°C (Derate 75.2 mW/°C above 85°C) 6.77 W Storage Temperature Range −65°C to +150°C Operating Temperature Range −55°C to +85°C Nominal Junction Temperature (T = 85°C, VDD = 5 V, IDQ = 600 mA) 124.9°C Junction Temperature to Maintain 1,000,000 Hour Mean Time to Failure (MTTF) 175°C Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Class 1A (passed 500 V) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Figure 2. Pin Configuration Table 4. Pin Function Descriptions 1 RFIN Radio Frequency (RF) Signal Input. This pad is ac-coupled and matched to 50 Ω. 2 to 9, 14, 16, 19, 21 NIC No Internal Connection. These pads have no internal connections. 10 V REF Reference Diode for Temperature Compensation of V DET RF Output Power Measurements. 11, 22, Die Bottom GND Ground. These pads and the di e bottom must be connected to RF and dc ground. 12 RFOUT RF Signal Output. This pad is ac-coupled and matched to 50 Ω. voltage that is proportional to the RF output power. 15, 17, 18 V DD1, VDD2A, VDD2B Drain Biases for Amplifier. External bypass ca pacitors of 4.7 μF and 0.01 μF are required. 20 V GG1 Gate Control for Amplifier. External bypass ca pacitors of 4.7 μF and 0.01 μF are required.
- NIC = NO INTERNAL CONNECTION. THESE PADS HAVE NO INTERNAL CONNECTION.
Figure 57. Alternate Assembly Diagram
Figure 69. 22-Pad Bare Die [CHIP] 1 The ADPA7002C-KIT is a sample order of two devices. *This die utilizes fragile air bridges. Any pickup tools used must not contact this area. registered trademarks are the property of their respective owners.