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46 dBm (40 W), 0.9 GHz to 1.6 GHz, GaN Power Amplifier Data Sheet ADPA1105 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Output power with PIN = 19 dBm: 46 dBm typical Small signal gain: 34.5 dB typical at 0.9 GHz to 1.4 GHz Power gain with PIN = 19 dBm: 27 dB typical Bandwidth: 0.9 GHz to 1.6 GHz PAE with P IN = 19 dBm: 60% typical at 0.9 GHz to 1.4 GHz Supply voltage: VDD = 50 V at 400 mA on 10% duty cycle 32-Lead, 5 mm × 5 mm, LFSCP_CAV package
APPLICATIONS
19 GND
20 RFOUT
21 RFOUT
24 GND
28 VDD2
31 VDD1
32 GND
Figure 1. GENERAL DESCRIPTION The ADPA1105 is a gallium nitride (GaN), broadband power amplifier that delivers 46 dBm (40 W) with 60% typical power added efficiency (PAE) across a bandwidth of 0.9 GHz to 1.4 GHz. The ADPA1105 provides ±0.5 dB gain flatness across a bandwidth of 0.9 GHz to 1.4 GHz. The ADPA1105 is ideal for pulsed applications such as wireless infrastructure, radar, public mobile radio, and general-purpose amplifications. The ADPA1105 comes in a 32-lead, lead frame chip scale package, premolded cavity (LFCSP_CAV).
Rev. 0 | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 3 of 16 SPECIFICATIONS ELECTRICAL SPECIFICATIONS TA = 25°C, supply voltage (VDD) = 50 V, IDQ = 400 mA, pulse width = 100 μs, 10% duty cycle, and frequency range = 0.9 GHz to 1.4 GHz, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 0.9 1.4 GHz GAIN Small Signal Gain 32 34.5 dB Gain Flatness ±0.5 dB RETURN LOSS Input 16 dB Output 9 dB POWER Output Power (POUT) Input Power (PIN) = 19 dBm 44 46 dBm Power Gain PIN = 19 dBm 25 27 dB PAE PIN = 19 dBm 60 % TARGET QUIESCENT CURRENT I DQ 400 mA Adjust the gate control voltage (VGG1, VGG2) to be between −4 V and 0 V to achieve an IDQ = 400 mA typical value TA = 25°C, VDD = 50 V, IDQ = 400 mA, pulse width = 100 μs, 10% duty cycle, and frequency range = 1.4 GHz to 1.6 GHz, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 1.4 1.6 GHz GAIN Small Signal Gain 30.5 32.5 dB Gain Flatness ±0.9 dB RETURN LOSS Input 11 dB Output 14 dB POWER POUT PIN = 19 dBm 44 46 dBm Power Gain PIN = 19 dBm 25 27 dB PAE PIN = 19 dBm 57 % TARGET QUIESCENT CURRENT I DQ 400 mA Adjust the gate control voltage (VGG1, VGG2) to be between −4 V and 0 V to achieve an IDQ = 400 mA typical value
1 Worst case frequency for PDISS. the PCB thermal design is required. JC is the junction to case thermal resistance (°C/W) of the device. Table 4. Thermal Resistance
1 The θJC value was determined by measuring θJC under the following
held constant at the operating temperature of 85°C. ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 5. ADPA1105, 32-Lead LFCSP_CAV
- THE NC PINS ARE NOT CONNECTED INTERNALLY.
- EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF AND DC GROUND. Figure 2. Pin Configuration Table 6. Pin Function Descriptions GND The GND pins must be connected to RF and dc ground. See Figure 6 for the interface schematic. connected to RF and dc ground externally. 4, 5 RFIN RF Input. The RFIN pins are ac-coupled and are matched to 50 Ω. See Figure 3 for the interface schematic. 10 V GG1 Gate Control, First Stage Gate Bias. S ee Figure 3 for the interface schematic. 11 V GG2 Gate Control, Second Stage Gate Bias. See Figure 4 for the interface schematic. requires the application of a dc bias voltage through an external series resistor. 20, 21 RFOUT RF Output. The RFOUT pins are ac-coupled and are matched to 50 Ω. See Figure 4 for the interface schematic. 28 V DD2 Amplifier Power Supply Voltage, Second Stage Drain Bias. See Figure 4 for the interface schematic. 31 V DD1 Amplifier Power Supply Voltage, First Stage Drain Bias. See Figure 3 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground. Figure 3. RFIN, VGG1, and VDD1 Interface Figure 4. RFOUT, VGG2, VDD2, and VDET Interface Figure 5. VREF Interface Figure 6. GND Interface
Figure 37. PAE vs. Frequency at Various Pulse Widths
55 POUT
Figure 39. POUT, Gain, PAE, and Supply Current (IDD) vs. PIN Figure 41. POUT, Gain, PAE, and IDD vs. Input Power Figure 42. POUT, Gain, PAE, and IDD vs. PIN
the basic block diagram in Figure 49. 50 Ω over the 0.9 GHz to 1.6 GHz operating frequency range. components or ac coupling capacitors. 1.5 GHz when the input power is 19 dBm. is proportional to the RF output. Figure 49. Basic Block Diagram
pins, VGG1 and VGG2, and drive the pins as shown in Figure 50. Pin 27, Pin 29, and Pin 30 are designated as no connect (NC) pins. and provide some additional thermal relief. that are farthest from the device. that is proportional to the RF output power. voltage or the drain voltage. to achieve the desired quiescent drain current. voltage during the on time of the pulse. Figure 50. Basic Connection
3.50 REF
0.050 MAX
0.035 NOM
0.203 REF
0.60 REF
Figure 53. 32-Lead Lead frame Chip Scale Package, Premolded Cavity [LFCSP_CAV] 1 All models are RoHS compliant parts. 2 The lead finish of the ADPA1105ACGZN and the ADPA1105ACGZN-R7 is nickel palladium gold (NiPdAu). 3 When ordering the evaluation board, use the reference model number ADPA1105-EVALZ. 4 See the Absolute Maximum Ratings section for more information. registered trademarks are the prop erty of their respective owners.