ADP8140 (Rev. B)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 23
Technical content
Rev. B | Page 2 of 23 TABLE OF CONTENTS
REVISION HISTORY
9/2020—Rev. A to Rev. B 9/2018—Rev. 0 to Rev. A 2/2015—Revision 0: Initial Version
Rev. B | Page 3 of 23 SPECIFICATIONS VIN = 12 V , EN = DIM = VT = 3.0 V , MIN = MODE = 0 V . Typical values are at TJ = 25°C and are not guaranteed. Minimum and maximum limits are guaranteed from TJ = −40°C to +125°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY Input Voltage Operating Range VIN 3.0 30.0 V Undervoltage Lockout V UVLO 2.85 2.95 V Quiescent Current During Standby IQ(STBY) EN = 0 V, VIN = 3.3 V to 30 V 200 μA During Operation IQ(ACTIVE) EN = 3 V, VIN = 3.3 V to 30 V, R SET = 71.5 kΩ 4.1 4.5 mA REG Output Output Voltage VREG1 VIN = 3.3 V to 30 V, I REG = 1 mA 2.85 3.0 3.15 V V REG2 VIN = 3 V, I REG = 1 mA 2.85 2.95 V Source Current IREGMAX VIN = 3.3 V to 30 V 15 mA Load Regulation VIN = 3.3 V to 30 V, IREG = 0.1 mA to 15 mA 0.75 mV/mA FEEDBACK OUTPUT FB_OUT Error Amplifier (EA) Accuracy VEA(450) 430 450 476 mV V EA(350) 324 350 380 mV FB_OUT NMOS Pull-Down Current IFB_PD SINKx = 0 V, FB_OUT = 3 V 12.0 15.0 18.0 mA FB_OUT Stage Gain GFB Force 1.2 V and 1.3 V on COMP , measure FB_OUT current (FB_OUT = 12 V) 12500 17000 22000 μmho FB_OUT Fault Current I FB_FC Fault activated, FB_OUT = 30 V 0.04 1 μA Amplifier Transconductance COMP GM 30 60 120 μmho Amplifier Transconductance Output Source COMPSOURCE COMP pin output source current 110 μA Sink COMPSINK COMP pin output sink current 1.5 mA Resistance COMP RO 20 MΩ Low Gain EA GBUFF Gain in buffer mode (MODE = 30.1 kΩ to GND) 3.6 3.9 4.2 Low Gain Bandwidth MODE = 30.1 kΩ to GND 100 kHz I S E T Accuracy ILED_500 R SET = 5.11 kΩ, SINKx = 600 mV 475 500 525 mA I LED_350 R SET = 7.32 kΩ, SINKx = 600 mV 332.5 350 367.5 mA I LED_100 R SET = 25.5 kΩ, SINKx = 600 mV 95 100 105 mA I LED_35 R SET = 71.5 kΩ, SINKx = 600 mV 33.0 35 37.5 mA Shorted Current ISET = GND 500 570 620 mA Open Current ISET = open 15 17 mA CURRENT SINKS Current Sink Headroom Voltage at Maximum Current VHR_500 R SET = 5.11 kΩ, ILED = 95% × ILED_500 320 430 mV V HR_350 R SET = 7.32 kΩ, ILED = 95% × ILED_350 210 324 mV Current at 350 mV IHR_350 Maximum guaranteed current using the 350 mV reference option 350 mA Sink Matching Matching = (ISINK_MAX − ISINK_MIN)/(ISINK_MAX + ISINK_MIN) × 100 At 500 mA Current I MATCH500 0.2 2 % At 350 mA Current I MATCH350 0.25 2 % At 100 mA Current I MATCH100 0.25 2 % At 35 mA Current IMATCH35 0.3 2 %
Rev. B | Page 4 of 23 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SINKx Leakage Current I SINK(LKG) SINKx pin = 4 V 8 12 μA Channel Clamp Threshold Low V CH_CLMP_LOW Threshold on SINKx to trigger VCH_CLMP_LOW, MIN pin = GND 7.4 7.75 8.1 V High V CH_CLMP_HIGH Threshold on SINKx to trigger V CH_CLMP_HIGH 14.5 15.1 15.7 V Channel Clamp Current Low ICLMP_LOW Channel pull-down current when SINKx > CHCLMP_LOW, RSET = 7.32 kΩ 315 350 385 mA High ICLMP_HIGH Channel pull-down current when SINKx > CHCLMP_HIGH 430 510 600 mA Channel Clamp Hysteresis V CH_CLMP_HYS Hysteresis after either channel clamp is triggered 1.2 V Lowest SINKx Current Output current for DIM = 0 V and RSET = 10 kΩ (see Figure 15) 125 μA INPUT CONTROLS Input Threshold (Low) V IL 0.6 V Input Threshold (High) V IH 1.1 V EN Input Resistance REN EN = 1.2 V 400 kΩ MODE Pin Pull-Up Current I M 15 20 24 μA MODE Threshold 1, 30.1 kΩ V M1 Threshold for increasing mode voltage to enter dc buffer operation 0.35 0.4 0.45 V MODE Threshold 2, 52.3 kΩ V M2 Threshold for increasing mode voltage to enter PWM buffer operation 0.75 0.8 0.85 V MODE Threshold 3 VM3 Threshold for increasing mode voltage to enter PWM EA operation 1.25 1.3 1.35 V LED SCALING CONTROLS DIM and VT Limit Voltage VT LIMIT VT (and DIM if MODE = GND) voltage to produce 100% output current 1.9 2.0 2.1 V Dimming Accuracy ILED_DIM1 I LED_DIM1/ILED_100, VT = 1 V, MIN = 0 V, RSET = 25.5 kΩ 48 50 52 % I LED_DIM2 ILED_DIM2/ILED_100, DIM = 0.2 V, MODE = GND, RSET = 25.5 kΩ 9.4 10 10.4 % I LED_DIM3 ILED_DIM3/ILED_100, DIM = 50%,140 Hz, MODE = REG, RSET = 25.5 kΩ 48 50 52 % VT Pull-Up Current Source 0.6 1 μA DIM Pin Frequency Range MODE = REG 0.14 40 kHz MIN Comparator Hysteresis V MIN_HYS 55 mV MIN Pin PWM Mode Threshold VMIN_PWM Voltage on MIN pin at which VT changes from scaling LED current to pulsing LED current 2.2 2.3 2.4 V PWM Delay and Rise/Fall Time Delay from VT low to high (or high to low) to LED current low to high (or high to low), MIN = REG 20 μs THERMAL FOLDBACK (INTERNAL) Thermal Foldback Threshold TFB THRES 135 °C Thermal Shutdown Threshold TSD THRES 150 °C Thermal Shutdown Hysteresis TSD HYS 20 °C F A U L T D E T E C T I O N A FAULT E A Threshold VFAULT_TH Threshold for A FAULT E A comparator 1.14 1.2 1.26 V A FAULT E A Hysteresis VFAULT_HYS Hysteresis for A FAULT E A comparator 100 mV A FAULT E A Filter tFAULT VO_SNS and A FAULT E A shutdown noise filter 10 μs A FAULT E A Pull-Down Resistance A FAULT E A PD Fault activated 7 15 20 Ω VO_SNS Threshold VVO_SNS_TH Threshold for VO_SNS comparator 1.176 1.2 1.224 V Hysteresis V VO_SNS_HYS Hysteresis for VO_SNS comparator 50 mV Leakage Current IVO_SNS 50 nA Open SINKx Fault Threshold V SFD_OPEN SINKx pin voltage threshold to remove a sink from the feedback loop after a VOUT_OVP fault 80 mV
Rev. B | Page 5 of 23 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Channel Overvoltage Threshold VCH_OVP Threshold on SINKx to trigger CH_OVP fault 5.3 5.7 6.1 V Channel Overvoltage Hysteresis VCH_OVP_HYS Hysteresis after V CH_OVP is triggered 1.2 V Short SINKx Fault Threshold V SFD_SHORT SINKx pin voltage threshold to remove a sink from the feedback loop after a CH_OVP fault 525 mV
1 The maximum operating junction temperature (TJ(MAX)) supersedes the
Temperature Ranges section for more information. printed circuit board (PCB) with natural convection cooling. The LFCSP exposed pad must be soldered to GND. Table 3. Thermal Resistance
Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1 VIN Supply Voltage Input (3.0 V to 30 V). 2 REG Regulated 3.0 V (Typical) Source. Connect a 1.0 μF (or greater) capacitor from REG to ground.
5 A FAULT
A pins must be connected together. pin. The action of this pin depends on the MODE setting. strings, or connect it to ground to disable overvoltage sensing. 10 SINK4 Current Sink for LED Channel 4. 11 SINK3 Current Sink for LED Channel 3. 12 SINK2 Current Sink for LED Channel 2. 13 SINK1 Current Sink for LED Channel 1. PWM signal applied to VT pulses the LED current. EPAD (GND) Exposed Pad (Ground). Connect the exposed pad of the LFCSP to ground.
9 VO_SNS
14 DIM
13 SINK1
12 SINK2
11 SINK3
10 SINK4
16 MINVIN 1
- CONNECT THE EXPOSED PAD OF THE LFCSP TO GROUND.
event of an open connection on the EN pin. Figure 20. Detailed Block Diagram
Figure 21. Start-Up Timing and Signals Table 1. For additional information on the headroom voltage, combined to drive one string of LEDs at up to 2.0 A. A goes low and FB_OUT and COMP are disabled). Each current sink has a maximum rated voltage of 20 V . stage, the voltage is not present when off or during a fault. power supplies that produce over 100 V for their output. buffer. The MODE pin is used to select the power control mode.
pin voltage is 0 V . The MODE status cannot change after power-up. Table 5. Modes of Operation Programmed by the MODE Pin error amplifier connects to the FB_OUT inverting buffer. ADIsimPE, is available at: www.analog.com/ADIsimPE. Figure 22. Error Amplifier Power Control
Figure 27. Fault Flowchart can quickly lead to a case where the output voltage is too high. is detected by the VO_SNS pin and the SINKx pins. 1.2 V , an output overvoltage fault (VOUT_OVP) is declared.
1.15 V (typical), the FB_OUT function resumes its normal
resumes its normal operation.
protect the LEDs and power stage. dissipation persists, the sequence repeats. driven at 1 A each, or two strings can be driven at 2 A each. Figure 28. Multiple ADP8140 ICs Powered from One Supply (Low Gain Buffer Control Shown)
Figure 31. Total Power Dissipation (All Four Strings) for a Normal (before entering thermal foldback). BOARD = 105°C, the maximum board temperature. ground trace on the opposite side of the board. VIN capacitor is not as important. Place the VO_SNS resistors (if used) close to the IC. noise on these dimming signals. sinks that control the COMP and FB_OUT voltage. up to 500 mA of LED current. control the power regulation (COMP and FB_OUT). four of the sinks can be driven to 500 mA in any configuration. to drive two strings at 1 A each).
Figure 36. Multiple ADP8140 ICs with One Power Stage
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP] 2 ADP8140ACPZ-1-R7: SINK4 function is normal. 3 ADP8140ACPZ-2-R7: SINK4 regulates current but does not control FB_OUT and COMP. TOJEDEC STANDARDS MO-229-WGGE.
0.40 BSC
0.05 MAX
0.02 NOM
0.203 REF
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