ADP7156 AD | Alldatasheet
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1.2 A, Ultralow Noise,
High PSRR, RF Linear Regulator Data Sheet ADP7156 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Input voltage range: 2.3 V to 5.5 V 16 standard voltages between 1.2 V and 3.3 V available Maximum load current: 1.2 A Low noise 0.9 μV rms total integrated noise from 100 Hz to 100 kHz 1.6 μV rms total integrated noise from 10 Hz to 100 kHz Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz Power supply rejection ratio (PSRR) 80 dB from 1 kHz to 100 kHz; 60 dB at 1 MHz, V OUT = 3.3 V, VIN = 4.0 V Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V Initial accuracy: ±0.6% at ILOAD = 10 mA Initial accuracy over line, load, and temperature: ±1.5% Quiescent current: I GND = 4.0 mA at no load, 7 mA at 1.2 A Low shutdown current: 0.2 μA Stable with a 10 μF ceramic output capacitor 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages Precision enable Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs Communications and infrastructure Backhaul and microwave links GENERAL DESCRIPTION The ADP7156 is a linear regulator that operates from 2.3 V to 5.5 V and provides up to 1.2 A of output current. Using an advanced proprietary architecture, it provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a 10 μF ceramic output capacitor. There are 16 standard output voltages for the ADP7156. The following voltages are available from stock: 1.2 V , 1.8 V , 2.0 V , 3.1 V , and 3.2 V . The ADP7156 regulator typical output noise is 0.9 μV rms from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density from 10 kHz to 1 MHz. The ADP7156 is available in a 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages, making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 1.2 A of output current in a small, low profile footprint. TYPICAL APPLICATION CIRCUIT GND (EPAD) EN REF VIN VOUT ADP7156 ON OFF VIN = 3.8V VOUT = 3.3V VOUT_SENSE CIN 10µF COUT 10µF BYP VREG CBYP 1µF CREG 1µF REF_SENSE CREF 1µF 12937-001 Figure 1. Table 1. Related Devices
1 Package
4.5 V to 16 V 800 mA Fixed/
Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V
ADP7156* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts View a parametric search of comparable parts Evaluation Kits
- ADP7156 Evaluation Board Documentation Data Sheet
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- UG-809: Evaluating the ADP7156 Ultralow Noise, 1.2 A, Fixed Output, RF Linear Regulator Tools and Simulations
- ADI Linear Regulator Design Tool and Parametric Search
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Rev. A | Page 2 of 22 TABLE OF CONTENTS Input and Output Capacitors, Recommended Specifications 4
REVISION HISTORY
5/2016—Rev. 0 to Rev. A Changes to Current-Limit and Thermal Shutdown Section .... 17 3/2016—Revision 0: Initial Version
Rev. A | Page 3 of 22 SPECIFICATIONS VIN = VOUT + 0.5 V or 2.3 V , whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF; TA = 25°C for typical specifications; TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN 2.3 5.5 V LOAD CURRENT ILOAD 1.2 A OPERATING SUPPLY CURRENT IGND ILOAD = 0 µA 4.0 8.0 mA ILOAD = 1.2 A 7.0 12.0 mA SHUTDOWN CURRENT IIN_SD EN = GND 0.2 4 µA NOISE1 VOUT = 1.2 V to 3.3 V Output Noise OUTNOISE 10 Hz to 100 kHz 1.6 µV rms 100 Hz to 100 kHz 0.9 µV rms Noise Spectral Density OUTNSD 10 kHz to 1 MHz 1.7 nV/√Hz POWER SUPPLY REJECTION RATIO1 PSRR 1 kHz to 100 kHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 1.2 A 80 dB 1 MHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 1.2 A 60 dB 1 kHz to 100 kHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 1.2 A 80 dB 1 MHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 1.2 A 60 dB OUTPUT VOLTAGE ACCURACY Output Voltage2 VOUT 1.2 3.3 V Initial Accuracy ILOAD = 10 mA, TA = 25°C −0.6 +0.6 % 10 mA < ILOAD < 1.2 A, TA= 25°C −1.0 +1.0 % 10 mA < ILOAD < 1.2 A, TA = −40°C to +125°C −1.5 +1.5 % REGULATION Line ∆VOUT/∆VIN VIN = VOUT + 0.5 V or 2.3 V, whichever is greater to 5.5 V −0.1 +0.1 %/V Load3 ∆VOUT/∆IOUT IOUT = 10 mA to 1.2 A 0.3 %/A CURRENT-LIMIT THRESHOLD4 ILIMIT REF 22 mA VOUT 1.4 1.8 2.4 A DROPOUT VOL TAGE5 VDROPOUT IOUT = 600 mA, VOUT = 3.3 V 60 80 mV IOUT = 1.2 A, VOUT = 3.3 V 120 170 mV PULL-DOWN RESISTANCE EN = 0 V, VIN = 5.5 V VOUT VOUT_PULL VOUT = 1 V 650 Ω VREG VREG_PULL VREG = 1 V 31 kΩ REF VREF_PULL VREF = 1 V 850 Ω BYP VBYP_PULL VBYP = 1 V 650 Ω START-UP TIME1, 6 VOUT = 3.3 V VOUT tSTART-UP 1.2 ms VREG tREG_START-UP 0.6 ms REF tREF_START-UP 0.5 ms THERMAL SHUTDOWN1 Threshold TSSD TJ rising 150 °C Hysteresis TSSD_HYS 15 °C UNDERVOLTAGE THRESHOLDS Input Voltage Rising UVLORISE 2.22 2.29 V Falling UVLOFAL L 1.95 2.02 V Hysteresis UVLOHYS 200 mV
Rev. A | Page 4 of 22 Parameter Symbol Test Conditions/Comments Min Typ Max Unit VREG UVLO THRESHOLDS7 Rising VREGUVLORISE 1.94 V Falling VREGUVLOFAL L 1.60 V Hysteresis VREGUVLOHYS 185 mV EN INPUT PRECISION 2.3 V ≤ VIN ≤ 5.5 V EN Input Logic High VEN_HIGH 1.13 1.22 1.31 V Logic Low VEN_LOW 1.05 1.13 1.22 V Logic Hysteresis VEN_HYS 90 mV LEAKAGE CURRENT REF_SENSE IREF_SENSE_LKG 10 nA EN IEN_LKG EN = VIN or GND 0.01 1 µA 1 Guaranteed by characterization; not production tested. 3.2 V, and 3.3 V. 3 Based on an endpoint calculation using 10 mA and 1.2 A loads. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 5 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout voltage applies only for output voltages greater than 2.3 V. 6 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value. 7 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed. INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit MINIMUM CAPACITANCE TA = −40°C to +125°C Input1 CIN 10.0 µF Regulator CREG 1.0 µF Output1 COUT 10.0 µF Bypass CBYP 1.0 µF Reference CREF 1.0 µF CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR) TA = −40°C to +125°C COUT, CIN RESR 0.001 0.1 Ω CREG, CREF RESR 0.001 0.2 Ω CBYP RESR 0.001 2.0 Ω 1 The minimum input and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any low dropout regulator.
Table 5. Thermal Resistance
- THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
10 VIN
9 VIN
8 VREG
7 REF
6 REF_SENSE
Figure 3. 10-Lead LFCSP Pin Configuration
- THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
Figure 4. 8-Lead SOIC Pin Configuration Table 6. Pin Function Descriptions 1, 2 1 VOUT Regulated Output Voltage. Bypass VOUT to ground with a 10 µF or greater capacitor. VOUT_SENSE as close to the load as possible. 4 3 BYP Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to ground to reduce noise. Do not connect a load to this pin. 6 5 REF_SENSE Reference Sense. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or GND. REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin. 9, 10 8 VIN Regulator Input Supply Voltage. Bypass VIN to ground with a 10 µF or greater capacitor. enhances thermal performance, and it is electrically connected to ground inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation.
Figure 29. RMS Output Noise vs. Output Voltage Figure 30. Noise Spectral Density vs. Frequency at Various Values of CBYP Figure 31. Output Noise Spectral Density vs. Frequency at Various Loads,
0.1 Hz to 1 MHz
Figure 32. Output Noise Spectral Density vs. Frequency at Various Loads,
10 Hz to 10 MHz
Figure 33. Load Transient Response, ILOAD = 100 mA to 1.2 A, Figure 34. Load Transient Response, ILOAD = 100 mA to 1.2 A,
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
0.20 MIN
Figure 64. 10-Lead Lead Frame Chip Scale Package [LFCSP]
0.10 MAX
0.05 NOM
3.81 REF
1.04 REF
1.27 BSC
Figure 65. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Rev. A | Page 22 of 22 ORDERING GUIDE Model1, 2 Temperature Range Output Voltage (V) Package Description Package Option Branding ADP7156ACPZ-1.2-R7 −40°C to +125°C 1.2 10-Lead LFCSP CP-10-9 LST ADP7156ACPZ-1.8-R7 −40°C to +125°C 1.8 10-Lead LFCSP CP-10-9 LSU ADP7156ACPZ-2.0-R7 −40°C to +125°C 2.0 10-Lead LFCSP CP-10-9 LTQ ADP7156ACPZ-2.5-R7 −40°C to +125°C 2.5 10-Lead LFCSP CP-10-9 LSV ADP7156ACPZ-2.8-R7 −40°C to +125°C 2.8 10-Lead LFCSP CP-10-9 LSW ADP7156ACPZ-3.0-R7 −40°C to +125°C 3.0 10-Lead LFCSP CP-10-9 LSY ADP7156ACPZ-3.3-R7 −40°C to +125°C 3.3 10-Lead LFCSP CP-10-9 LSZ ADP7156ARDZ-1.2-R7 −40°C to +125°C 1.2 8-Lead SOIC_N_EP RD-8-1 ADP7156ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-1 ADP7156ARDZ-2.0-R7 −40°C to +125°C 2.0 8-Lead SOIC_N_EP RD-8-1 ADP7156ARDZ-2.5-R7 −40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-1 ADP7156ARDZ-2.8-R7 −40°C to +125°C 2.8 8-Lead SOIC_N_EP RD-8-1 ADP7156ARDZ-3.0-R7 −40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-1 ADP7156ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-1 ADP7156CP-3.3EVALZ Evaluation Board 1 Z = RoHS Compliant Part. representative. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12937-0-5/16(A)