ADP7112ACBZ-3.3-R7

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20 V, 200 mA, Low Noise,

Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2014–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Low noise: 11 μV rms independent of fixed output voltage PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, VOUT = 5 V, VIN = 7 V Input voltage range: 2.7 V to 20 V Maximum output current: 200 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature ±1.8%, T J = −40°C to +125°C Low dropout voltage: 200 mV (typical) at a 200 mA load, VOUT = 5 V User-programmable soft start Low quiescent current, I GND = 50 μA (typical) with no load Low shutdown current 1.8 μA at VIN = 5 V 3.0 μA at VIN = 20 V Stable with a small 2.2 μF ceramic output capacitor Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V 15 standard voltages between 1.2 V and 5.0 V are available Adjustable output from 1.2 V to VIN – VDO, output can be adjusted above initial set point Precision enable 1 mm × 1.2 mm, 6-ball WLCSP

APPLICATIONS

Regulation to noise sensitive applications ADC and DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation TYPICAL APPLICATION CIRCUITS GND EN SS VIN VOUT ADP7112 ON OFF VIN = 6V VOUT = 5V SENSE/ADJ CIN 2.2µF COUT 2.2µF CSS 1nF 12508-001 Figure 1. ADP7112 with Fixed Output Voltage, 5 V Figure 2. ADP7112 with 5 V Output Adjusted to 6 V the output voltage for the fixed options of 5 V or less. The ADP7112 is available in 15 fixed output voltage options. 1 mm × 1.2 mm WLCSP, making it a very compact solution.

Rev. D | Page 2 of 21 TABLE OF CONTENTS Input and Output Capacitance, Recommended Specifications

REVISION HISTORY

3/2020—Rev. C to Rev. D Change to Effect of Noise Reduction on Start-Up Time Section ... 16 7/2016—Rev. B to Rev. C Changes to Programmable Precision Enable Section and Soft Added Effect of Noise Reduction on Start-Up Time Section .. 16 12/2014—Rev. A to Rev. B Changed EN to GND Parameter from −0.3 V to VIN to −0.3 V 12/2014—Rev. 0 to Rev. A 9/2014—Revision 0: Initial Version

Rev. D | Page 3 of 21 SPECIFICATIONS VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, EN = VIN, IOUT = 10 mA, CIN = COUT = 2.2 μF, CSS = 0 pF, TA = 25°C for typical specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted. Table 1. Parameter Symbol Test Conditio ns/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN 2.7 20 V MAXIMUM OUTPUT CURRENT I LOAD_MAX 200 mA OPERATING SUPPLY CURRENT I GND I OUT = 0 μA 50 140 μA IOUT = 10 mA 80 190 μA IOUT = 200 mA 180 320 μA SHUTDOWN CURRENT IGND-SD EN = GND 1.8 μA EN = GND, VIN = 20 V 3.0 10 μA OUTPUT VOLTAGE ACCURACY Output Voltage Accuracy V OUT I OUT = 10 mA, TJ = 25°C –0.8 +0.8 % 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V –1.8 +1.8 % LINE REGULATION ∆VOUT/∆VIN V IN = (VOUT + 1 V) to 20 V –0.02 +0.02 %/V LOAD REGULATION1 ∆V OUT/∆IOUT I OUT = 100 μA to 200 mA 0.002 0.004 %/mA SENSE INPUT BIAS CURRENT SENSE I-BIAS 100 μA < I OUT < 200 mA VIN = (VOUT + 1 V) to 20 V 10 1000 nA DROPOUT VOLTAGE2 V DROPOUT I OUT = 10 mA 30 60 mV IOUT = 200 mA 200 420 mV START-UP TIME3 T START-UP V OUT = 5 V 380 μs SOFT START SOURCE CURRENT SS I-SOURCE SS = GND 1.15 μA CURRENT-LIMIT THRESHOLD4 I LIMIT 250 360 460 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TS SD T J rising 150 °C Thermal Shutdown Hysteresis TS SD-HYS 15 °C UNDERVOLTAGE THRESHOLDS Input Voltage Rising UVLO RISE 2.69 V Input Voltage Falling UVLO FALL 2.2 V Hysteresis UVLO HYS 230 mV EN INPUT STANDBY 2.7 V ≤ VIN ≤ 20 V EN Input Logic High ENSTBY-HIGH 1.0 V EN Input Logic Low ENSTBY-LOW 0.4 V EN Input Logic Hysteresis EN STBY-HYS 150 mV EN INPUT PRECISION 2.7 V ≤ VIN ≤ 20 V EN Input Logic High ENHIGH 1.15 1.22 1.30 V EN Input Logic Low ENLOW 1.06 1.12 1.18 V EN Input Logic Hysteresis EN HYS 100 mV EN Input Leakage Current I EN-LKG EN = V IN or GND 0.04 1 μA EN Input Delay Time tEN-DLY From EN rising from 0 V to V IN to 0.1 × VOUT 80 μs OUTPUT NOISE OUT NOISE 10 Hz to 100 kHz, all output voltage options 11 μV rms POWER SUPPLY REJECTION RATIO PSRR 1 MHz, V IN = 7 V, VOUT = 5 V 50 dB 100 kHz, VIN = 7 V, VOUT = 5 V 68 dB 10 kHz, VIN = 7 V, VOUT = 5 V 88 dB 1 Based on an endpoint calculation using 100 μA and 200 mA loads. See Figure 5 for typical load regulation performance for loads less than 1 mA. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages greater than 2.7 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V.

Rev. D | Page 4 of 21 INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditio ns/Comments Min Typ Max Unit INPUT AND OUTPUT CAPACITANCE Minimum Capacitance1 C MIN T A = −40°C to +125°C 1.5 μF Capacitor Effective Series Resistance (ESR) RESR T A = −40°C to +125°C 0.001 0.3 Ω 1 The minimum input and output capacitance must be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with any LDO.

operational section of this specification is not implied. extended periods may affect product reliability. junction-to-ambient thermal resistance of the package (θJA). JESD51-9 for detailed information on the board construction. Table 4. Thermal Resistance

Figure 3. Pin Configuration Table 5. Pin Function Descriptions A1 VIN Regulator Input Supply. Bypass VIN to GND with a 2.2 μF or greater capacitor. for a typical 380 μs start-up time. Do not ground this pin. to turn off the regulator. For automatic startup, connect EN to VIN. A2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 2.2 μF or greater capacitor. B2 SENSE/ADJ Sense Input (SENSE). Connect to load. voltage higher than 1.2 V by connecting an external resistor divider to the ADJ pin.

set to a 6 V output according to Equation 3 (see Figure 2). the output voltage noise is proportional to the output voltage. to the target voltage to minimize the increase in output noise. the error amplifier. RNR is chosen to be small with respect to R2. slightly greater than unity gain. Figure 48. Noise Reduction Modification where RPAR is a parallel combination of R1 and RNR. is restored to the operating value. junction temperature does not exceed 125°C. where power supply sequencing is critical. as shown in Figure 48, the start-up time is approximately 0.6 sec. length of the start-up time instead of the soft start capacitor.

the amount of copper attached to the pins of the ADP7112. does not yield significant heat dissipation benefits. boards where area is limited. Figure 53. Example WLCSP PCB Layout

Table 7. Recommended LDOs for Super Low Noise Operation

10 Hz to

1 MHz

Table 8. Related Devices

0.40 BSC

Figure 54. 6-Ball Wafer Level Chip Scale Package [WLCSP] 2 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 3 The evaluation boards are preconfigured with an adjustable ADP7112. registered trademarks are the prop erty of their respective owners.