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20 V, 500 mA, Low Noise LDO Regulator
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Input voltage range: 3.3 V to 20 V Maximum output current: 500 mA Low noise: 15 µV rms for fixed output versions PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 350 mV at 500 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature: −2% to +1% Low quiescent current: 900 μA at VIN = 10 V, IOUT = 500 mA Low shutdown current: <50 µA at VIN = 12 V, stable with small 1 µF ceramic output capacitor 3 fixed output voltage options: 1.8, 3.3 V and 5 V Adjustable output from 1.22 V to 19 V Programmable soft start for inrush current control Foldback current-limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages
APPLICATIONS
Regulation of noise sensitive applications: ADC and DAC circuits, precision amplifiers, high frequency oscillators, clocks, and PLLs Communications and infrastructure Medical and healthcare Industrial and instrumentation TYPICAL APPLICATION CIRCUITS Figure 1. ADP7105 with Fixed Output Voltage, 5 V Figure 2. ADP7105 with Adjustable Output Voltage, 5 V function facilitates sequencing of multiple power supplies. small, low profile footprint.
Rev. 0 | Page 2 of 28 TABLE OF CONTENTS Input and Output Capacitor, Recommended Specifications .. 4
REVISION HISTORY
7/13—Revision 0: Initial Version
Rev. 0 | Page 3 of 28 SPECIFICATIONS VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN 3.3 20 V OPERATING SUPPLY CURRENT IGND IOUT = 100 µA, VIN = 10 V 400 µA IOUT = 100 µA, VIN = 10 V, TJ = −40°C to +125°C 900 µA IOUT = 10 mA, VIN = 10 V 450 µA IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 1050 µA IOUT = 300 mA, VIN = 10 V 750 µA IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 1400 µA IOUT = 500 mA, VIN = 10 V 900 µA IOUT = 500 mA, VIN = 10 V, TJ = −40°C to +125°C 1600 µA SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 12 V 40 50 µA EN = GND, VIN = 12 V, TJ = −40°C to +125°C 75 µA INPUT REVERSE CURRENT IREV-INPUT EN = GND, VIN = 0 V, VOUT = 20 V 0.3 µA EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to +125°C 5 µA OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy VOUT IOUT = 10 mA −0.8 +0.8 % 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −2 +1 % Adjustable Output Voltage Accuracy VADJ IOUT = 10 mA 1.21 1.22 1.23 V 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 1.196 1.232 V LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −0.015 +0.015 %/V LOAD REGULATION1 ∆VOUT/∆IOUT 1 mA < IOUT < 500 mA 0.2 %/A 1 mA < IOUT < 500 mA, TJ = −40°C to +125°C 0.75 %/A ADJ INPUT BIAS CURRENT2 ADJI-BIAS 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V, ADJ connected to VOUT 10 nA SENSE INPUT BIAS CURRENT2 SENSEI-BIAS 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V, SENSE connected to VOUT, VOUT = 1.5 V 1 μA DROPOUT VOL TAGE3 VDROPOUT IOUT = 10 mA 20 mV IOUT = 10 mA, TJ = −40°C to +125°C 40 mV IOUT = 150 mA 100 mV IOUT = 150 mA, TJ = −40°C to +125°C 175 mV IOUT = 300 mA 200 mV IOUT = 300 mA, TJ = −40°C to +125°C 325 mV IOUT = 500 mA 350 mV IOUT = 500 mA, TJ = −40°C to +125°C 550 mV START-UP TIME4 tSTART-UP CSS = 0 nF, IOUT = 10 mA 625 µs CSS = 10 nF, IOUT = 10 mA 11.5 ms CURRENT-LIMIT THRESHOLD5 ILIMIT 625 775 1000 mA PG OUTPUT LOGIC LEVEL PG Output Logic High PGHIGH IOH < 1 µA 1.0 V PG Output Logic Low PGLOW IOL < 2 mA 0.4 V PG OUTPUT THRESHOLD Output Voltage Falling PGFAL L −9.2 % Output Voltage Rising PGRISE −6.5 % THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C
Rev. 0 | Page 4 of 28 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SOFT START SOURCE CURRENT SSI-SOURCE SS = GND 1 µA PROGRAMMABLE EN/UVLO UVLO Threshold Rising UVLORISE 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 1.18 1.23 1.28 V UVLO Threshold Falling UVLOFAL L 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in series with the enable input pin 1.13 V UVLO Hysteresis Current UVLOHYS VEN > 1.25 V, TJ = −40°C to +125°C 7.5 9.8 12 µA Enable Pull-Down Current IEN-IN EN = VIN 500 nA Start Threshold VSTART TJ = −40°C to +125°C 3.2 V Shutdown Threshold VSHUTDOWN TJ = −40°C to +125°C 2.45 V Hysteresis 250 mV OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 15 µV rms 10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V 15 µV rms
10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 15 µV rms
10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V 15 µV rms
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V, adjustable mode 18 µV rms
10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V, adjustable
30 µV rms
10 Hz to 100 kHz, VIN = 20 V, VOUT = 15 V,
65 µV rms POWER SUPPLY REJECTION RATIO PSRR 100 kHz, VIN = 4.3 V, VOUT = 3.3 V 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V 50 dB 10 kHz, VIN = 4.3 V, VOUT = 3.3 V 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V 60 dB 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 60 dB 100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 60 dB 10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 80 dB 10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 80 dB 1 Based on an endpoint calculation using 1 mA and 500 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. 2 The adjust input function (ADJ) of the SENSE/ADJ pin applies to adjustable output voltage models only; whereas the sense function (SENSE) applies to fixed output voltage models only. 3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This specification applies only for output voltages greater than 3.0 V. 4 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 5 Current-limit threshold is defined as the current at which the output voltage falls to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to fall to 90% of 5.0 V, or 4.5 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit Minimum Input and Output Capacitance1 CMIN TA = −40°C to +125°C 0.7 µF Capacitor ESR RESR TA = −40°C to +125°C 0.001 0.2 Ω 1 Ensure that the minimum input and output capacitance is greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO regulator.
maximum ambient temperature may need to be derated. thermal resistance of the package (θJA). (LFCSP), available at www.analog.com. device soldered in a circuit board for surface-mount packages. mounted heat sinks. θJC is presented here for reference only. Table 4. Thermal Resistance
Figure 3. Pin Configuration, LFCSP Package Figure 4. Pin Configuration, Narrow-Body SOIC Package Table 5. Pin Function Descriptions 1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor. between the regulator output and the load. This function applies to fixed voltage models only. adjustable voltage models only. 4 SS Soft Start. A capacitor connected to this pin determines the soft start time. 5 EN/UVLO Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. the upper and lower thresholds are determined by the programming resistors. not used, the pin can be left open or connected to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor. exposed pad be connected to the ground plane on the board.
- IT IS HIGHLY RECOMMENDED THAT THE
6 GND
5 EN/UVLO
8 VIN
- IT IS HIGHLY RECOMMENDED THAT THE
Figure 59. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
generation inside the LDO regulator. restored to its operating value. 0 mA that continues as long as the short remains at the output. limited so that the junction temperature does not exceed 125°C. die to exceed the maximum junction temperature of 125°C. copper used to solder the package GND pins to the PCB. Table 6. Typical θJA Values 1 Device soldered to minimum size pin traces. Table 7. Typical ΨJB Values with PCB Area
1 Note that the ΨJB value for the LFCSP package accounts for PCB area, which
TA is the ambient temperature. θJA is the junction-to-ambient thermal resistance. VIN and VOUT are the input and output voltages, respectively.
Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
0.05 MAX
0.02 NOM
0.80 MAX
0.20 MIN
0.10 MAX
0.05 NOM
3.81 REF
1.04 REF
1.27 BSC
Rev. 0 | Page 26 of 28 ORDERING GUIDE Model1 Temperature Range Output Voltage (V) Package
Description
ADP7105ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-5 LNS ADP7105ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-5 LNT ADP7105ACPZ-5.0-R7 −40°C to +125°C 5 8-Lead LFCSP_WD CP-8-5 LNU ADP7105ACPZ-R2 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LNV ADP7105ACPZ-R7 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LNV ADP7105ARDZ-1.8 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-3.3 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-5.0 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-5.0-R7 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-R7 −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2 1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28 NOTES
Rev. 0 | Page 28 of 28 NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11641-0-7/13(0)