ADP7102

ADP7102 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

20 V, 300 mA, Low Noise, CMOS LDO

Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Input voltage range: 3.3 V to 20 V Maximum output current: 300 mA Low noise: 15 μV rms for fixed output versions PSRR performance of 60 dB at 10 kHz, V OUT = 3.3 V Reverse current protection Low dropout voltage: 200 mV at 300 mA load Initial accuracy: ±0.8% Accuracy over line, load, and temperature: −2%, +1% Low quiescent current (V IN = 5 V), IGND = 750 μA with 300 mA load Low shutdown current: 40 μA at VIN = 12 V Stable with small 1 μF ceramic output capacitor 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,

5 V, and 9 V

Adjustable output from 1.22 V to V IN − VDO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages

APPLICATIONS

Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation TYPICAL APPLICATION CIRCUITS VOUT = 5VVIN = 8V PG VOUTVIN PG GND SENSE EN/ UVLO RPG 100kΩ 100kΩ 100kΩ COUT 1µF CIN 1µF ON OFF 09506-001 Figure 1. ADP7102 with Fixed Output Voltage, 5 V Figure 2. ADP7102 with Adjustable Output Voltage, 5 V IN − VDO via an external feedback divider. function facilitates sequencing of multiple power supplies.

Rev. E | Page 2 of 28 TABLE OF CONTENTS Input and Output Capacitor, Recommended Specifications .. 4

REVISION HISTORY

9/15—Rev. D to Rev. E 5/14—Rev. C to Rev. D Changed UVLO Threshold Rising Typ Parameter from 1.23 V 8/13—Rev. B to Rev. C 2/13—Rev. A to Rev. B Changes to Noise Reduction of the Adjustable ADP7102 11/11—Rev. 0 to Rev. A 10/11—Revision 0: Initial Version

Rev. E | Page 3 of 28 SPECIFICATIONS VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V IN 3.3 20 V OPERATING SUPPLY CURRENT I GND I OUT = 100 μA, VIN = 10 V 400 μA IOUT = 100 μA, VIN = 10 V, TJ = −40°C to +125°C 900 μA IOUT = 10 mA, VIN = 10 V 450 μA IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 1050 μA IOUT = 150 mA, VIN = 10 V 650 μA IOUT = 150 mA, VIN = 10 V, TJ = −40°C to +125°C 1250 μA IOUT = 300 mA, VIN = 10 V 750 μA IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 1400 μA SHUTDOWN CURRENT I GND-SD EN = GND, V IN = 12 V 40 μA EN = GND, VIN = 12 V, TJ = −40°C to +125°C 75 μA INPUT REVERSE CURRENT I REV-INPUT EN = GND, V IN = 0 V, VOUT = 20 V 0.3 μA EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to +125°C 5 μA OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy VOUT I OUT = 10 mA −0.8 +0.8 % 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −2 +1 % Adjustable Output Voltage Accuracy VADJ I OUT = 10 mA 1.21 1.22 1.23 V 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 1.196 1.232 V LINE REGULATION ∆VOUT/∆VIN V IN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −0.015 +0.015 %/V LOAD REGULATION1 ∆V OUT/∆IOUT I OUT = 1 mA to 300 mA 0.2 %/A IOUT = 1 mA to 300 mA, TJ = −40°C to +125°C 1.0 %/A ADJ INPUT BIAS CURRENT ADJ I-BIAS 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, ADJ connected to VOUT 10 nA SENSE INPUT BIAS CURRENT SENSE I-BIAS 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, SENSE connected to VOUT, VOUT = 1.5 V 1 μA DROPOUT VOLTAGE2 V DROPOUT I OUT = 10 mA 20 mV IOUT = 10 mA, TJ = −40°C to +125°C 40 mV IOUT = 150 mA 100 mV IOUT = 150 mA, TJ = −40°C to +125°C 175 mV IOUT = 300 mA 200 mV IOUT = 300 mA, TJ = −40°C to +125°C 325 mV START-UP TIME3 t START-UP V OUT = 5 V 800 μs CURRENT-LIMIT THRESHOLD4 I LIMIT 450 575 750 mA PG OUTPUT LOGIC LEVEL PG Output Logic High PG HIGH I OH < 1 μA 1.0 V PG Output Logic Low PG LOW I OL < 2 mA 0.4 V PG OUTPUT THRESHOLD Output Voltage Falling PG FALL −9.2 % Output Voltage Rising PG RISE −6.5 %

Rev. E | Page 4 of 28 Parameter Symbol Test Conditions/Comments Min Typ Max Unit THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD T J rising 150 C Thermal Shutdown Hysteresis TSSD-HYS 15 C PROGRAMMABLE EN/UVLO UVLO Threshold rising UVLO RISE 3.3 V ≤ V IN ≤ 20 V, T J = −40°C to +125°C 1.18 1.22 1.28 V UVLO Threshold falling UVLO FALL 3.3 V ≤ V IN ≤ 20 V, T J = −40°C to +125°C, 10 kΩ in series with enable pin 1.13 V UVLO Hysteresis Current UVLO HYS V EN > 1.25 V, TJ = −40°C to +125°C 7.5 9.8 12 μA Enable Pulldown Current I EN-IN EN = V IN 500 nA INPUT VOLTAGE Start Threshold VSTART T J = −40°C to +125°C 3.2 V Shutdown Threshold V SHUTDOWN T J = −40°C to +125°C 2.45 V Hysteresis 250 mV OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, V IN = 5.5 V, VOUT = 1.8 V 15 μV rms 10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V 15 μV rms

10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 15 μV rms

10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V 15 μV rms

10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V, adjustable mode 18 μV rms

10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V,

30 μV rms

10 Hz to 100 kHz, VIN = 18 V, VOUT = 15 V,

65 μV rms POWER SUPPLY REJECTION RATIO PSRR 100 kHz, V IN = 4.3 V, VOUT = 3.3 V 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V 50 dB 10 kHz, VIN = 4.3 V, VOUT = 3.3 V 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V 60 dB 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 60 dB 100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 60 dB 10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 80 dB 10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 80 dB 1 Based on an end point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. 2 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 3.0 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit Minimum Input and Output Capacitance1 C MIN T A = −40°C to +125°C 0.7 μF Capacitor ESR RESR T A = −40°C to +125°C 0.001 0.2 Ω 1 The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.

the application and board layout. device soldered in a circuit board for surface-mount packages. heat sinks. θJC is presented here for reference only. Table 4. Thermal Resistance

1. NC = NO CONNECT. DO NOT CONNECT TO
2. IT IS HIGHLY RECOMMENDED THAT THE

5 EN/UVLO

Figure 3. LFCSP Package

1. NC = NO CONNECT. DO NOT CONNECT TO
2. IT IS HIGHLY RECOMMENDED THAT THE

Figure 4. Narrow Body SOIC Package Table 5. Pin Function Descriptions 1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor. 2 SENSE/ADJ Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier. regulator output and the load. This function applies to fixed voltages only. 4 NC Do Not Connect to this Pin. 5 EN/UVLO Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. the upper and lower thresholds are determined by the programming resistors. may be left open or connected to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor. that the EPAD be connected to the ground plane on the board.

in series with the EN/ UVLO pin. Figure 65. Typical VOUT Response to EN Pin Operation resistors program the minimum operational voltage for the LDO. VIN is the desired turn on voltage. VHYS is the desired EN/UVLO hysteresis level. enable threshold is 2.44 V with a hysteresis of 1 V . Figure 66. Typical EN Pin Voltage Divider Figure 65 shows the typical hysteresis of the EN/UVLO pin. on the EN pin as it passes through the threshold points.

3.3 V option is approximately 580 μs from the time the EN active

Figure 67. Typical Start-Up Behavior

restored to its operating value. continues as long as the short remains at the output. so the junction temperature does not exceed 125°C. junction temperature of 125°C. of copper used to solder the package GND pins to the PCB. the typical ΨJB values of the 8-lead SOIC and 8-lead LFCSP . Table 6. Typical θJA Values 1 Device soldered to minimum size pin traces. Table 7. Typical ΨJB Values TA is the ambient temperature. VIN and VOUT are input and output voltages, respectively. ambient temperatures, power dissipation, and areas of PCB copper.

0.05 MAX

0.02 NOM

0.80 MAX

0.20 MIN

Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

0.10 MAX

0.05 NOM

3.81 REF

1.04 REF

1.27 BSC

Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Rev. E | Page 26 of 28 ORDERING GUIDE Model1 Temperature Range Output Voltage (V) 2, 3 Package

Description

ADP7102ACPZ-R7 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LHO ADP7102ACPZ-1.5-R7 −40°C to +125°C 1.5 8-Lead LFCSP_WD CP-8-5 LJV ADP7102ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-5 LJW ADP7102ACPZ-2.5-R7 −40°C to +125°C 2.5 8-Lead LFCSP_WD CP-8-5 LJZ ADP7102ACPZ-3.0-R7 −40°C to +125°C 3.0 8-Lead LFCSP_WD CP-8-5 LKO ADP7102ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-5 LK1 ADP7102ACPZ-5.0-R7 −40°C to +125°C 5 8-Lead LFCSP_WD CP-8-5 LK2 ADP7102ACPZ-9.0-R7 −40°C to +125°C 9 8-Lead LFCSP_WD CP-8-5 LLC ADP7102ARDZ-R7 −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-1.5-R7 −40°C to +125°C 1.5 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-2.5-R7 −40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-3.0-R7 −40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-5.0-R7 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-9.0-R7 −40°C to +125°C 9 8-Lead SOIC_N_EP RD-8-2 ADP7102CP-EVALZ 3.3 LFCSP Evaluation Board ADP7102RD-EVALZ 3.3 SOIC Evaluation Board ADP7102CPZ-REDYKIT LFCSP REDYKIT ADP7102RDZ-REDYKIT SOIC REDYKIT 1 Z = RoHS Compliant Part. 2 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 3 The ADP7102CP-EVALZ and ADP7102RD-EVALZ evaluation boards are preconfigured with a 3.3 V ADP7102

Rev. E | Page 27 of 28 NOTES

Rev. E | Page 28 of 28 NOTES ©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D09506-0-9/15(E)