ADP5300 (Rev. B)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 21
Technical content
50 mA/500 mA, High Efficiency, Ultralow Power Step-Down Regulator Data Sheet ADP5300 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Input supply voltage range: 2.15 V to 6.50 V Operates down to 2.00 V voltage Ultralow 180 nA quiescent current Selectable output voltage of 0.8 V to 5.0 V ±1.5% output accuracy over full temperature range in PWM mode Selectable hysteresis mode or PWM operation mode Output current Up to 50 mA in hysteresis mode Up to 500 mA in PWM mode VOUTOK flag monitors the output voltage Ultrafast stop switching control 100% duty cycle operation mode
2.0 MHz typical switching frequency in PWM mode with
optional SYNC clock range from 1.5 MHz to 2.5 MHz Quick output discharge (QOD) option UVLO, OCP , and TSD protection 10-lead, 3 mm × 3 mm LFCSP −40°C to +125°C operating temperature range
APPLICATIONS
Energy (gas and water) metering Portable and battery-powered equipment Medical applications Keep-alive power supplies TYPICAL APPLICATION CIRCUIT 2.2µH SW PGND FB 10µF 10µF VOUT PVIN VID VIN = 2.15 TO 6.50V ADP5300 VID0: 1.2V VID1: 1.5V VID2: 1.8V VID3: 2.0V VID4: 2.1V VID5: 2.2V VID6: 2.3V VID7: 2.4V VID8: 2.5V VID9: 2.6V VID10: 2.7V VID11: 2.8V VID12: 2.9V VID13: 3.0V VID14: 3.3V VID15: 3.6V EPAD ENOFF ON PWM SYNC/MODEHYS STOP STOPSW VOUTOK AGND 13366-001 Figure 1. GENERAL DESCRIPTION The ADP5300 is a high efficiency, ultralow quiescent current step-down regulator that draws only 180 nA quiescent current to regulate the output. The ADP5300 runs from an input supply voltage range of 2.15 V to 6.50 V , allowing the use of multiple alkaline or NiMH, Li-Ion cells, or other power sources. The output voltage is selectable from 0.8 V to 5.0 V by an external VID resistor and factory fuse. The total solution requires only four tiny external components. The ADP5300 can operate between hysteresis mode and pulse- width modulation (PWM) mode via the SYNC/MODE pin. The regulator in hysteresis mode achieves excellent efficiency at a power of less than 1 mW and provides up to 50 mA of output current. The regulator in PWM mode produces a lower output ripple and supplies up to 500 mA of output current. The flexible configuration capability during operation of the device enables very efficient power management to meet both the longest battery life and low system noise requirements. The ADP5300 contains a VOUTOK flag, which monitors the output voltage and runs at a 2 MHz switching frequency in PWM mode. SYNC/MODE can be synchronized to an external clock from 1.5 MHz to 2.5 MHz. The ADP5300 includes an STOP pin that can disable the regulator switching temporarily, in this way a quiet system environment can be achieved to benefit noise sensitive circuitry, such as data conversion, RF data transmission, and analog sensing. Other key features in the ADP5300 include separate enabling, QOD, and safety features such as overcurrent protection (OCP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5300 is available in a 10-lead, 3 mm × 3 mm LFCSP rated for a −40°C to +125°C operating temperature range. Multifunction pin names may be referenced by their relevant function only.
Rev. B | Page 2 of 21 TABLE OF CONTENTS
REVISION HISTORY
11/2017—Rev A. to Rev. B 6/2016—Rev. 0 to Rev. A 8/2015—Revision 0: Initial Version
Rev. B | Page 3 of 21 DETAILED FUNCTIONAL BLOCK DIAGRAM VOUTOK MODE INTERNAL FEEDBACK RESISTOR DIVIDER SOFT START 90% 87% FB CONTROL LOGIC ILIM_PWM ILIM_HYS STANDBY 0.808V –0.6A (PWM) 0.8VV TO I 0A (HYS) 0.8V PWM DRIVER PVIN PVIN SW PGND FB 1.2V 0.4V SYNC MODE 1.2V 0.4V PVIN UVLO BAND GAP BIAS AND HOUSEKEEPING KEEP ALIVE BLOCK 2.06V 2.00V STOP EN SYNC/ MODE DRIVER PVIN Σ VID AGND 2MHz OSC SLOPE COMPENSATION 0.4V 1.2V FORCE SLEEP 13366-002 Figure 2.
Rev. B | Page 4 of 21 SPECIFICATIONS VIN = 3.6 V, VOUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE RANGE VIN 2.15 6.50 V SHUTDOWN CURRENT ISHUTDOWN 18 40 nA VEN = 0 V, −40°C ≤ TJ ≤ +85°C 18 130 nA VEN = 0 V, −40°C ≤ TJ ≤ +125°C QUIESCENT CURRENT Operating Quiescent Current in Hysteresis Mode IQ_HYS 180 260 nA −40°C ≤ TJ ≤ +85°C 180 350 nA −40°C ≤ TJ ≤ +125°C 570 1400 nA 100% duty cycle operation, VIN = 3.0 V, VOUT set to 3.3 V Operating Quiescent Current in Hysteresis Mode IQ-HYS2 2.3 3.2 µA VIN = 3.6 V, VSTOP = 3.6 V Operating Quiescent Current in PWM Mode IQ_PWM 425 630 µA UNDERVOLTAGE LOCKOUT UVLO UVLO Threshold Rising VUVLO_RISING 2.06 2.14 V Falling VUVLO_FALLING 1.90 2.00 V OSCILLATOR CIRCUIT Switching Frequency in PWM Mode fSW 1.7 2.0 2.3 MHz Feedback (FB) Threshold of Frequency Fold VOSC_FOLD 0.3 V SYNCHRONIZATION THRESHOLD SYNC Clock Range SYNCCLOCK 1.5 2.5 MHz SYNC High Level Threshold SYNCHIGH 1.2 V SYNC Low Level Threshold SYNCLOW 0.4 V SYNC Duty Cycle Range SYNCDUTY 100 1/fSW − 150 ns SYNC/MODE Leakage Current ISYNC_LEAKAGE 50 150 nA VSYNC/MODE = 3.6 V MODE TRANSITION Transition Delay from Hysteresis Mode to PWM Mode tHYS_TO_PWM 20 Clock cycles SYNC/MODE goes logic high from logic low EN PIN Input Voltage Threshold High VIH 1.2 V Low VIL 0.4 V Input Leakage Current IEN_LEAKAGE 25 nA STOP Switching PWM Switching Stop Delay tSTOP-RISE-DELAY 10 ns STOP goes logic high from low PWM Switching Resume Delay tSTOP-FAL L-DELAY 20 ns STOP goes logic low from high FB PIN Output Options by VID Resistor VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in various factory options PWM Mode Fixed VID Code Voltage Accuracy VFB_PWM_FIX −0.6 +0.6 % TJ = 25°C, output voltage setting via factory fuse Adjustable VID Code Voltage Accuracy VFB_PWM_ADJ −1.5 +1.5 % Output voltage setting via VID resistor
Rev. B | Page 5 of 21 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Hysteresis Mode Fixed VID Code Threshold Accuracy from Active Mode to Standby Mode VFB_HYS_FIX −0.75 +0.75 % TJ = 25°C Adjustable VID Code Threshold Accuracy from Active Mode to Standby Mode VFB_HYS_ADJ −3 +3 % −40°C ≤ TJ ≤ +125°C Hysteresis of Threshold Accuracy from Active Mode to Standby Mode VFB_HYS (HYS) 1 % Feedback Bias Current IFB 66 95 nA Output Option 0, VOUT = 2.5 V 25 45 nA Output Option 1, VOUT = 1.3 V SW PIN High-Side Power FET On Resistance RDS (ON) H 386 520 mΩ Pin to pin measurement Low-Side Power FET On Resistance RDS (ON) L 299 470 mΩ Pin to pin measurement Current Limit in PWM Mode ILIM_PWM 800 1000 1200 mA SYNC/MODE = high Peak Current in Hysteresis Mode ILIM_HYS 265 mA SYNC/MODE = low Minimum On Time tMIN_ON 40 70 ns VOUTOK PIN Monitor Threshold VOUTOK (RISE) 87 90 93 % Monitor Hysteresis VOUTOK (HYS) 3 % Monitor Rising Delay tVOUTOK_RISE 40 µs Monitor Falling Delay tVOUTOK_F ALL 10 µs Leakage Current IVOUTOK_LEAKAGE 0.1 1 µA Output Low Voltage VOUTOK_LOW 50 80 mV IVOUTOK = 100 µA SOFT START Default Soft Start Time tSS 350 µs Factory trim, 1 bit (350 µs and 2800 µs) Start-Up Delay tSTART_DELAY 2 ms Delay from the EN pin being pulled high COUT DISCHARGE SWITCH ON RESISTANCE RDIS 290 Ω THERMAL SHUTDOWN Threshold TSHDN 142 °C Hysteresis THYS 127 °C
Table 3. Thermal Resistance
10 PVIN
- THE EXPOSED PAD MUST BE SOLDERED TO A
UNDERNEATH THE IC FOR THERMAL DISSIPATION. Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1 EN Enable Input for the Regulator. Set to logic low to disable the regulator. pin is logic low, the regulator resumes the regulator switching. connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz. PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode. voltage of the regulator (see Table 5). 5 FB Feedback Sensing Input for the Regulator. 6 VOUTOK Output Power-Good Signal. This open-drain outp ut is the power-good signal for the output voltage. 9 SW Switching Node Output for the Regulator. 10 PVIN Power Input for the Regulator.
Li-Ion cells and other power sources. low quiescent current as well as high efficiency performance. up and generates the PWM pulses to charge the output again. is larger than the ripple in PWM mode. configuration in hysteresis mode or PWM mode. PWM mode, which is useful for noise sensitive applications. the system switches between active mode and standby mode. frequency transitions to the frequency of the external clock. switches back to the internal clock. accuracy resistor through VID to ground is recommended. Table 5. Output Voltage (V
Rev. B | Page 15 of 21 UNDERVOLTAGE LOCKOUT (UVLO) The undervoltage lockout circuitry monitors the input voltage level on the PVIN pin. If the input voltage falls below 2.00 V (typical), the regulator turns off. After the input voltage rises above 2.06 V (typical), the soft start period initiates, and when the EN pin is high, the regulator enables. ENABLE/DISABLE The ADP5300 includes a separate enable (EN) pin. A logic high on the EN pin starts the regulator. Due to the low quiescent current design, it is typical for the regulator to start switching after a delay of a few milliseconds from the EN pin being pulled high. A logic low on the EN pin immediately disables the regulator and brings the regulator into extremely low current consumption. CURRENT LIMIT The buck regulators in the ADP5300 have protection circuitry that limits the direction and the amount of current to a certain level that flows through the high-side MOSFET and the low- side MOSFET in cycle-by-cycle mode. The positive current limit on the high-side MOSFET limits the amount of current that can flow from the input to the output. The negative current limit on the low-side MOSFET prevents the inductor current from reversing direction and flowing out of the load. SHORT-CIRCUIT PROTECTION The buck regulators in the ADP5300 include frequency foldback to prevent current runaway on a hard short. When the output voltage at the feedback (FB) pin falls below 0.3 V typical, indicating the possibility of a hard short at the output, the switching frequency (in PWM mode) is reduced to one-fourth of the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. SOFT START The ADP5300 has an internal soft start function that ramps up the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This feature prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the device. The default typical soft start time is 350 µs for the regulator. A different soft start time (2800 µs) can be programmed for ADP5300 by the factory fuse. STARTUP WITH PRECHARGED OUTPUT The buck regulators in the ADP5300 include a precharged start-up feature to protect the low-side MOSFET from damage during startup. If the output voltage is precharged before the regulator turns on, the regulator prevents reverse inductor current, which discharges the output capacitor, until the internal soft start reference voltage exceeds the precharged voltage on the FB pin. 100% DUTY OPERATION When the input voltage approaches the output voltage, the ADP5300 stops switching and enters 100% duty cycle operation. It connects the output via the inductor and the internal high-side power switch to the input. When the input voltage is charged again and the required duty cycle falls to 95% typical, the buck immediately restarts switching and regulation without allowing overshoot on the output voltage. In hysteresis mode, the ADP5300 draws an ultralow quiescent current of only 570 nA typical during 100% duty cycle operation. ACTIVE DISCHARGE The regulator in the ADP5300 integrates an optional, factory programmable discharge switch from the switching node to ground. This switch turns on when its associated regulator is disabled, which helps discharge the output capacitor quickly. The typical value of the discharge switch is 290 Ω for the regulator. By default, the discharge function is not enabled. The factory fuse can enable the active discharge function. VOUTOK FUNCTION The ADP5300 includes an open-drain, power-good output (VOUTOK pin) that is active high when the buck regulator operates normally. By default, the VOUTOK pin monitors the output voltage. A logic high on the VOUTOK pin indicates that the regulated output voltage of the buck regulator is above 90% (typical) of its nominal output. When the regulated output voltage of the buck regulator falls below 87% (typical) of its nominal output for a delay time greater than approximately 10 µs, the VOUTOK pin goes low.
temporarily stop the regulator switching in hysteresis mode. when the STOP signal goes high to fully stop switching. Figure 40. STOP Switching Operation Status thermal shutdown, a soft start initiates for each enabled channel.
ADP5300. The typical application circuit is shown in Figure 41. Figure 41. Typical Application Circuit the choice of external components. increases the core temperature rise and enlarges the core loss. Use the inductor series from the different vendors shown in Table 6. ESRCOUT is the ESR of the chosen capacitor. VRIPPLE is the peak-to-peak output voltage ripple. and may reduce output ripple and enhance load transient response. account for the loss of capacitance due to output voltage dc bias. Use the capacitor series from the different vendors shown in Table 7. Table 6. Recommended Inductors 1 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current. Table 7. Input and Output Capacitors
temperature and with the input voltage decrease. core losses and low electromagnetic interference (EMI). turn on and turn off the power devices at the switching frequency. then from the gate to ground. CGATE_H is the gate capacitance of the internal high-side switch. CGATE_L is the gate capacitance of the internal low-side switch. fSW is the switching frequency in PWM mode. twice for each switching cycle. tR is the rise time of the SW node. tF is the fall time of the SW node. The typical value for the rise and fall times, tR and tF, is 2 ns. Figure 42. Typical PCB Layout
To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 8. Output Voltage VID Setting Options Table 9. Output Discharge Functionality Options Table 10. Soft-Start Timer Options
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
0.20 MIN
Figure 45. 10-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.