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Triple 1800 mA Buck Regulator with Precision Enables and Power-Good Outputs Data Sheet ADP5135 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Input voltage range: 3.0 V to 5.5 V Three 1800 mA buck regulators 24-lead, 4 mm × 4 mm LFCSP package Regulator accuracy: ±1.8% Factory programmable or external adjustable VOUTx pins Precision enables for easier power sequencing Power-good pins for monitoring each regulator
3 MHz buck operation with forced PWM and auto PWM/PSM
BUCK1/BUCK2/BUCK3: output voltage range from 0.8 V to 3.8 V
APPLICATIONS
Power for processors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and radio frequency (RF) chipsets Portable instrumentation and medical devices Space constrained devices TYPICAL APPLICATION CIRCUIT Figure 1. GENERAL DESCRIPTION The ADP5135 combines three high performance buck regulators (BUCK1, BUCK2, and BUCK3). It is available in a 24-lead, 4 mm × 4 mm LFCSP. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set to high, the buck regulators operate in forced pulse-width modulation (PWM) mode. When the MODE pin is set to low, the buck regulators operate in PWM mode only when the load is above a predefined threshold. When the load current falls below this predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. BUCK1 and BUCK2 operate in synchronization, and BUCK3 operates out of phase to reduce the input capacitor requirement. Regulators in the ADP5135 are activated through dedicated enable pins. The default output voltages can be externally set in the adjustable version, or factory programmable to a wide range of preset values in the fixed voltage version. Table 1. Family Devices
2 ENx pins
Rev. 0 | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
11/14—Revision 0: Initial Version
Rev. 0 | Page 3 of 24 SPECIFICATIONS VAVIN = VIN1 = VIN2 = VIN3 = 3.0 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VAVIN, VIN1, VIN2, VIN3 3.0 5.5 V THERMAL SHUTDOWN Threshold TS SD T J rising 150 °C Hysteresis TS SD_HYS 20 °C START-UP TIME1 BUCK1 t START1 450 μs BUCK2 t START2 550 μs BUCK3 t START3 550 μs START-UP TIME, BUCK3 FIRST BUCK3 t START4 550 μs BUCK1 t START5 200 μs BUCK2 t START6 300 μs SHUTDOWN CONTROL All ENx pins below VIL_EN level to achieve ISHUTDOWN V Level High VIH_EN 0.9 Level Low VIL_EN 0.35 V PRECISION ENABLE PINS Regulator activation/deactivation thresholds V Analog Activation Threshold V ENR Device out of shutdown (V ENx > VIH_EN) 0.94 0.97 1 Hysteresis (Regulator Deactivation) V ENH 80 mV Input Leakage Current VI-LEAKAGE 0.05 1 μA POWER-GOOD PINS Monitors VOUT falling out of regulation Falling Threshold VPGLOW 85 % V OUT Rising Threshold VPGHYS 91 94 97 % V OUT Delay t PGDLY 20 μs Leakage Current IPGIQ V PG = VIN 1 μA Output Voltage Low VPGOL Load current = 1 mA 0.02 0.15 V MODE PIN Level High VIH_MOD 1.1 V Level Low VIL_MOD 0.4 V INPUT CURRENT No load, no buck switching All Channels Enabled ISTBY_NOSW 85 110 μA All Channels Disabled ISHUTDOWN T J = −40°C to +85°C 0.3 1.5 μA AVIN UNDERVOLTAGE LOCKOUT Mid UVLO Input Voltage Rising UVLO AVINRISE 2.95 V Mid UVLO Input Voltage Falling UVLO AVINFALL 2.45 V 1 Start-up time is defined as the time from EN1 = EN2 = EN3 at 0 V to VAVIN to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. 0 | Page 4 of 24 BUCK1, BUCK2, AND BUCK3 VAVIN = VIN1 = VIN2 = VIN3 = 3.0 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔVOUT1/VOUT1, ΔVOUT2/VOUT2, ΔVOUT3/VOUT3 PWM mode; ILOAD1 = ILOAD2 = ILOAD3 = 0 mA −1.8 +1.8 % Line Regulation (ΔVOUT1/VOUT1)/ΔVIN1, (ΔVOUT2/VOUT2)/ΔVIN2, (ΔVOUT3/VOUT3)/ΔVIN3 PWM mode −0.05 %/V Load Regulation (ΔVOUT1/VOUT1)/ΔIOUT1, (ΔVOUT2/VOUT2)/ΔIOUT2, (ΔVOUT3/VOUT3)/ΔIOUT3 ILOAD = 0 mA to 1800 mA, PWM mode −0.1 %/A VOLTAGE FEEDBACK V FB1, VFB2 Models with adjustable outputs 0.491 0.5 0.509 V OPERATING SUPPLY CURRENT MODE = ground BUCK1 Only IIN1 ILOAD1 = 0 mA, device not switching, all other channels disabled 42 μA BUCK2 Only IIN2 ILOAD2 = 0 mA, device not switching, all other channels disabled 52 μA BUCK3 Only IIN3 ILOAD3 = 0 mA, device not switching, all other channels disabled 52 μA BUCK1, BUCK2, and BUCK3 IIN ILOAD1 = ILOAD2 = ILOAD3 = 0 mA, device not switching 85 μA PSM CURRENT THRESHOLD I PSM PSM to PWM operation 100 mA SWx CHARACTERISTICS SWx On Resistance R NFET V IN1 = VIN2 = VIN3 = 3.6 V 140 225 mΩ R PFET V IN1 = VIN2 = VIN3 = 3.6 V 190 295 mΩ R NFET V IN1 = VIN2 = VIN3 = 5.5 V 122 189 mΩ R PFET V IN1 = VIN2 = VIN3 = 5.5 V 147 228 mΩ Current Limit ILIMIT1, ILIMIT2, ILIMIT3 Positive channel field effect transistor (PFET) switch peak current limit 2250 2600 2950 mA ACTIVE PULL-DOWN RESISTANCE RPWDN VIN1 = VIN2 = VIN3 = 3.6 V; channel disabled 75 Ω OSCILLATOR FREQUENCY f SW 2.5 3.0 3.5 MHz 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). INPUT AND OUTPUT CAPACITORS, RECOMMENDED TA = −40°C to +125°C, unless otherwise specified. Table 4. Parameter Symbol Min Typ Max Unit NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2, and BUCK3 Input Capacitor Ratings CMIN1, CMIN2, CMIN3 4.7 40 μF Output Capacitor Ratings CMIN4, CMIN5, CMIN6 10 40 μF CAPACITOR ESR RESR 0.001 1 Ω
Dissipation and Thermal Considerations section. soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance
Figure 2. Pin Configuration—View from the Top of the Die Table 7. Pin Function Descriptions 1 PG3 Open-Drain Power-Good Output to Monitor the Output Voltage of BUCK3. 2 PG2 Open-Drain Power-Good Output to Mo nitor the Output Voltage of BUCK2. 3 VIN2 BUCK2 Input Supply (3.0 V to 5.5 V). Connect VIN2 to VIN1, VIN3, and AVIN. 5 PGND2 Dedicated Power Ground for BUCK2. 6 PG1 Open-Drain Power-Good Output to Mo nitor the Output Voltage of BUCK1. 7 EN2 BUCK2 Enable. A high level turns on this regulator, and a low level turns it off. BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2. 10 VOUT1 BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1. BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 12 EN1 BUCK1 Enable. A high level turns on this regulator, and a low level turns it off. 13 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. 14 PGND1 Dedicated Power Ground for BUCK1. 15 SW1 BUCK1 Switching Node. 16 VIN1 BUCK1 Input Supply (3.0 V to 5.5 V). Connect VIN1 to VIN2, VIN3, and AVIN. 17 AVIN Analog Input Supply (3.0 V to 5.5 V). Connect AVIN to VIN1, VIN2, and VIN3. 19 PGND3 Dedicated Power Ground for BUCK3. 20 SW3 BUCK3 Switching Node. 21 VIN3 BUCK3 Input Supply (3.0 V to 5.5 V). Connect VIN3 to VIN1, VIN2 and AVIN. 22 VOUT3 BUCK3 Output Voltage Sensing Input. Connect VOUT3 to the top of the capacitor on VOUT3. BUCK3 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 24 EN3 BUCK3 Enable. A high level turns on this regulator, and a low level turns it off. EP Exposed Pad. Solder the exposed pad to the ground plane.
- SOLDER THE EXPOSED PAD TO THE GROUND
Figure 33. LFCSP PMOS RDSON vs. Input Voltage Across Temperature Figure 34. LFCSP NMOS RDSON vs. Input Voltage Across Temperature
Figure 35. Detailed Functional Block Diagram provide a small power management solution. the internal clock, and BUCK3 operates out of phase from it. activated by a logic high level applied to the respective ENx pin.
Rev. 0 | Page 14 of 24 Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values (see the Ordering Guide section). When a regulator is turned on, the output voltage ramp rate is controlled through a soft start circuit to avoid a large inrush current caused by the charging of the output capacitors. Power-Good Output Power-good outputs are available for each buck channel to monitor their respective output voltages. The PGx pin connects to a pull-up current to drive external regulators or other circuits. In this configuration, the PGx pin goes high when the channel being monitored is in regulation and goes low when the output voltage falls below 85% of the nominal VOUTx level. The PGx pin can also drive an LED for fault monitoring. In this configuration, a red LED, for example, is biased and current sinks into the PGx pin when the output voltage falls below 85% of the nominal VOUTx level, thereby turning the LED on, and turns off when the output voltage is in regulation. Thermal Protection In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off all the regulators. Extreme junction temperatures can be the result of high current opera- tion, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 130°C. When coming out of thermal shutdown, all regulators restart with soft start control. Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated into the system. If the input voltage on AVIN drops below the UVLO threshold, 2.45 V minimum, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the device is enabled once more. Alternatively, the user can request a new device model with a UVLO set at a higher level, suitable for 5 V supply applications, or to a lower level, suitable for low voltage operations. To order a device with options other than the default options listed in the Ordering Guide section, contact your local Analog Devices, Inc., sales or distribution representative. In case of a thermal or UVLO event, the active pull-downs (if factory enabled) are enabled to quickly discharge the output capacitors. The pull-down resistors remain engaged until the thermal fault event is no longer present or when the input supply voltage falls below the power-on reset voltage level POR). The typical value of VPOR is approximately 1 V. Precision Enable and Shutdown Control The ADP5135 has an individual enable control pin for each regulator. A voltage input to the ENx pin above the VIH_EN level puts the device out of shutdown and turns on the housekeeping block of the ADP5135. As the VENx level continues to rise above the precision enable threshold (VENR), the regulators activate. When VENx goes 80 mV typical below the VENR level, the regulators deactivate and, when all VENx levels continue to go down below the VIL_EN level, the device goes into shutdown mode. In this mode, the current consumption of the device drops to below 1.5 μA. Figure 36 shows the activation timings for the ADP5135 when the regulators are in sequence. VOUT1 is controlling EN2, and VOUT2 is controlling EN3. Also shown are the individual power- good signals (PGx) monitoring all regulators.
Rev. 0 | Page 16 of 24 Power Save Mode (PSM) The buck regulators smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When any of the bucks enters PSM, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level that is approximately 1.5% above the PWM regulation level, PWM operation turns off. At this point, both power switches are off, and the buck regulators enter an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. The ADP5135 has a dedicated MODE pin controlling the PSM and PWM operations. A logic high level applied to the MODE pin forces all bucks to operate in PWM mode. A logic low level sets the bucks to operate in auto PSM/PWM. PSM Current Threshold The PSM current threshold is set to 100 mA. The buck regulators employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from PSM. The PSM current threshold is optimized for excellent efficiency over all load currents. Oscillator/Phasing of Inductor Switching The ADP5135 ensures that all three bucks operate at the same switching frequency when all bucks are in PWM mode. Additionally, the ADP5135 ensures that when all bucks are in PWM mode, BUCK3 operates out of phase with BUCK1 and BUCK2, whereby the BUCK3 PFET starts conducting exactly half a clock period after the BUCK1 and BUCK2 PFETs start conducting. Short-Circuit Protection The bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possi- bility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. Buck Regulator Soft Start The buck regulators have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Current Limit Each buck regulator has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a drop in input voltage, or with an increase in load current, the buck regulators may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck regulators transition to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck regulators immediately restart PWM regulation without allowing overshoot on the output voltage. Active Pull-Down Resistors All regulators have optional, factory programmable, active pull- down resistors that discharge the respective output capacitors when the regulators are disabled. The pull-down resistors are connected between VOUTx and AGND. The active pull-down resistors are disabled when the regulators are turned on. The typical value of the pull-down resistor is 75 Ω.
Table 9. Suggested 2.2 μH Inductors 1 ISAT is the saturation current. expect a large load variation when working in PSM mode. output capacitor, a low ESR capacitor is recommended. Table 10. Suggested 22 μF Capacitors Table 11. Suggested 10 μF Capacitors Table 12. Suggested 4.7 μF Capacitors Table 13. Suggested 1.0 μF Capacitors
Figure 41. ADP5135 Fixed Output Voltages with Precision Enable Pins
Rev. 0 | Page 21 of 24 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5135 is a highly efficient micro PMU and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5135 turns off all the regulators, allowing the device to cool down. When the die temperature falls below 130°C, the ADP5135 resumes normal operation. This section provides guidelines to calculate the power dissi- pated in the device and to ensure that the ADP5135 operates below the maximum allowable operating junction temperature. The efficiency for each regulator on the ADP5135 is given by 100% IN OUT P P (1) where: η is the efficiency. POUT is the output power. PIN is the input power. Power loss is given by PLOSS = PIN − POUT (2a) or PLOSS = POUT (1− η)/η (2b) Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 3 to derive the power lost in the inductor and, from this, use Equation 7 to calculate the power dissipation in the ADP5135 buck converter. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 3 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 7. Add the power dissipated in the three bucks to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of V IN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11. BUCK REGULATOR POWER DISSIPATION The inductor losses are external to the device, and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL ≈ IOUT1(RMS)2 × DCRL (3) where: IOUT1(RMS) is the rms load current of the buck regulator. DCRL is the inductor series resistance. 12+ 1) ( rII OUT1RMS OUT1 (4) where r is the normalized inductor ripple current. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (5) where: L is the inductance. f SW is the switching frequency. D is the duty cycle. D = VOUT1/VIN1 (6) The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (7) where: P DBUCK is the power dissipation on one of the ADP5135 buck regulators. P L is the inductor power losses. The ADP5135 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. P DBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the P-channel MOSFET and the N-channel MOSFET power switches that have internal resistance, RDSON_P and RDSON_N, respectively. The amount of conductive power loss is found by PCOND = [RDSON_P × D + RDSON_N × (1 − D)] × IOUT1(RMS)2 (9) where RDSON_P is approximately 0.19 Ω, RDSON_N is approxi- mately 0.14 Ω at a 25°C junction temperature, and VIN1 = VIN2 = respectively.
Rev. 0 | Page 22 of 24 Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE_P + CGATE_N) × VIN12 × fSW (10) where: CGATE_P is the P-channel MOSFET gate capacitance. CGATE_N is the N-channel MOSFET gate capacitance. For the ADP5135, the total of (CGATE_P + CGATE_N) is approximately 150 pF. The transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously, and the SWx node takes some time to slew from near ground to near V OUT1 (and from VOUT1 to ground). The amount of transition loss (PTRAN) is calculated by PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11) where tRISE and tFALL are the rise time and the fall time, respectively, of the switching node, SWx. For the ADP5135, the rise and fall times of SWx are in the order of 5 ns. If Equation 1 to Equation 11 and their associated parameters are used for estimating the converter efficiency, note that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, include a sufficient safety margin in the estimate. The total power dissipation in the ADP5135 simplifies to P D = PDBUCK1 + PDBUCK2 + PDBUCK3 (12) JUNCTION TEMPERATURE In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) (13) Refer to Table 6 for the thermal resistance values of the LFCSP package. A very important factor to consider is that θJA is based on a 4-layer, 4 in × 3 in, 2.5 oz copper printed circuit board (PCB), as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. Solder the exposed pad to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by T J = TC + (PD × θJC) (14) where TC is the case temperature and θJC is the junction to case thermal resistance provided in Table 6. When designing an application for a particular ambient tempera- ture range, calculate the expected ADP5135 power dissipation (PD) due to the losses of all channels by using Equation 8 to Equation 12. From this power calculation, the junction tempera- ture, TJ, can be estimated using Equation 13. The reliable operation of the converter can be achieved only if the estimated die junction temperature of the ADP5135 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) are highly affected by increasing the junction temperature. Additional information about product reliability can be found in the ADI Reliability Handbook at www.analog.com/UG-311.
Rev. 0 | Page 23 of 24 PCB LAYOUT GUIDELINES Poor layout can affect ADP5135 performance, causing EMI and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to the ADP5135CP-EV ALZ user guide. Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SWx node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Connect VIN1, VIN2, VIN3, and AVIN together close to the IC using short tracks. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. For best performance, connect the input capacitors very close to the pins as follows: place the AVIN capacitor between the AVIN and AGND pins, place the VIN1 capacitor between the VIN1 and PGND1 pins, place the VIN2 capacitor between the VIN2 and PGND2 pins, and place the VIN3 capacitor between VIN3 and PGND3.
Figure 42. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 UVLO: low, mid, or high. To order a device with other than the default options listed, contact your local Analog Devices sales or distribution representative. 4 BUCK1, BUCK2, BUCK3: active pull-down resistor is programmable to be either enabled or disabled. COMPLIANT TOJEDEC STANDARDS MO-220-WGGD-8.
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
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