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2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5076 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Input supply voltage range: 2.85 V to 5.5 V Generates well regulated, independently resistor programmable VPOS and VNEG outputs Boost regulator to generate VPOS output Adjustable positive output to 35 V Integrated 2.0 A main switch Inverting regulator to generate V NEG output Adjustable negative output to −30 V Integrated 1.20 A main switch 1.2 MHz or 2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to
2.6 MHz
Resistor programmable soft start timer Slew rate control for lower system noise Individual precision enable and flexible start-up sequence control for symmetric start, V POS first, or VNEG first Out of phase operation UVLO, OCP , OVP , and TSD protection 1.61 mm × 2.18 mm, 20-ball WLCSP −40°C to +125°C junction temperature range
APPLICATIONS
Bipolar amplifiers, ADCs, DACs, and multiplexers Charge coupled device (CCD) bias supply Optical module supply RF power amplifier bias Time of flight module supply GENERAL DESCRIPTION The ADP5076 is a dual, high performance, dc-to-dc regulator that generates independently regulated positive and negative rails. The input voltage range of 2.85 V to 5.5 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +35 V and a negative output voltage down to −30 V . The ADP5076 operates at a pin selected 1.2 MHz or 2.4 MHz switching frequency. The ADP5076 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the metal-oxide semiconductor field effect transistor (MOSFET) driver stage to reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first. The ADP5076 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. Other key safety features in the ADP5076 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5076 is available in a 20-ball wafer level chip scale package (WLCSP) and is rated for a −40°C to +125°C junction temperature range. Table 1. Family Models
Rev. A | Page 2 of 23 TABLE OF CONTENTS
REVISION HISTORY
12/2019—Rev. 0 to Rev. A 8/2019—Revision 0: Initial Version
Rev. A | Page 3 of 23 SPECIFICATIONS PVIN = AVIN = +2.85 V to +5.5 V , adjustable positive output voltage (VPOS) = +15 V , adjustable negative output voltage (VNEG) = −15 V , switching frequency (fSW) = 1200 kHz, junction temperature (TJ) = −40°C to +125°C for minimum and maximum specifications, and ambient temperature (TA) = +25°C for typical specifications, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE VIN 2.85 5.5 V PVIN pin, AVIN pin QUIESCENT CURRENT Operating Quiescent Current Sum of PVIN and AVIN IQ 3.5 4.0 mA No switching, EN1 pin = EN2 pin = high Standby Current ISTNDBY 2.05 2.2 mA No switching, EN1 pin = EN2 pin = low UVLO System UVLO Threshold AVIN pin Rising V UVLO_RISING 2.8 2.85 V Falling V UVLO_FALLING 2.5 2.55 V Hysteresis V HYS_1 0.25 V OSCILLATOR CIRCUIT Switching Frequency fSW 1.130 1.200 1.270 MHz SYNC pin = low 2.240 2.400 2.560 MHz SYNC pin = high (connect to AVIN pin) SYNC Input Input Clock Range fSYNC 1.000 2.600 MHz Input Clock Minimum On Pulse Width t SYNC_MIN_ON 100 ns Input Clock Minimum Off Pulse Width t SYNC_MIN_OFF 100 ns Input Clock High Logic VH (SYNC) 1.3 V Input Clock Low Logic VL (SYNC) 0.4 V PRECISION ENABLING (EN1, EN2) High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve I STNDBY Pull-Down Resistance REN 1.48 MΩ BOOST REGULATOR Adjustable Positive Output Voltage V POS 35 V Feedback Voltage VFB1 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % T J = 25°C Feedback Bias Current IFB1 0.1 μA Overvoltage Protection Threshold V OV1 0.86 V At FB1 pin Load Regulation (∆VFB1/VFB1)/ΔILOAD1 0.0003 %/mA I LOAD11 = 5 mA to 150 mA Line Regulation (∆VFB1/VFB1)/ΔVPVIN 0.002 %/V I LOAD1 = 50 mA Error Amplifier (EA) Transconductance G M1 260 300 340 μA/V Power Field Effect Transistor (FET) On Resistance RDS (ON) BOOST 175 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) BOOST 39 V Current-Limit Threshold, Main Switch I LIM (BOOST) 2.0 2.2 2.4 A Minimum On Time 50 ns Minimum Off Time 25 ns
Rev. A | Page 4 of 23 Parameter Symbol Min Typ Max Unit Test Conditions/Comments INVERTING REGULATOR Adjustable Negative Output Voltage V NEG −30 V Reference Voltage VREF 1.60 V Reference Voltage Accuracy −0.5 +0.5 % T J = 25°C Feedback Voltage VREF − VFB2 0.8 V VFB2 is the FB2 reference voltage Feedback Voltage Accuracy −0.5 +0.5 % T J = 25°C Feedback Bias Current IFB2 0.1 μA Overvoltage Protection Threshold V OV2 0.74 V At FB2 pin after soft start has completed Load Regulation (∆(VREF − VFB2)/(VREF − VFB2))/∆ILOAD2 0.0004 %/mA I LOAD2 = 5 mA to 75 mA Line Regulation (∆(VREF − VFB2)/(VREF − VFB2))/ΔVPVIN 0.003 %/V I LOAD2 = 25 mA EA Transconductance GM2 260 300 340 μA/V Power FET On Resistance RDS (ON) INVERTER 350 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) INVERTER 39 V Current-Limit Threshold, Main Switch I LIM (INVERTER) 1.20 1.32 1.44 A Minimum On Time 60 ns Minimum Off Time 50 ns SOFT START Soft Start Timer for DC-DC Regulators t SS 4 ms SS pin = open 32 ms SS resistor = 50 kΩ to GND Hiccup Time tHICCUP 8 × t SS ms THERMAL SHUTDOWN Threshold T SHDN 150 °C Hysteresis T HYS 15 °C 1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
PCB thermal design is required. top of package thermal characterization parameter. calculating junction to case temperature in the application. Table 4. Thermal Resistance
Figure 2. Pin Configuration (Top View) Table 5. Pin Function Descriptions A1, B2 PVIN Power Input for the Inverter Regulator. A2 SW2 Switching Node for the Inverting Regulator. A3, B3 SW1 Switching Node for the Boost Regulator. A4, B4 PGND Power Ground for the Boost Regulator. B1 AVIN System Power Supply for the ADP5076. the inverting regulator output. connect the SYNC pin to an external clock. SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to the AVIN pin. the slowest slew rate (best noise performance), connect the SLEW pin to the AGND pin. start time, connect a resistor between the SS pin and the AGND pin. regulator output capacitor and the AGND pin to program the output voltage. inverting regulator output capacitor and the VREF pin to program the output voltage.
Figure 39. Typical Application Circuit switch turns on, applying a positive voltage across the inductor. voltage by adjusting the peak inductor current threshold. regulators can skip pulses to maintain output voltage regulation. Skipping pulses increases the device efficiency. and the regulators are enabled. peak current consumption and noise. Table 6. SYNC Pin Options the circuit from accidental loading.
UVLO input by using a resistor divider. each regulator to off when the pin is floating. reference level, the regulator is enabled. the fastest rate when the SS pin is open. Figure 40. Switching Node at Various Slew Rate Settings current through the MOSFET switch. and FB2 pins for the boost and inverting regulators. after the soft start period has elapsed. can be implemented via the SEQ pin, as explained in Table 7. Table 7. SEQ Pin Settings To configure the manual enable mode, leave the SEQ pin open. their respective precision enable pins.
VPOS is the positive output voltage. VFB1 is the FB1 reference voltage. RFT1 is the feedback resistor from VPOS to FB1. RFB1 is the feedback resistor from FB1 to AGND. VNEG is the negative output voltage. VFB2 is the FB2 reference voltage. RFT2 is the feedback resistor from VNEG to FB2. RFB2 is the feedback resistor from FB2 to VREF. VREF is the VREF pin reference voltage. Table 8. Recommended Feedback Resistor Values for Boost Regulator Table 9. Recommended Feedback Resistor Values for Inverting Regulator
25 V or 50 V (depending on output) are recommended for best
temperature and dc bias characteristics. CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst-case capacitor temperature coefficient. DCBIASCO is the dc bias derating at the output voltage. Tolerance is the worst-case component tolerance. behavior of the capacitors be evaluated for each application. suggested as a good balance between performance and size. ripple and improve transient response. The effective capacitance needed for stability is a minimum of 10 μF. Figure 43. Soft Start Behavior where VDIODE1 is the forward voltage drop of D1.
Rev. A | Page 18 of 23 The dc input current in CCM (IIN) can be determined using the following equation: (1 ) OUT1 IN II DUTY Using the DUTY1 and fSW, determine the on time (tON1) using the following equation: ON1 SW DUTYt f The inductor ripple current (IL1) in steady state is calculated using the following equation: INO N 1 VtI L1 Solve for the inductor (L1) using the following equation: INO N 1 VtL1 I Assuming an inductor ripple current of 30% of the maximum dc input current, solve for L1 using the following equation: (1 ) 0.3 1IN ON1 OUT1 Vt D U T YL1 I Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When the ADP5076 boost regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. This slope compensation is built in to the ADP5076. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance (L MIN1) for the application parameters in the following equation: 0.13 0.16( µH1) MIN1 IN L1 L V DUTY Table 11 suggests a series of inductors to use with the ADP5076 boost regulator. Inductor Selection for the Inverting Regulator The inductor stores energy during the on time of the power switch and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 μH to 22 μH are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current that is close to 30% of the maximum dc current in the inductor typically yields an optimal compromise. For the inductor ripple current in CCM operation, the V IN and output voltage (VNEG) determine the switch duty cycle (DUTY2) using the following equation: DIODE2NEGIN DIODE2NEG V V V V VDUTY | | | | where VDIODE2 is the forward voltage drop of D2. The dc current in the inductor in CCM (IL2) can be determined using the following equation: (1 ) OUT2 II DUTY Using the DUTY2 and fSW, determine the on time (tON2) using the following equation: ON2 SW DUTYt f The inductor ripple current (IL2) in steady state is calculated using the following equation: INO N 2 VtI L2 Solve for the inductor (L2) using the following equation: INO N 2 VtL2 I Assuming an inductor ripple current of 30% of the maximum dc current in the inductor, solve for L2 using the following equation: (1 ) 0.3 2IN ON2 OUT2 Vt D U T YL2 I Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When the ADP5076 inverting regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance (L MIN2) for the application parameters in the following equation: 0.13 0.16( µH1) MIN2 IN L2 L V DUTY Table 12 suggests a series of inductors to use with the ADP5076 inverting regulator. LOOP COMPENSATION The ADP5076 uses external components to compensate the regulator loop, allowing the optimization of the loop dynamics for a given application.
fZ1(RHP) is the right half plane zero frequency. is also equal to the output voltage divided by the load current. VFB1 is the feedback regulation voltage. VPOS is the regulated positive output voltage. GM1 is the error amplifier transconductance gain. ROUT1 is the output impedance of the error amplifier and is 33 MΩ. internally set by the ADP5076 and is 12.5 A/V . operates under in the calculation for RC1. where CC1 is the compensation capacitor value. Figure 44. Compensation Components undesirable right half plane zero in the regulation feedback loop. fZ2(RHP) is the right half plane zero frequency. VFB2 is the FB2 reference voltage. VNEG is the regulated negative output voltage. GM2 is the error amplifier transconductance gain. ROUT2 is the output impedance of the error amplifier and is 33 MΩ.
below the appropriate current limit specifications. Table 11. Recommended Boost Regulator Small Sized Components
1 COUT1 = 10 μF
Table 12. Recommended Inverting Regulator Small Sized Components
1 COUT2 = 10 μF
their connections to the ADP5076. between the input and output capacitors. and L2 to prevent radiated switching noise injection. OUT1 and COUT2 for optimum output voltage sensing. CC2) as close as possible to the COMP1 and COMP2 pins. sensitive COMP1 and COMP2 pins. Figure 48. Suggested Layout for VIN = +3.3 V, VPOS = +15 V, ILOAD1 = 90 mA and
1.60 REF
1.20 REF
Figure 49. 20-Ball Wafer Level Chip Scale Package [WLCSP] registered trademarks are the prop erty of their respective owners.