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1 A/0.6 A DC to DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5072 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Input supply voltage range: 2.85 V to 5.5 V Generates well regulated, independently resistor programmable VPOS and VNEG outputs Boost regulator to generate VPOS output Adjustable positive output to 35 V Integrated 1.0 A main switch Inverting regulator to generate VNEG output Adjustable negative output to −30 V Integrated 0.6 A main switch 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz Resistor programmable soft start timer Slew rate control for lower system noise Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first Out of phase operation UVLO, OCP , OVP , and TSD protection 1.61 mm × 2.18 mm, 20-ball WLCSP −40°C to +125°C junction temperature range

APPLICATIONS

Bipolar amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and multiplexers Charge coupled device (CCD) bias supplies Optical module supplies RF power amplifier bias Time of flight module supplies TYPICAL APPLICATION CIRCUIT ADP5072 SS SW1 SW1 RC1 CC1 COMP1 RC2 CC2 COMP2 EN1 SYNC SLEW SEQ EN2 AGND PVIN PVIN AVINCIN VIN FB1 VIN RFB1 RFT1 VPOS SW2 PGND PGND FB2 VREF RFB2 RFT2 VNEG CVREF COUT1 COUT2 12069-001 Figure 1. GENERAL DESCRIPTION The ADP5072 is a dual, high performance dc-to-dc regulator that generates independently regulated positive and negative rails. The input voltage range of 2.85 V to 5.5 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to 35 V and a negative output voltage down to −30 V. The ADP5072 operates at a pin selected 1.2 MHz or 2.4 MHz switching frequency. The ADP5072 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programma- ble slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first. The ADP5072 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. Other key safety features in the ADP5072 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5072 is available in a 20-ball WLCSP and is rated for a −40°C to +125°C junction temperature range. Table 1. Family Models

Rev. 0 | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

1/2019—Revision 0: Initial Version

Rev. 0 | Page 3 of 24 SPECIFICATIONS PVIN = AVIN = 2.85 V to 5.5 V, positive output voltage (VPOS) = 15 V, negative output voltage (VNEG) = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE RANGE VIN 2.85 5.5 V PVIN, AVIN QUIESCENT CURRENT Operating Quiescent Current PVIN, AVIN (Total) IQ 3.5 4.0 mA No switching, EN1 = EN2 = high, PVIN = AVIN = 5 V Standby Current ISTNDBY 2.05 2.2 mA No switching, EN1 = EN2 = low, PVIN = AVIN = 5 V UVLO System UVLO Threshold AVIN Rising VUVLO_RISING 2.8 2.85 V Falling VUVLO_FALLING 2.5 2.55 V Hysteresis VHYS 0.25 V OSCILLATOR CIRCUIT Switching Frequency fSW 1.130 1.2 1.270 MHz SYNC = low 2.240 2.4 2.560 MHz SYNC = high (connect to PVIN) SYNC Input Input Clock Range fSYNC 1.0 2.6 MHz Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns Input Clock High Logic VH (SYNC) 1.3 V Input Clock Low Logic VL (SYNC) 0.4 V PRECISION ENABLING (EN1, EN2) High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve I STNDBY Pull-Down Resistance REN 1.48 MΩ BOOST REGULATOR Adjustable Positive Output Voltage VPOS 35 V Feedback Voltage VFB1 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C Feedback Bias Current IFB1 0.1 µA Overvoltage Protection Threshold VOV1 0.86 V At FB1 pin Load Regulation (∆VFB1/VFB1)/ΔILOAD1 0.0003 %/mA ILOAD11 = 5 mA to 150 mA Line Regulation (∆VFB1/VFB1)/ΔVPVIN 0.002 %/V VPVIN = 2.85 V to 5.5 V, ILOAD1 = 50 mA Error Amplifier (EA) Transconductance gM1 260 300 340 µA/V Power FET On Resistance RDS (ON) BOOST 175 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) BOOST 39 V Current-Limit Threshold, Main Switch ILIM (BOOST) 1.0 1.1 1.3 A Minimum On Time 50 ns Minimum Off Time 25 ns

Rev. 0 | Page 4 of 24 Parameter Symbol Min Typ Max Unit Test Conditions/Comments INVERTING REGULATOR Adjustable Negative Output Voltage VNEG −30 V Reference Voltage VREF 1.60 V Reference Voltage Accuracy −0.5 +0.5 % TJ = 25°C Feedback Voltage VREF − VFB2 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C Feedback Bias Current IFB2 0.1 µA Overvoltage Protection Threshold VOV2 0.74 V At FB2 pin after soft start has completed Load Regulation (∆(VREF − VFB2)/(VREF − VFB2))/ ILOAD2 0.0004 %/mA ILOAD2 = 5 mA to 75 mA Line Regulation (∆(VREF − VFB2)/(VREF − VFB2))/ VPVIN 0.003 %/V VPVIN = 2.85 V to 5.5 V, ILOAD2 = 25 mA EA Transconductance gM2 260 300 340 µA/V Power FET On Resistance RDS (ON) INVERTER 350 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) INVERTER 39 V Current-Limit Threshold, Main Switch ILIM (INVERTER) 600 660 750 mA Minimum On Time 60 ns Minimum Off Time 50 ns SOFT START Soft Start Timer for DC to DC Regulators tSS 4 ms SS = open 32 ms SS resistor = 50 kΩ to GND Hiccup Time tHICCUP 8 × tSS ms THERMAL SHUTDOWN Threshold TSHDN 150 °C Hysteresis THYS 15 °C 1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).

PCB thermal design is required. case thermal characterization parameter. Table 4. Thermal Resistance

2 The thermal resistance values specified in Table 4 are simulated based on

Figure 2. Pin Configuration (Top View) Table 5. Pin Function Descriptions A1, B2 PVIN Power Input for the Boost Regulator. A2 SW2 Switching Node for the Inverting Regulator. A3, B3 SW1 Switching Node for the Boost Regulator. A4, B4 PGND Power Ground for the Boost Regulator. B1 AVIN System Power Supply for the ADP5072. the inverting regulator output. C2 SYNC Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC pin high. connect the SYNC pin to an external clock. slew rate (optimal efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to PVIN. For the slowest slew rate (optimal noise performance), connect the SLEW pin to AGND. start time, connect a resistor between the SS pin and AGND. regulator output capacitor and AGND to program the output voltage. inverting regulator output capacitor and VREF to program the output voltage. E3 VREF Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and AGND.

Figure 39. Functional Block Diagram voltage by adjusting the peak inductor current threshold. and the regulators are enabled. peak current consumption and noise. is configured using the SYNC pin options shown in Table 6. Table 6. SYNC Pin Options the circuit from accidental loading.

each regulator to off when the pin is floating. reference level, the regulator is enabled. set to the fastest rate when the SS pin is open. Figure 40. Switching Node at Various Slew Rate Settings current through the MOSFET switch. and FB2 pins for the boost and inverting regulators. after the soft start period has elapsed. can be implemented via the SEQ pin, as explained in Table 7. Table 7. SEQ Pin Settings To configure the manual enable mode, leave the SEQ pin open. their respective precision enable pins.

current through the divider is at least 10 times IFB1 or IFB2. VPOS is the positive output voltage. VFB1 is the FB1 reference voltage. RFT1 is the feedback resistor from VPOS to FB1. RFB1 is the feedback resistor from FB1 to AGND. VNEG is the negative output voltage. VFB2 is the FB2 reference voltage. RFT2 is the feedback resistor from VNEG to FB2. RFB2 is the feedback resistor from FB2 to VREF . VREF is the VREF pin reference voltage. Table 8. Recommended Feedback Resistor Values

25 V or 50 V (depending on output) are recommended for optimal

temperature and dc bias characteristics. CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst-case capacitor temperature coefficient. Tolerance is the worst case component tolerance. behavior of the capacitors be evaluated for each application. ripple and improve transient response. The effective capacitance needed for stability is a minimum of 10 μF. Figure 43. Soft Start Behavior junction capacitance is a significant contributor to efficiency. when the output voltage is greater than 5 V .

Rev. 0 | Page 18 of 24 For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VPOS) voltages determine the switch duty cycle (DUTY1) by the following equation: DIODE1POS IN POS DIODE1 V VVDUTY VV where VDIODE1 is the forward voltage drop of the Schottky diode (D1). The dc input current in CCM (IIN) can be determined by the following equation: (1 ) OUT1 IN II DUTY= − Using the duty cycle (DUTY1) and switching frequency (fSW), determine the on time (tON1) using the following equation: ON1 SW DUTYt f= The inductor ripple current (∆IL1) in steady state is calculated by IN ON1 VtI L1 ×∆= Solve for the inductance value (L1) using the following equation: IN ON1 VtL1 I ×= ∆ Assuming an inductor ripple current of 30% of the maximum dc input current results in (1 ) 0.3 1IN ON1 OUT1 V t DUTYL1 I × ×−= × Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is less than the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When the ADP5072 boost regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. This slope compensation is built in to the ADP5072. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, L MIN1, for the application parameters in the following equation: 0.13 0.16(1 ) MIN1 IN L1 L V DUTY (µH) Table 10 suggests a series of inductors to use with the ADP5072 boost regulator. Inductor Selection for the Inverting Regulator The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 µH to 22 µH are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current close to 30% of the maximum dc current in the inductor typically yields an optimal compromise. For the inductor ripple current in continuous conduction mode (CCM) operation, the input (V IN) and output (VNEG) voltages determine the switch duty cycle (DUTY2) by the following equation: DIODE2NEG2 DIODE2IN NEG VVDUTY VV V where VDIODE2 is the forward voltage drop of the Schottky diode (D2). The dc current in the inductor in CCM (IL2) can be determined by the following equation: (1 ) OUT2 II DUTY= − Using the duty cycle (DUTY2) and switching frequency (fSW), determine the on time (tON2) by the following equation: ON2 SW DUTYt f= The inductor ripple current (∆IL2) in steady state is calculated by IN ON2 VtI L2 ×∆= Solve for the inductance value (L2) by the following equation: IN ON2 VtL2 I ×= ∆ Assuming an inductor ripple current of 30% of the maximum dc current in the inductor results in (1 ) 0.3 IN ON2 2 OUT2 V t DUTYL2 I × ×−= × Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is less than the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator.

fZ1(RHP) is the right half plane zero frequency. divided by the load current. VPOS is the regulated positive output voltage. gM1 is the error amplifier transconductance gain. ROUT1 is the output impedance of the error amplifier and is 33 MΩ. set by the ADP5072 and is 6.25 A/V . is dominated by the impedance of an output capacitor (COUT1). where fC1 is the crossover frequency. under which it operates in the calculation for RC1. where CC1 is the compensation capacitor value. Figure 44. Compensation Components

undesirable right half plane zero in the regulation feedback loop. fZ2(RHP) is the right half plane zero frequency. divided by the load current. VFB2 is the feedback regulation voltage. VNEG is the regulated negative output voltage. gM2 is the error amplifier transconductance gain. ROUT2 is the output impedance of the error amplifier and is 33 MΩ. set by the ADP5072 and is 6.25 A / V. is dominated by the impedance of the output capacitor, COUT2. where fC2 is the crossover frequency. under which it operates in the calculation for RC2. where CC2 is the compensation capacitor. Figure 45. Compensation Component

Table 10. Recommended Boost Regulator Small Sized Components Table 11. Recommended Inverting Regulator Small Sized Components

  • Keep the input bypass capacitor, CIN, close to the PVIN pin and the AVIN pin.
  • Keep the high current paths as short as possible. These paths include the connections between the following:
  • CIN, L1, D1, COUT1, and PGND for the boost regulator, the connections
  • L2, D2, COUT2, and PGND for the inverting regulator
  • The connections of these components for both the boost and inverting regulators to the ADP5072.
  • Keep AGND and PGND separate on the top layer of the board. This separation avoids pollution of AGND with switching noise. Connect both AGND and PGND to the board ground plane with vias. Ideally, connect PGND to the plane at a point between the input and output capacitors.
  • Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and EMI.
  • Avoid routing high impedance traces near any node con- nected to the SW1 and SW2 pins or near Inductors L1and L2 to prevent radiated switching noise injection.
  • Place the feedback resistors as close to the FB1 and FB2 pins as possible to prevent high frequency switching noise injection.
  • Place the top of the upper feedback resistors, RFT1 and RFT2, as close as possible to the top of COUT1 and COUT2 for optimum output voltage sensing, or route traces to the RFT1 and RFT2 resistors as close as possible from the top of COUT1 and COUT2.
  • Place the compensation components as close as possible to COMP1 and COMP2. Do not share vias to the ground plane with the feedback resistors to avoid coupling high frequency noise into the sensitive COMP1 and COMP2 pins.
  • Place the CVREF capacitor as close to the VREF pin as possible. Ensure that short traces are used between VREF and RFB2. 16646-045

Figure 48. Suggested Layout for VIN = 3.3 V, VPOS = 12 V, ILOAD1 = 100 mA and

1.60 REF

1.20 REF

Figure 49. 20-Ball Wafer Level Chip Scale Package [WLCSP] registered trademarks are the property of their respective owners.