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1 A/0.6 A, DC-to-DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5070 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Wide input supply voltage range: 2.85 V to 15 V Generates well regulated, independently resistor programmable VPOS and VNEG outputs Boost regulator to generate VPOS output Adjustable positive output to 39 V Integrated 1.0 A main switch Optional single-ended primary-inductor converter (SEPIC) configuration for automatic step-up/step-down Inverting regulator to generate VNEG output Adjustable negative output to VIN − 39 V Integrated 0.6 A main switch True shutdown for both positive and negative outputs 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz Resistor programmable soft start timer Slew rate control for lower system noise Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first Out-of-phase operation UVLO, OCP, OVP, and TSD protection 4 mm × 4 mm, 20-lead LFCSP and 20-lead TSSOP −40°C to +125°C junction temperature range Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, ADCs, DACs and multiplexers Charge-coupled device (CCD) bias supply Optical module supply RF power amplifier (PA) bias TYPICAL APPLICATION CIRCUIT ADP5070 SS INBK SW1 RC1 CC1 COMP1 RC2 CC2 COMP2 CVREG VREG EN1 SYNC/FREQ SLEW SEQ EN2 AGND PVIN1 PVIN2 PVINSYSCIN1 VIN FB1 RFB1 RFT1 VPOS SW2 PGND FB2 VREF RFB2 RFT2 VNEG CVREF COUT1 COUT2 12068-001 Figure 1. GENERAL DESCRIPTION The ADP5070 is a dual high performance dc-to-dc regulator that generates independently regulated positive and negative rails. The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +39 V and a negative output voltage down to −39 V below input voltage. The ADP5070 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5070 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first. The ADP5070 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, both regulators completely disconnect the loads from the input supply to provide a true shutdown. Other key safety features in the ADP5070 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5070 is available in a 20-lead LFCSP or in a 20-lead TSSOP and is rated for a −40°C to +125°C junction temperature range. Table 1. Family Models
ADP5070* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts View a parametric search of comparable parts Evaluation Kits
- ADP5070/ADP5071 Evaluation Board Documentation Application Notes
- AN-1359: Low Noise, Dual-Supply Solution Using the ADP5070 for the Precision AD5761R Bipolar DAC in Single-Supply Systems
- AN-1366: Using the ADP5070/ADP5071 to Create Positive and Negative Voltage Rails when VOUT < VIN
- AN-1368: Ferrite Bead Demystified Data Sheet
- ADP5070: 1 A/0.6 A, DC-to-DC Switching Regulator with Independent Positive and Negative Outputs User Guides
- UG-758: Evaluating the ADP5070CP/ADP5071CP LFCSP DC-to-DC Switching Regulators/Converters
- UG-848: Evaluating the ADP5070RE/ADP5071RE TSSOP DC-to-DC Switching Regulators/Converters Tools and Simulations
- ADIsimPower™ Voltage Regulator Design Tool
- ADP507x Design Tool Reference Materials Press
- Bias Generation and Level Setting Made Easy with Multiple Range, User Programmable Voltage Output D/A Converter Design Resources
- ADP5070 Material Declaration
- PCN-PDN Information
- Quality And Reliability
- Symbols and Footprints Discussions View all ADP5070 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.
Rev. A | Page 2 of 27 TABLE OF CONTENTS
REVISION HISTORY
6/15—Rev. 0 to Rev A Changes to Output Capacitors Section, Soft Start Resistor Section, 2/15—Revision 0: Initial Version
Rev. A | Page 3 of 27 SPECIFICATIONS PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, VPOS = 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE RANGE VIN 2.85 15 V PVIN1, PVIN2, PVINSYS QUIESCENT CURRENT Operating Quiescent Current PVIN1, PVIN2, PVINSYS (Total) IQ 3.5 4.0 mA No switching, EN1 = EN2 = high, PVIN1 = PVIN2 = PVINSYS = 5 V Shutdown Current ISHDN 5 10 µA No switching, EN1 = EN2 = low, PVIN1 = PVIN2 = PVINSYS = 5 V UVLO System UVLO Threshold PVINSYS Rising VUVLO_RISING 2.8 2.85 V Falling VUVLO_FALLING 2.5 2.55 V Hysteresis VHYS_1 0.25 V OSCILLATOR CIRCUIT Switching Frequency fSW 1.130 1.200 1.270 MHz SYNC/FREQ = low 2.240 2.400 2.560 MHz SYNC/FREQ = high (connect to VREG) SYNC/FREQ Input Input Clock Range fSYNC 1.000 2.600 MHz Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns Input Clock High Logic VH (SYNC) 1.3 V Input Clock Low Logic VL (SYNC) 0.4 V PRECISION ENABLING (EN1, EN2) High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve I SHDN Pull-Down Resistance REN 1.48 MΩ INTERNAL REGULATOR VREG Output Voltage VREG 4.25 V BOOST REGULATOR Feedback Voltage VFB1 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C Feedback Bias Current IFB1 0.1 µA Overvoltage Protection Threshold VOV1 0.86 V At FB1 pin Load Regulation ∆VFB1/ILOAD1 0.0003 %/mA ILOAD11 = 5 mA to 150 mA Line Regulation ∆VFB1/VPVIN1 0.002 %/V VPVIN1 = 2.85 V to 14.5 V, ILOAD11 = 15 mA Error Amplifier (EA) Transconductance gM1 270 300 330 µA/V Power FET On Resistance RDS (ON) BOOST 175 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) BOOST 39 V Input Disconnect Switch On Resistance RDS (ON) INBK 210 mΩ Current-Limit Threshold ILIM (BOOST) 1.00 1.10 1.20 A Minimum On Time 50 ns Minimum Off Time 25 ns
Rev. A | Page 4 of 27 Parameter Symbol Min Typ Max Unit Test Conditions/Comments INVERTING REGULATOR Reference Voltage VREF 1.60 V Reference Voltage Accuracy −0.5 +0.5 % TJ = 25°C Feedback Voltage VREF − VFB2 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C Feedback Bias Current IFB2 0.1 µA Overvoltage Protection Threshold VOV2 0.74 V At FB2 pin after soft start has completed Load Regulation ∆(VREF − VFB2)/ ILOAD2 0.0004 %/mA ILOAD21 = 5 mA to 75 mA Line Regulation ∆(VREF − VFB2)/ VPVIN2 0.003 %/V VPVIN2 = 2.85 V to 14.5 V, ILOAD21 = 15 mA EA Transconductance gM2 270 300 330 µA/V Power FET On Resistance RDS (ON) INVERTER 350 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) INVERTER 39 V Current-Limit Threshold ILIM (INVERTER) 600 660 720 mA Minimum On Time 60 ns Minimum Off Time 50 ns SOFT START Soft Start Timer for Boost and Inverting Regulators tSS 4 ms SS = open 32 ms SS resistor = 50 kΩ to GND Hiccup Time tHICCUP 8 × tSS ms THERMAL SHUTDOWN Threshold TSHDN 150 °C Hysteresis THYS 15 °C 1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
0.3 V or +6 V
Table 4. Thermal Resistance
15 PVIN1
11 FB2
- EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
Figure 2. 20-Lead LFCSP Pin Configuration
- EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
Figure 3. 20-Lead TSSOP Pin Configuration Table 5. Pin Function Descriptions 1 3 INBK Input Disconnect Switch Output for the Boost Regulator. switching frequency, connect the SYNC/FREQ pin to an external clock. VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to AGND. regulator output capacitor and AGND to program the output voltage. soft start time, connect a resistor between the SS pin and AGND. the inverting regulator output. inverting regulator output capacitor and VREF to program the output voltage. 14 16 VREG Internal Regulator Output. Connect a 1.0 μF ce ramic filter capacitor between the VREG pin and AGND. 15 17 PVIN1 Power Input for the Boost Regulator. 16 18 PVINSYS System Power Supply for the ADP5070. 17 19 PVIN2 Power Input for the Inverting Regulator.
Rev. A | Page 7 of 27 Pin No. Mnemonic Description LFCSP TSSOP 18 20 SW2 Switching Node for the Inverting Regulator. 19 1 PGND Power Ground for the Boost and Inverting Regulators. 20 2 SW1 Switching Node for the Boost Regulator. EPAD Exposed Pad. Connect the exposed pad to AGND.
Figure 40. Functional Block Diagram voltage by adjusting the peak inductor current threshold. and the regulators are enabled. peak current consumption and noise. is configured using the SYNC/FREQ pin options shown in Table 6. Table 6. SYNC/FREQ Pin Options but must not be used to supply external circuitr y. circuit from accidental loading.
each regulator to off when the pin is floating. reference level, the regulator is enabled. set to the fastest rate when the SS pin is open. during analog-to-digital converter (ADC) sampling. Figure 41. Switching Node at Various Slew Rate Settings current through the MOSFET switch. and FB2 pins for the boost and inverting regulators. after the soft start period has elapsed. can be implemented via the SEQ pin, as explained in Table 7. Table 7. SEQ Pin Settings To configure the manual enable mode, leave the SEQ pin open. their respective precision enable pins.
The ADP5070 is supported by the ADIsimPower design toolset. request an unpopulated board through the tool. current through the divider is at least 10 times IFB1 or IFB2. VPOS is the positive output voltage. VFB1 is the FB1 reference voltage. RFT1 is the feedback resistor from VPOS to FB1. RFB1 is the feedback resistor from FB1 to AGND. VNEG is the negative output voltage. VFB2 is the FB2 reference voltage. RFT2 is the feedback resistor from VNEG to FB2. RFB2 is the feedback resistor from FB2 to VREF . VREF is the VREF pin reference voltage. Table 8. Recommended Feedback Resistor Values
temperature and dc bias characteristics. CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst-case capacitor temperature coefficient. DCBIASCO is the dc bias derating at the output voltage. Tolerance is the worst-case component tolerance. of the capacitors be evaluated for each application. is suggested as a good balance between performance and size. ripple and improve transient response. ESR capacitor is recommended. The effective capacitance needed for stability is a minimum of 10 µF. Figure 44. Soft Start Behavior
Rev. A | Page 19 of 27 For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VPOS) voltages determine the switch duty cycle (DUTY1) by +−= DIODE1POS DIODE1INPOS1 VV VVVDUTY where VDIODE1 is the forward voltage drop of the Schottky diode (D1). The dc input current in CCM (IIN) can be determined by the following equation: )1( 1 OUT1 IN DUTY II Using the duty cycle (DUTY1) and switching frequency (fSW), determine the on time (tON1) using the following equation: SW ON1 f DUTYt = The inductor ripple current (∆IL1) in steady state is calculated by tVI ON1IN ×=∆ Solve for the inductance value (L1) using the following equation: ON1IN I tVL1 ∆ Assuming an inductor ripple current of 30% of the maximum dc input current results in OUT1 1ON1IN I DUTYtVL1 −××= 3.0 )1( Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When the ADP5070 boost regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. This slope compensation is built in to the ADP5070. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, L MIN1, for the application parameters in the following equation: ×=> 33.0 )1( 27.0 INMIN1 DUTY VLL1 (µH) Table 10 suggests a series of inductors to use with the ADP5070 boost regulator. Inductor Selection for the Inverting Regulator The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 µH to 22 µH are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current close to 30% of the maximum dc current in the inductor typically yields an optimal compromise. For the inductor ripple current in continuous conduction mode (CCM) operation, the input (V IN) and output (VNEG) voltages determine the switch duty cycle (DUTY2) by DIODE2NEGIN DIODE2NEG2 VVV VVDUTY where VDIODE2 is the forward voltage drop of the Schottky diode (D2). The dc current in the inductor in CCM (IL2) can be determined by the following equation: )1( 2 OUT2 DUTY II Using the duty cycle (DUTY2) and switching frequency (fSW), determine the on time (tON2) by the following equation: SW ON2 f DUTYt = The inductor ripple current (∆IL2) in steady state is calculated by tVI ON2IN ×=∆ Solve for the inductance value (L2) by the following equation: ON2IN I tVL2 ∆ Assuming an inductor ripple current of 30% of the maximum dc current in the inductor results in OUT2 2ON2IN I DUTYtVL2 −××= 3.0 )1( Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator.
tool to calculate compensation components. fZ1(RHP) is the right half plane zero frequency. divided by the load current. VPOS is the regulated positive output voltage. GM1 is the error amplifier transconductance gain. ROUT1 is the output impedance of the error amplifier and is 33 MΩ. set by the ADP5070 and is 6.25 A/V . is dominated by the impedance of an output capacitor (COUT1). where fC1 is the crossover frequency. which it operates under in the calculation for RC1. where CC1 is the compensation capacitor value. Figure 45. Compensation Components
undesirable right half plane zero in the regulation feedback loop. fZ2(RHP) is the right half plane zero frequency. divided by the load current. VFB2 is the feedback regulation voltage. VNEG is the regulated negative output voltage. GM2 is the error amplifier transconductance gain. ROUT2 is the output impedance of the error amplifier and is 33 MΩ. set by the ADP5070 and is 6.25 A/V. is dominated by the impedance of the output capacitor, COUT2. where fC2 is the crossover frequency. operates under in the calculation for RC2. where CC2 is the compensation capacitor. Figure 46. Compensation Component
Table 10. Recommended Boost Regulator Components Table 11. Recommended Inverting Regulator Components
generation from a +5 V supply. Figure 48. Super Low Noise ±15 V Generation with Post Regulation by the ADP7142 (+40 V, +200 mA, Low Noise LDO) and ADP7182 (−28 V, −200 mA, Low Noise LDO) Table 12. Recommended LDOs for Super Low Noise Operation
supported in the ADIsimPower toolset. Figure 49. SEPIC Application for +12 V in to ±5 V Output Generation
COMPLIANT TOJEDEC STANDARDS MO-220-WGGD.
0.02 NOM
0.20 REF
0.25 MIN
Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
0.65 BSC
1.20 MAX
Figure 53. 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] registered trademarks are the property of their respective owners.