ADP5056 (Rev. 0)
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- PDF pages: 31
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FEATURES
Wide input voltage range: 2.75 V to 18 V Bias input voltage range: 4.5 V to 18 V Operation up to 150°C junction temperature −0.62% to +0.69% feedback voltage accuracy (−40°C to +125°C junction temperature) Channel 1 and Channel 2: 7 A synchronous buck regulator (9.4 A minimum valley current limit) Channel 1 and Channel 2: 14 A output in parallel operation Channel 3: 3 A synchronous buck regulator (4.2 A minimum valley current limit) 250 kHz to 2500 kHz adjustable switching frequency External compensation for fast load transient response Precision enable pin with 0.615 V accurate reference voltage Programmable power-up and power-down sequence Selective FPWM/PSM mode selection Frequency synchronization input or output Power-good flag for three channels Active output discharge switch UVLO, overcurrent protection, and TSD protection 43-terminal, 5 mm × 5.5 mm LGA package
APPLICATIONS
Field programmable gate array (FPGA) and processor TYPICAL APPLICATION CIRCUIT BST1 SW1 PGND VOUT1 FB1 VREG GND BST2 SW2 PGND VOUT2 FB2 EN1 PVIN1 2.75V TO 18.0V PVIN2 COMP1 COMP2 EN2 VBIAS INT VREG BST3 SW3 PGND C10 VOUT3 FB3 PVIN3 COMP3 EN3 RT CFG1 CFG2 OSC SYNC/MODE (VBIAS = 4.5V TO 18.0V) RAMP1 PWRGD RAMP2 RAMP3 LOGIC GND GND CHANNEL 3 3A BUCK CHANNEL 2 7A BUCK CHANNEL 1 7A BUCK 17270-001 Figure 1. GENERAL DESCRIPTION The ADP5056 combines three high performance buck regulators in a 43-terminal land grid array (LGA) package that meets the demanding performance and board space requirements. The device enables direct connection to high input voltages up to 18 V with no preregulators. All channels integrate both high-side and low-side power metal- oxide semiconductor field effect transistors (MOSFETs) to achieve an efficiency optimized solution. Channel 1 and Channel 2 deliver a programmable output current of 3.5 A or 7 A, or provide a single output with up to 14 A of current in parallel operation. Channel 3 delivers a programmable output current of 1.5 A or 3 A. The switching frequency of the ADP5056 can be programmed or synchronized to an external clock. The ADP5056 contains an enable pin (ENx) on each channel for easy power-up sequencing or adjustable undervoltage lockout (UVLO) threshold. The ADP5056 integrates start-up/shutdown sequence control, forced pulse-width modulation/power saving mode (FPWM/PSM) selection, an output discharge switch, and a power-good signal. The ADP5056 is rated at −40°C to +150°C junction temperature. Note that throughout this data sheet, multifunction pins, such as SYNC/MODE, are referred to either by the entire pin name or by a single function of the pin, for example, SYNC, when only that function is relevant.
Rev. 0 | Page 2 of 31 TABLE OF CONTENTS
REVISION HISTORY
5/2020—Revision 0: Initial Version
Rev. 0 | Page 3 of 31 FUNCTIONAL BLOCK DIAGRAM RT SYNC/MODE DIGITAL DECODER CFG1 CFG2 VBIAS VREG INTERNAL REGULATOR (POR, UVLO) GND GND VREG POWER-ON RESET PWRGD HOUSEKEEPING LOGIC UVLO1 PVIN1 SW1 BST1 VREG VREG PGND CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION EN1 0.615V HICCUP AND LATCH-UP –OCP COMP1 FB1 CLK1 ZERO CROSS CHANNEL 1 – BUCK DUPLICATE CHANNEL 1 CHANNEL 2 – BUCKEN2 COMP2 FB2 PGND PVIN2 SW2 BST2 EA1 CMP1 DUPLICATE CHANNEL 1 CHANNEL 3 – BUCKEN3 COMP3 FB3 PGND PVIN3 SW3 BST3 0.9µA 2.6µA RAMP1 ACS1*ICS ICS 107% × VREF VREF CLK1 100nF 25V RAMP2 RAMP3 ½ × PVIN1 CLK2 CLK3 GND OSCILLATOR SLOPE COMP 93% × VREF DRIVER DRIVER DISCHARGE SWITCH 100nF 25V 17270-002 *ACS1 IS THE CURRENT SENSING AMPLIFIER OF CHANNEL 1. Figure 2.
Rev. 0 | Page 4 of 31 SPECIFICATIONS Input voltage (VIN) = bias input voltage (VBIAS) = 12 V, VREG voltage (VREG) = 4.8 V, TJ = −40°C to +150°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments WIDE INPUT VOLTAGE RANGE VIN 2.75 18 V PVIN1 pin, PVIN2 pin, PVIN3 pin BIAS INPUT VOLTAGE RANGE VBIAS 4.5 18 V VBIAS pin QUIESCENT CURRENT VBIAS pin Operating Quiescent Current IQ(3-BUCKS) 6.2 7.5 mA No switching, all ENx pins high Shutdown Current of Three Channels ISHDN(3-BUCKS) 42 80 µA All ENx pins low UNDERVOLTAGE LOCKOUT Power Input UVLOPVINx PVIN1 pin, PVIN2 pin, PVIN3 pin Rising Threshold VUVLO1-RISING 2.5 2.75 V Falling Threshold VUVLO1-FALLING 2.22 V Hysteresis VHYS1 0.30 V Bias Input Voltage UVLOVBIAS VBIAS pin Rising Threshold VUVLO2-RISING 4.20 4.50 V Falling Threshold VUVLO2-FALLING 3.60 3.80 V Hysteresis VHYS2 0.40 V OSCILLATOR CIRCUIT Switching Frequency fSW 530 600 630 kHz RT = 280 kΩ 1140 1200 1250 kHz RT = 140 kΩ 1700 1800 1900 kHz RT = 94.2 kΩ Switching Frequency Range 250 2500 kHz Synchronization Input Input Clock Range fSYNC 250 2700 kHz Input Clock Pulse Width Minimum On Time tSYNC_MIN_ON 100 ns Minimum Off Time tSYNC_MIN_OFF 100 ns Input Clock High Voltage VH(SYNC) 2.65 V Input Clock Low Voltage VL(SYNC) 1.2 V Synchronization Output Clock Frequency fCLK fSW kHz Positive Pulse Duty Cycle tCLK_PULSE_DUTY 50 % Rise or Fall Time tCLK_RISE_FALL 2 ns High Level Voltage VH(SYNC_OUT) VREG V PRECISION ENABLING EN1 pin, EN2 pin, EN3 pin Enable Voltage Range VEN_RANGE 0 18 V High Level Threshold VTH_H(EN) 0.615 0.67 V Low Level Threshold VTH_L(EN) 0.52 0.575 V Source Current (High Level) ITH_H(EN) 0.48 0.9 1.55 µA Above the rising threshold Source Current (Low Level) ITH_L(EN) 2.0 3.5 6.0 µA Below the falling threshold POWER GOOD Rising High Threshold VPWRGD(RISE_H) 105 % Rising Low Threshold VPWRGD(RISE_L) 95 % Falling High Threshold VPWRGD(FALL_H) 107 % Falling Low Threshold VPWRGD(FALL_L) 93 % Internal Power-Good Hysteresis VPWRGD(HYS) 2 % Falling Delay for PWRGD Pin tPWRGD_FALL_DLY 4 × switching period (tSW) ms Rising Delay for PWRGD Pin1 tPWRGD_RISE_DLY 0 or tSET ms tSET = 2.6 ms when the resistor value on the CFG2 pin (RCFG2) = 0 Ω
Rev. 0 | Page 5 of 31 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Leakage Current for PWRGD Pin IPWRGD_LEAKAGE 0.1 1 µA Output Low Voltage for PWRGD Pin VPWRGD_LOW 10 150 mV PWRGD pin current (IPWRGD) = 1 mA THERMAL SHUTDOWN (TSD) Thermal Shutdown Threshold TSHDN 175 °C Thermal Shutdown Hysteresis THYS 15 °C 1 tSET is the setting time programmed by CFG2. BUCK REGULATOR SPECIFICATIONS VIN = 12 V, VREG = 4.8 V, fSW = 600 kHz for all channels, TJ = −40°C to +150°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments CHANNEL 1 BUCK REGULATOR Continuous Output Current IO 7 Determined by CFG1 pin configuration (see Table 6), CFG1 resistor (RCFG1) = 0 Ω
3.5 Determined by CFG1 pin configuration
(see Table 6), RCFG1 = open FB1 Pin Feedback Voltage 600 mV Feedback Voltage Accuracy VFB1_DEFAULT −0.25 +0.25 % TJ = 25°C Feedback Reference Voltage of Channel 1 (VFB1) = 600 mV Default Feedback Bias Current IFB1 0.1 µA Adjustable voltage SW1 Pin High-Side Power Field Effect Transistor (FET) On Resistance RDSON_HS(1) 25 mΩ Pin to pin measurement Low-Side Power FET On Resistance RDSON_LS(1) 12 mΩ Pin to pin measurement Valley Current-Limit Threshold ITH(ILIM1) 9.4 A Current limit of Channel 1 (ILIM1) = 7 A, TJ = 25°C 4.4 A ILIM1 = 3.5 A, TJ = 25°C Negative Current-Limit Threshold ITH(ILIM1-NEG) −5.0 A Minimum On Time tMIN_ON1 35 55 ns fSW = 250 kHz to 2500 kHz Minimum Off Time tMIN_OFF1 120 150 ns fSW = 250 kHz to 2500 kHz Error Amplifier (EA), COMP1 Pin EA Transconductance gm1 330 350 365 µS Soft Start Soft Start Time tSS1 0.83 × tSET ms tSET = 2.6 ms when RCFG2 = 0 Ω Hiccup Time tHICCUP1 7 × tSET ms Output Capacitor (COUT) Discharge Switch On Resistance RDIS1 85 Ω CHANNEL 2 BUCK REGULATOR Continuous Output Current IO 7 Determined by CFG1 pin configuration (see Table 6), RCFG1 = 0 Ω (see Table 6), RCFG1 = open FB2 Pin Feedback Voltage 600 mV Feedback Voltage Accuracy VFB2_DEFAULT −0.25 +0.25 % TJ = 25°C Feedback Reference Voltage of Channel 2 (VFB2) = 600 mV Default Feedback Bias Current IFB2 0.1 µA Adjustable voltage
Rev. 0 | Page 6 of 31 Parameter Symbol Min Typ Max Unit Test Conditions/Comments SW2 Pin High-Side Power FET On Resistance RDSON_HS(2) 25 mΩ Pin to pin measurement Low-Side Power FET On Resistance RDSON_LS(2) 12 mΩ Pin to pin measurement Valley Current-Limit Threshold ITH(ILIM2) 9.4 A Current limit of Channel 2 (ILIM2) = 7 A, TJ = 25°C 4.4 A ILIM2 = 3.5 A, TJ = 25°C Negative Current-Limit Threshold ITH(ILIM2-NEG) −5.0 A Minimum On Time tMIN_ON2 35 55 ns fSW = 250 kHz to 2500 kHz Minimum Off Time tMIN_OFF2 120 150 ns fSW = 250 kHz to 2500 kHz EA, COMP2 Pin EA Transconductance gm2 330 350 365 µS Soft Start Soft Start Time tSS2 0.83 × tSET ms tSET = 2.6 ms when the RCFG2 = 0 Ω Hiccup Time tHICCUP2 7 × tSET ms COUT Discharge Switch On Resistance RDIS2 85 Ω CHANNEL 1 AND CHANNEL 2 IN PARALLEL OPERATION Continuous Output Current IO 14 Determined by CFG1 pin configuration (see Table 6), RCFG1 = 23.7 kΩ CHANNEL 3 BUCK REGULATOR Continuous Output Current IO 3 Determined by CFG1 pin configuration (see Table 6), RCFG1 = 0 Ω
1.5 Determined by CFG1 pin configuration
(see Table 6) R CFG1 = open FB3 Pin Feedback Voltage 600 mV Feedback Voltage Accuracy VFB3_DEFAULT −0.25 +0.25 % TJ = 25°C Feedback Reference Voltage of Channel 3 (VFB3) = 600 mV Default Feedback Bias Current IFB3 0.1 µA Adjustable voltage SW3 Pin High-Side Power FET On Resistance RDSON_HS(3) 85 mΩ Pin-to-pin measurement Low-Side Power FET On Resistance RDSON_LS(3) 45 mΩ Pin-to-pin measurement Valley Current-Limit Threshold ITH(ILIM3) 4.2 A Current Limit of Channel 3 (ILIM3) = 3 A, TJ = 25°C 2.1 A ILIM3 = 1.5 A, TJ = 25°C Negative Current-Limit Threshold ITH(ILIM3-NEG) −2.5 A Minimum On Time tMIN_ON3 35 55 ns fSW = 250 kHz to 2500 kHz Minimum Off Time tMIN_OFF3 120 150 ns fSW = 250 kHz to 2500 kHz EA, COMP3 Pin EA Transconductance gm3 330 350 365 µS Soft Start Soft Start Time tSS3 0.83 × tSET ms tSET = 2.6 ms when the RCFG2 = 0 Ω Hiccup Time tHICCUP3 7 × tSET ms COUT Discharge Switch On Resistance RDIS3 85 Ω
PCB thermal design is required. heat sink, airflow) technique improves thermal resistance values. Table 4. Thermal Resistance
41 PVIN142 PVIN143 PVIN1
38 SW139 SW140 SW1
35 PGND36 PGND37 PGND
32 SW2
29 PVIN230 PVIN231 PVIN2
33 SW234 SW2
Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1 GND This pin is for internal test purposes. Connect this pin to ground. 2 GND This pin is for internal test purposes. Connect this pin to ground. 3 RAMP1 Slope Compensation Setting for Channel 1. Connect a re sistor from RAMP1 to ground to set the slope compensation. 4 FB1 Feedback Sensing Input for Channel 1. 5 COMP1 Error Amplifier Output for Channel 1. Connect a resist ance and capacitor (RC) network from this pin to ground. 6 RT Frequency Setting. Connect a resistor from RT to ground to program the switching frequency. 7 EN1 Enable Input for Channel 1. ceramic capacitor (X7R or X5R) between this pin to GND. 10 VBIAS Bias Input Voltage Pin to Supply Internal Regulator. as a synchronization output via the CFG1 pin configuration. mode. When this pin is logic low, all channels operate in automatic PWM/PSM mode. 12 BST1 Supply Rail for the High-Side Gate Drive in Channel 1. Place a 0.1 μF capacitor (X7R or X5R) between SW1 and BST1. 13 BST3 Supply Rail for the High-Side Gate Drive in Channel 3. Place a 0.1 μF capacitor (X7R or X5R) between SW3 and BST3. 14 PGND Power Ground for all Channels. 15 SW3 Switching Node Output for Channel 3. 16 PVIN3 Power Input for Channel 3. 17 BST2 Supply Rail for the High-Side Gate Drive in Channel 2. Place a 0.1 μF capacitor (X7R or X5R) between SW2 and BST2. 18 EN3 Enable Input for Channel 3. 19 RAMP3 Slope Compensation Setting for Channel 3. Connect a re sistor from RAMP3 to ground to set the slope compensation. 20 FB3 Feedback Sensing Input for Channel 3. 21 COMP3 Error Amplifier Output for Channel 3. Conn ect an RC network from this pin to ground.
Rev. 0 | Page 9 of 31 Pin No. Mnemonic Description 22 PWRGD Power Good Output for Selective Channels. 23 EN2 Enable Input for Channel 2. 24 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground. 25 FB2 Feedback Sensing Input for Channel 2. 26 RAMP2 Slope Compensation Setting for Channel 2. Connect a resistor from RAMP2 to ground to set the slope compensation. 27 CFG2 System Configuration Pin 2. Connect one resistor from this pin to ground to program the tSET timer, fast transient mode, and sequence mode. 28 CFG1 System Configuration Pin 1. Connect one resistor from this pin to ground to program the current limit, parallel operation, and clock output settings. 29 PVIN2 Power Input for Channel 2. 30 PVIN2 Power Input for Channel 2. 31 PVIN2 Power Input for Channel 2. 32 SW2 Switching Node Output for Channel 2. 33 SW2 Switching Node Output for Channel 2. 34 SW2 Switching Node Output for Channel 2. 35 PGND Power Ground for all Channels. 36 PGND Power Ground for all Channels. 37 PGND Power Ground for all Channels. 38 SW1 Switching Node Output for Channel 1. 39 SW1 Switching Node Output for Channel 1. 40 SW1 Switching Node Output for Channel 1. 41 PVIN1 Power Input for Channel 1. 42 PVIN1 Power Input for Channel 1. 43 PVIN1 Power Input for Channel 1.
to meet demanding performance and board space requirements. the emulated current ramp voltage crosses the COMPx voltage. side MOSFET stays on for the remainder of the cycle. *ACS IS THE CURRENT SENSING AMPLIFIER. Figure 28. FlexMode™ PWM Control Architecture capacitor supplies all the output current. FPWM mode of operation under light load conditions. enter continuous conduction mode (CCM). in discontinuous mode (DCM). pin is 600 mV for each channel. ground in Channel 1 and Channel 2.
second ADP5056 device is 0° (see Figure 36). Figure 36. Waveforms of Two ADP5056 Devices Operating in internal registers and cannot be changed in operation. different functionality in the CFG1 pin. different functionality in the CFG2 pin. Table 6. Configuration by the CFG1 Pin
23.7 SYNC/MODE Interleaved
32.4 SYNC/MODE In phase
39.2 Clock output 7 A 7 A 3 A
127 Clock output Interleaved
511 Clock output In phase
Table 7. Configuration by the CFG2 Pin
corresponding channel enables when the ENx pin is high. rising threshold), a soft start initiates for each enabled channel. the output voltage on three channels. signal fails, the PWRGD pin goes low with no delay. Figure 44. Power-Good Delay, VIN = 12 V, VOUT = 1.0 V, fSW = 600 kHz, FPWM start is initiated for each enabled channel.
Rev. 0 | Page 21 of 31 APPLICATIONS INFORMATION PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE The output voltage of the ADP5056 is externally set by a resistive voltage divider from the output voltage to the FBx pin. To limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in the divider is not too large. A value of less than 50 kΩ is recommended. The equation for the output voltage setting is VOUT = VREF × (1 + (RTOP/RBOT)) where: VOUT is the output voltage. VREF is the feedback reference voltage, 0.6 V for Channel 1 to Channel 3. RTOP is the feedback resistor from VOUT to FBx. RBOT is the feedback resistor from FBx to ground. VOLTAGE CONVERSION LIMITATIONS For a given input voltage, upper and lower limitations on the output voltage exist due to the minimum on time and the minimum off time. The minimum on time limits the output voltage for a given input voltage and switching frequency. The minimum on time for Channel 1 to Channel 3 is 50 ns (maximum). In FPWM mode, Channel 1 and Channel 2 can skip the switching pulses to maintain the output regulation when the minimum on time limit is exceeded. Careful selection of switching frequency is required to avoid this condition. To calculate the minimum output voltage in CCM for a given input voltage and switching frequency, use the following equation: V OUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) × IOUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN (1) where: VOUT_MIN is the minimum output voltage. VIN is the input voltage. tMIN_ON is the minimum on time. fSW is the switching frequency. RDSON_HS is the on resistance of the high-side MOSFET. RDSON_LS is the on resistance of the low-side MOSFET. IOUT_MIN is the minimum output current. RL is the resistance of the output inductor. The maximum output voltage for a given input voltage and switching frequency is limited by the minimum off time and the maximum duty cycle. The maximum output voltage for a given input voltage and switching frequency can be calculated using the following equation: VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) × IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2) where: tMIN_OFF is the minimum off time. IOUT_MAX is the maximum output current. As shown in Equation 1 and Equation 2, reducing the switching frequency eases the minimum on time and off time limitations. CURRENT-LIMIT SETTING The ADP5056 has two selectable current-limit thresholds for Channel 1, Channel 2, and Channel 3. Ensure that the selected current-limit value is larger than the peak current of the inductor (IPEAK) for the current-limit configuration for all channels. SOFT START SETTING The buck regulators in the ADP5056 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. To set the soft start time to a value of 2.2 ms or 17.3 ms, connect a resistor from the CFG2 pin to ground (see the Soft Start section). INDUCTOR SELECTION The inductor value is determined by the switching frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor value yields faster transient response but may degrade efficiency due to the larger inductor ripple current. Using a large inductor value yields a smaller ripple current and improved efficiency but results in slower transient response. Thus, a trade-off must be made between transient response and efficiency. As a guideline, the inductor peak-to-peak ripple current, ΔIL, is typically set to a value from 30% to 40% of the maximum load current. Use the following equation to calculate the inductor value: L = ((VIN − VOUT) × D)/(ΔIL × fSW) where: VOUT is the output voltage. D is the duty cycle (D = VOUT/VIN). ΔIL is the inductor ripple current. The ADP5056 has internal slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is greater than 50%. Use the following equation to calculate the peak inductor current: I PEAK = IOUT + (ΔIL/2) The saturation current of the inductor must be larger than the peak inductor current. For ferrite core inductors with a fast saturation characteristic, ensure that the saturation current rating
buck regulator to prevent the inductor from becoming saturated. Table 8. Recommended Inductors
1 Visit the Coilcraft, Toko, and Wurth manufacturer websites for more
information about the recommended series inductors. undershoot of the output voltage. KUV is a factor (typically set to 2). ΔVOUT_UV is the allowable undershoot on the output voltage. the output capacitor, causing an overshoot of the output voltage. KOV is a factor (typically set to 2). ΔVOUT_OV is the allowable overshoot on the output voltage. ΔIL is the inductor ripple current. ΔVOUT_RIPPLE is the allowable output voltage ripple. RESR is the equivalent series resistance of the output capacitor. Circuits section for suggested capacitor values. higher voltage rating may be required.
the input voltage, as shown in Figure 30. VIN_RISING is the VIN turn on voltage. VIN_FALLING is the VIN turn off voltage. RBOT_EN is the resistor from ENx to ground. RTOP_EN is the resistor from VIN to ENx. RAMPX) from the RAMPx pin to ground. s is the domain in the control to output transfer function. AVI = 12.5 A/V for Channel 1 and Channel 2, 5 A/V for Channel 3. where COUT is the output capacitance. simplified peak current mode control small signal circuit. Figure 45. Simplified Peak Current Mode Control Small Signal Circuit The compensation components, RC and CC, contribute a zero. RC and the optional CCP contribute an optional pole.
- Determine the cross frequency (fC). Generally, fC is between
- Calculate RC using the following equation:
- Place the compensation zero at the domain pole (fP).
- CCP is optional. CCP can be used to cancel the zero caused
Rev. 0 | Page 24 of 31 POWER DISSIPATION The total power dissipation in the ADP5056 simplifies to PD = PBUCK1 + PBUCK2 + PBUCK3 where: PD is the power dissipation in the package. PBUCK1 is the power dissipation of Channel 1. PBUCK2 is the power dissipation of Channel 2. PBUCK3 is the power dissipation of Channel 3. Buck Regulator Power Dissipation The power dissipation (PLOSS) for each buck regulator includes power switch conduction losses (PCOND), switching losses (PSW), and transition losses (PTRAN). Other sources of power dissipation exist, but these sources are generally less significant at the high output currents of the application thermal limit. Use the following equation to estimate the power dissipation of the buck regulator: P LOSS = PCOND + PSW + PTRAN Power Switch Conduction Loss (PCOND) Power switch conduction losses are caused by the flow of output current through both the high-side and low-side power switches. Each of these switches has internal on resistance (R DSON). Use the following equation to estimate the power switch conduction loss: PCOND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2 where: RDSON_HS is the on resistance of the high-side MOSFET. RDSON_LS is the on resistance of the low-side MOSFET. Switching Loss (PSW) Switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. Use the following equation to estimate the switching loss: P SW = (CGATE_HS + CGATE_LS) × VIN2 × fSW where: CGATE_HS is the gate capacitance of the high-side MOSFET. CGATE_LS is the gate capacitance of the low-side MOSFET. Transition Loss (PTRAN) Transition losses occur because the high-side MOSFET cannot turn on or off instantaneously. During a switch node transition, the MOSFET provides all the inductor current. The source to drain voltage of the MOSFET is half the input voltage, resulting in power loss. Transition losses increase with both load and input voltage and occur twice for each switching cycle. Use the following equation to estimate the transition loss: P TRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW where: tR is the rise time of the switch node. tF is the fall time of the switch node. JUNCTION TEMPERATURE The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: T R = θJA × PD where: θJA is the thermal resistance from the junction of the die to the ambient temperature of the package (see Table 4). An important factor to consider is that the thermal resistance value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of copper, as specified in the JEDEC standard, whereas real-world applications may use PCBs with different dimensions and a different number of layers. It is important to maximize the amount of copper used to remove heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. Connect Pin 35, Pin 36, and Pin 37 to the ground plane with the maximum number of vias.
Figure 46. Typical Application, 12 V Input, fSW = 600 kHz, VOUT1 = 1.0 V, VOUT2 = 1.3 V, VOUT3 = 1.8 V, Sequence Mode
Figure 47. Typical Application, 12 V Input, fSW = 600 kHz, VOUT1 = 1.0 V, VOUT2 = 3.3 V, VOUT3 = 1.5 V
Figure 48. Typical Channel 1/Channel 2 Interleaved Parallel Application, 12 V Input, fSW = 600 kHz, VOUT1 = 1.0 V, VOUT3 = 1.5 V
procedures and the external components required for Channel 1. Table 9 lists the design requirements for this example. Table 9. Example Design Requirements for Channel 1 channels (Channel 1 to Channel 3). higher conversion efficiency due to lower switching losses. based on the trade-off between efficiency and solution size. Voltage Conversion Limitations section). where VREF is 0.6 V for Channel 1. values: RTOP = 10 kΩ, RBOT = 10 kΩ. D is the duty cycle (D = VOUT/VIN = 0.1). value is 0.8 μH. Therefore, ΔIL is 2.25 A. The calculated peak current for the inductor is 8.125 A. The rms current of the inductor is approximately 7.03 A. peak current limit, typically 11.65 A, for reliable operation.
the EMI and electromagnetic compatibility (EMC) performance. bootstrap capacitor near to the IC. and PGND to other power planes. pins and the output capacitors. component side to improve thermal dissipation. Place the frequency setting resistor near to the RT pin. traces and the switch node to avoid noise pickup. Figure 50. Typical PCB Layout for the ADP5056
Rev. 0 | Page 31 of 31 OUTLINE DIMENSIONS A 6 2 04-20-2020-B PKG-005467 5.15 5.00 4.85 5.65 5.50 5.35 TOP VIEW SIDE VIEW 0.30 0.25 0.20 0.30 0.25 0.20 0.70 0.65 0.60 0.35 0.30 0.25 0.913 0.863 0.813 0.213 0.183 0.153
0.68 REF
0.50 BSC 0.38 BSC 0.115 BSC 0.115 BSC 0.10 BSC 1.13 BSC 0.10 BSC 3.35 BSC 0.50 BSC 0.215 BSC4.00 REF B C D E F G H J K 75 4 3 1 DETAIL A DETAIL A 0.90 0.85 0.80 0.65 0.60 0.55 0.55 0.50 0.45 0.375 BSC 0.375 BSC 0.30 BSC 0.30 0.25 0.20 Figure 51. 43-Terminal Land Grid Array [LGA] (CC-43-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADP5056ACCZ-R7 −40°C to +150°C 43-Termin al Land Grid Array [LGA] CC-43-1 ADP5056-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17270-5/20(0)