ADP5043ACPZ-1-R7

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Micro PMU with 800 mA Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset Data Sheet ADP5043 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Input voltage range: 2.3 V to 5.5 V One 800 mA buck regulator One 300 mA LDO 20-lead, 4 mm × 4 mm LFCSP package Initial regulator accuracy: ±1% Overcurrent and thermal protection Soft start Undervoltage lockout Open-drain processor reset with threshold monitoring ±1.5% threshold accuracy over the full temperate range Guaranteed reset output valid to V CC = 1 V Dual watchdog for secure systems Watchdog 1 controls reset Watchdog 2 controls reset and regulators power cycle Buck regulator key specifications Current-mode topology for excellent transient response

3 MHz operating frequency

Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PFM/PSM modes 100% duty cycle low dropout mode LDO key specifications Low V IN from 1.7 V to 5.5 V Stable with1 μF ceramic output capacitors High PSRR, 60 dB up to 1 kHz/10 kHz Low output noise Low dropout voltage: 150 mV at 300 mA load −40°C to +125°C junction temperature range GENERAL DESCRIPTION The ADP5043 combines one high performance buck regulator and one low dropout (LDO) regulator in a small 20-lead LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes board space. The MODE pin selects the buck’s mode of operation. When set to logic high, the buck regulator operates in forced PWM mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM) improving the light-load efficiency. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5043 LDO extend the battery life of portable devices. The LDO maintains a power supply rejection of greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator is activated by a high level on the respective enable pin. The ADP5043 is available with factory programmable default output voltages and can be set to a wide range of options. The ADP5043 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. The ADP5043 also provides power-on reset signals. An on-chip dual watchdog timer can reset the microprocessor or power cycle the system (Watchdog 2) if it fails to strobe within a preset timeout period. HIGH LEVEL BLOCK DIAGRAM VIN WD1 MODE SELECTION FPWM PSM/PWM MODE SW VOUT1 PGND 10µF 1µH EN_BK BUCK EN_LDO LDO VIN1 EN1 VIN2 EN2 1µF VOUT2 GND GND 4.7µF ON OFF ON OFF NC VIN1 = 2.3V TO 5.5V AVIN RFILT 30Ω VIN2 = 1.7V TO 5.5V MR 1µF MICROPROCESSOR SUPERVISOR WSTAT WMOD WDI1 WDI2 nRSTO NC AGND AVIN AVIN ADP5043 VOUT1 @ 800mA VOUT2 @ 300mA 09682-001 Figure 1.

Rev. C | Page 2 of 30 TABLE OF CONTENTS Input and Output Capacitor, Recommended Specifications .. 6

REVISION HISTORY

9/2019—Rev. B to Rev. C 5/2018—Rev. A to Rev. B 10/2011—Rev. 0 to Rev. A 4/2011—Revision 0: Initial Version

Rev. C | Page 3 of 30 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = (VOUT1 + 0.5 V) or 2.3 V , whichever is greater, AVIN, VIN1 ≥ VIN2, TA = 25°C, unless otherwise noted. Regulators are enabled. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit AVIN UNDERVOLTAGE LOCKOUT UVLOAVIN T J = −40°C to +125°C Input Voltage Rising UVLOAVINRISE Option A 2.25 V Option B 3.9 V Input Voltage Falling UVLOAVINFALL Option A 1.95 V Option B 3.1 V SHUTDOWN CURRENT IGND-SD ENx = GND 0.1 μA ENx = GND, TJ = −40°C to +125°C 2 μA Thermal Shutdown Threshold TSSD T J rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 20 °C ENx, WDIx, MODE, WMOD, MR INPUTS Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V Input Leakage Current (WMOD Excluded) V I-LEAKAGE ENx = AVIN or GND 0.05 μA ENx = AVIN or GND, TJ = −40°C to +125°C 1 μA WMOD Input Leakage Current VI-LKG-WMOD VWMOD = 3.6 V, T J = −40°C to +125°C 50 μA OPEN-DRAIN OUTPUTS nRSTO, WSTAT Output Voltage VOL AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA 30 mV Open-Drain Reset Output Leakage Current 1 μA SUPERVISORY SPECIFICATIONS AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY Supply Current (Supervisory Circuit Only) 45 55 μA AVIN = 5.5 V, EN1 = EN2 = VIN1 43 52 μA AVIN = 3.6 V, EN1 = EN2 = VIN1 RESET THRESHOLD ACCURACY VTH − 0.8% V TH V TH + 0.8% V T A = 25°C, sensed on VOUTx V TH − 1.5% V TH V TH + 1.5% V T J = −40°C to +125°C, sensed on VOUTx RESET THRESHOLD TO OUTPUT DELAY GLITCH IMMUNITY (tUOD) 50 125 400 μs V TH = VOUT − 50 mV RESET TIMEOUT PERIOD WATCHDOG1 (tRP1) Option A 24 30 36 ms Option B 160 200 240 ms RESET TIMEOUT PERIOD WATCHDOG2 (tRP2) 3.5 5 7 ms VCC TO RESET DELAY (tRD) 150 μs VIN1 falling at 1 mV/μs REGULATORS SEQUENCING DELAY (tD1, tD2) 2 ms WATCHDOG INPUTS Watchdog 1 Timeout Period (tWD1) Option A 81.6 102 122.4 ms Option B 1.28 1.6 1.92 sec

Rev. C | Page 4 of 30 Parameter Min Typ Max Unit Test Conditions/Comments Watchdog 2 Timeout Period (tWD2) Option A 6 7.5 9 sec Option B Watchdog 2 disabled Option C 3.2 4 4.8 min Option D 6.4 8 9.6 min Option E 11.2 16 19.2 min Option F 25.6 32 38.4 min Option G 51.2 64 76.8 min Option H 102.4 128 153.8 min Watchdog 2 Power Off Period (tPOFF) Option A 210 ms Option B 400 ms WDI1 Pulse Width 80 ns V IL = 0.4 V, VIH = 1.2 V WDI2 Pulse Width 8 μs V IL = 0.4 V, VIH = 1.2 V Watchdog Status Timeout Period (tWDCLEAR) 11.2 sec WDI1 Input Current (Source) 8 15 20 μA V WDI1 = VCC, time average WDI1 Input Current (Sink) −30 −25 −14 μA V WDI1 = 0, time average WDI2 Internal Pull-Down 45 kΩ MANUAL RESET INPUT MR Input Pulse Width 1 μs MR Glitch Rejection 220 ns MR Pull-Up Resistance 25 52 80 kΩ MR to Reset Delay 280 ns V CC = 5 V

Rev. C | Page 5 of 30 BUCK SPECIFICATIONS AVIN, VIN1 = 3.6 V , VOUT1 = 1.8 V , TJ = −40°C to +125°C for minimum/maximum specifications, L = 1 μH, COUT = 10 μF, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 3. Parameter Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Voltage Range (VIN1) 2.3 5.5 V OUTPUT CHARACTERISTICS Output Voltage Accuracy PWM mode, ILOAD = 100 mA −1 +1 % PSM mode −2 +2 % VIN1 = 2.3 V to 5.5 V, PWM mode, ILOAD = 1 mA to 800 mA −3 +3 % PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA INPUT CURRENT CHARACTERISTICS DC Operating Current ILOAD = 0 mA, device not switching 21 35 μA Shutdown Current ENx = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA SW CHARACTERISTICS SW On Resistance PFET 180 240 mΩ PFET, AVIN = VIN1 = 5 V 140 190 mΩ NFET 170 235 mΩ NFET, AVIN = VIN1 = 5 V 150 210 mΩ Current Limit PFET switch peak current limit 1100 1360 1600 mA ACTIVE PULL-DOWN EN1 = 0 V 75 Ω OSCILLATOR FREQUENCY 2.5 3.0 3.5 MHz START-UP TIME 250 μs 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO SPECIFICATIONS AVIN = 3.6 V , VIN2 = (VOUT2 + 0.2 V) or 2.3 V , whichever is greater; AVIN, VIN1 ≥ VIN2; IOUT = 10 mA; CIN = COUT = 1 μF; TA = 25°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN2 T J = −40°C to +125°C 1.7 5.5 V OPERATING SUPPLY CURRENT (per LDO) I GND I OUT = 0 μA, VOUT = 3.3 V 15 μA IOUT = 0 μA, VOUT = 3.3 V, TJ = −40°C to +125°C 50 μA IOUT = 10 mA 67 μA IOUT = 10 mA, TJ = −40°C to +125°C 105 μA IOUT = 200 mA 100 μA IOUT = 200 mA, TJ = −40°C to +125°C 245 μA FIXED OUTPUT VOLTAGE ACCURACY V OUT2 I OUT = 10 mA −1 +1 % 100 μA < IOUT < 300 mA −2 +2 % VIN2 = (VOUT2 + 0.5 V) to 5.5 V 100 μA < IOUT < 300 mA −3 +3 % VIN2 = (VOUT2 + 0.5 V) to 5.5 V TJ = −40°C to +125°C

Rev. C | Page 6 of 30 Parameter Symbol Test Conditions/Comments Min Typ Max Unit REGULATION Line Regulation ∆VOUT2/∆VIN2 VIN2= (VOUT2 + 0.5 V) to 5.5 V −0.03 +0.03 %/ V IOUT2 = 1 mA TJ = −40°C to +125°C Load Regulation1 ∆V OUT2/∆IOUT2 IOUT2 = 1 mA to 200 mA 0.002 %/mA IOUT2 = 1 mA to 200 mA 0.0075 %/mA TJ = −40°C to +125°C DROPOUT VOLTAGE2 V DROPOUT VOUT2 = 3.3 V IOUT2 = 10 mA 4 mV IOUT2 = 10 mA, TJ = −40°C to +125°C 5 mV IOUT2 = 200 mA 60 mV IOUT2 = 200 mA, TJ = −40°C to +125°C 100 mV ACTIVE PULL-DOWN RPDLDO EN2 = 0 V 600 Ω START-UP TIME TSTART-UP VOUT2 = 3.3 V 85 μs CURRENT-LIMIT THRESHOLD3 I LIMIT T J = −40°C to +125°C 335 470 mA OUTPUT NOISE OUTLDONOISE 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 123 μV rms

10 Hz to 100 kHz, VIN2 = 5 V,

VOUT2 = 2.8 V 110 μV rms VOUT2 = 1.5 V 59 μV rms POWER SUPPLY REJECTION RATIO PSRR 1 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, IOUT = 100 mA 66 dB 100 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, IOUT = 100 mA 57 dB 1 MHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, I OUT = 100 mA 60 dB 1 Based on an end-point calculation using 1 mA and 100 mA loads. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CAPACITANCE (BUCK)1 C MIN1 T J = −40°C to +125°C 7 40 μF MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO) C MIN2 T J = −40°C to +125°C 0.70 μF CAPACITOR ESR RESR T J = −40°C to +125°C 0.001 1 Ω 1 The minimum output capacitance should be greater than 4.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. 2 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.

Manufacturing Guide for the Lead Frame Chip Scale (LFCSP). PCB thermal design is required. Table 7. Thermal Resistance

1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

THE PIN SHOULD BE LEFT FLOATING.

15 WSTAT

11 VOUT1

Figure 2. Pin Configuration Table 8. Pin Function Descriptions 1, 14 NC No Connect. Do not connect to this pin. The pin should be left floating. 2 VOUT2 LDO Output Voltage and Sensing Input. 3 VIN2 LDO Input Supply (1.7 V to 5.5 V). 4 EN2 Enable LDO. EN2 = high: turn on the LDO; EN2 = low: turn off the LDO. 5 nRSTO Open-Drain Reset Output, Active Low. 6 AVIN Regulators Housekeeping and Supe rvisory Input Supply (2.3 V to 5.5 V). 7 VIN1 Buck Input Supply (2.3 V to 5.5 V). 9 PGND Dedicated Power Ground for Buck Regulator. 10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. 12 WDI2 Watchdog 2 (Long Timeout) Refresh Input from Processor. This pin can be disabled only by a factory option. 13, 16 GND Connect to the ground plane. Watchdog 2 timeout. Auto cleared after one second. regulator operates in power save mode (PSM) at light load and in constant PWM at higher load. three-state condition applied on WDI1. WMOD has an internal 200 kΩ pull-down resistor connected to AGND. 19 WDI1 Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled. 20 MR Manual Reset Input, Active Low. EPAD Exposed Pad. The exposed pad should be connected to analog ground (AGND).

Figure 33. LDO Ground Current vs. Output Load, VOUT2 = 2.8 V Figure 34. LDO Ground Current vs. Input Voltage, Across Output Load,

1 VOUT

Figure 35. LDO Response to Load Transient, IOUT2 from 1 mA to 80 mA, Figure 36. LDO Response to Line Transient, VIN2 = 4.5 V to 5.5 V, VOUT2 = 3.3 V Figure 37. LDO Output Current Capability vs. Output Voltage Figure 38. LDO Output Noise vs. Load Current, Across Input and

Figure 43. Functional Block Diagram reset, and a push-button reset input (nRSTO). due to the discharged output capacitors. level, the switching regulator operates in auto PWM/PSM mode. when the load current is above the power saving current threshold. function of the current load and the output capacitor value.

the thermal shutdown circuit turns off the buck and LDO. operation, poor circuit board design, or high ambient temperature. supply drops to 3.65 V typical. logic level low turns off a regulator. Table 9. ADP5043 Regulators Sequencing enters an idle mode, which improves conversion efficiency. across the inductor, causing the inductor current to decrease. stays below the PSM current threshold. efficiency over all load currents. source is connected to the input of the converter.

current from reversing direction and flowing out of the load. allowing overshoot on the output voltage. battery-operated portable equipment. provided from the buck regulator. with a small 1 μF ceramic input and output capacitors. better noise performance than the buck regulator. reducing the current flowing to the output. vision by controlling the reset input of the microprocessor. and corrected with a dual-watchdog timer. adequate in most situations. up connected to the nRSTO output. Figure 44. Reset Timing Diagram complete list of the reset thresholds available for the ADP5043. rail supplying a processor to restart the processor operations.

a reset. WSTAT is an open-drain output. Table 10 shows the possible watchdog decoded statuses. Table 10. Watchdog Status Decoding Figure 47. ADP5043 State Flow

VRIPPLE is allowable peak-to-peak output voltage ripple in volts. IRIPPLE is the inductor ripple current in Amperes. fSW is the converter switching frequency in Hertz. Table 12. Suggested 10 μF Capacitors large load variation when working in PSM mode (see Figure 50). Figure 50. Processor System Power Management with PSM/PWM Control capacitor, a low ESR input capacitor is recommended. maximum of 10 μF . Suggested capacitors are shown in Table 13. Table 13. Suggested 4.7 μF Capacitors LDO to large changes in load current. required, increase the input capacitor to match it. Table 14. Suggested 1.0 μF Capacitors

Rev. C | Page 25 of 30 POWER DISSIPATION/THERMAL CONSIDERATIONS The ADP5043 is a highly efficient micro PMU, and in most cases the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125°C). When the junction temperature exceeds 150°C, the ADP5043 turns off all the regulators, allowing the device to cool down. Once the die temperature falls below 135°C, the ADP5043 resumes normal operation. This section provides guidelines to calculate the power dissi- pated in the device and to make sure the ADP5043 operates below the maximum allowable junction temperature. The efficiency for each regulator on the ADP5043 is given by 100%OUT IN P P (1) where: η is efficiency. PIN is the input power. POUT is the output power. Power loss is given by PLOSS = PIN − POUT (2a) or PLOSS = POUT (1-η)/η (2b) The power dissipation of the supervisory function is small and can be neglected. Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. The measurements should be performed at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor, and from this use Equation 3 to calculate the power dissipation in the ADP5043 buck regulator. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, while the power lost on the LDO is calculated using Equation 12. Once the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and thus calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDO to find the total dissipated power. It should be noted that the buck efficiency curves are typical values and may not be provided for all possible combinations of V IN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDO provided by Equation 12. Buck Regulator Power Dissipation The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: P DBUCK is the power dissipation on the ADP5043 buck regulator. PL is the inductor power losses. The inductor losses are external to the device and they don’t have any effect on the die temperature. The inductor losses are estimated (without core losses) by LRMSOUT1L DCRI P  2 ) ( (4) where IOUT1(RMS) is the RMS load current of the buck regulator. /12 + 1) ( rII OUT1RMSOUT1   (5) where r is the inductor ripple current. r ≈ VOUT1 × (1-D)/(IOUT1 × L × fSW) (6) D = VOUT1/VIN1 (7) fSW is switching frequency. L is inductance. DCRL is the inductor series resistance. D is duty cycle. The ADP5043 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application will be. Equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. P DBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the PMOSFET and the NMOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by: PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT12 (9) For the ADP5043, at 125°C junction temperature and VIN =

3.6 V , R

DSON-P is approximately 0.2 Ω, and RDSON-N is approximately 0.16 Ω. At VIN = 2.3 V , these values change to 0.31 Ω and 0.21 Ω respectively, and at VIN = 5.5 V , the values are 0.16 Ω and 0.14 Ω.

Rev. C | Page 26 of 30 Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by: P SW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the PMOSFET gate capacitance. CGATE-N is the NMOSFET gate capacitance. For the ADP5043, the total of (CGATE-P + CGATE-N) is ~150 pF. The transition losses occur because the PMOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by: PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW . For the ADP5043, the rise and fall times of SW are in the order of 5 ns. If the equations and parameters previously given are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout, so a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation The power loss of a LDO regulator is given by: PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (12) where: I LOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. I GND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. Junction Temperature The total power dissipation in the ADP5043 simplifies to: PD = {[PDBUCK + PDLDO1 + PDLDO2]} (13) In cases where the board temperature (TA) is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula: TJ = TA + (PD × θJA) (14) The typical θJA value for the 20-lead, 4 mm × 4 mm LFCSP is 38°C/W , see Table 7. An important factor to consider is that θJA is based on a four- layer 4 inch × 3 inch, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device, and copper exposed to air dissipates heat better than copper used in the inner layers. The thermal pad (TP) should be connected to the ground plane with several vias as shown in Figure 55. If the case temperature can be measured, the junction temperature is calculated by: T J = TC + (PD × θJC) (15) where: TC is the case temperature. θJC is the junction-to-case thermal resistance provided in Table 7. When designing an application for a particular ambient temperature range, calculate the expected ADP5043 power dissipation (PD) due to the losses of all channels by using Equation 8 to Equation 13. From this power calculation, the junction temperature, T J, can be estimated using Equation 14. The reliable operation of the buck regulator and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5043 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) is highly affected by increasing the junction temperature. Additional information about product reliability can be found in the Analog Devices, Inc., Reliability Handbook.

Figure 56. Application Diagram

Table 16. Reset Voltage Threshold Options1 1 When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V). Table 17. Reset Timeout Options Table 18. Watchdog 1 Timer Options Table 19. Watchdog 2 Timer Options

001 Watchdog 2 disabled

Table 20. Power-Off Timing Options Table 21. Reset Sensing Options

00 VOUT1 pin

01 Reserved

10 VOUT2 pin

11 AVIN 1 pin

1 When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V). Table 22. BUCK and LDO Output Voltage Options

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

Figure 57. 20-Lead, Lead Frame Chip Scale Package [LFCSP] Considerations section for more information. registered trademarks are the property of their respective owners.