ADP5034

ADP5034 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

Dual 3 MHz, 1200 mA Buck Regulators with Two 300 mA LDOs Data Sheet ADP5034 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Main input voltage range: 2.3 V to 5.5 V Two 1200 mA buck regulators and two 300 mA LDOs 24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package Regulator accuracy: ±1.8% Factory programmable or external adjustable VOUTx

3 MHz buck operation with forced PWM and auto PWM/PSM

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V LDO1/LDO2: output voltage range from 0.8 V to 5.2 V LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices GENERAL DESCRIPTION The ADP5034 combines two high performance buck regulators and two low dropout (LDO) regulators. It is available in either a 24-lead 4 mm × 4 mm LFCSP or a 28-lead TSSOP package. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set to high, the buck regulators operate in forced PWM mode. When the MODE pin is set to low, the buck regulators operate in PWM mode when the load is above a pre- defined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. Table 1. Family Models

2 EN pins

high as 10 kHz while operating with a low headroom voltage. of preset values in the fixed voltage version.

Rev. E | Page 2 of 28 TABLE OF CONTENTS Input and Output Capacitor, Recommended Specifications .. 6

Rev. E | Page 3 of 28

REVISION HISTORY

5/13—Rev. D to Rev. E 1/13—Rev. C to Rev. D 11/12—Rev. B to Rev. C 7/12—Rev. A to Rev. B Changes to Output Voltage Accuracy Parameter, Added TSSOP SW On Resistance Specifications, Changes to Voltage Feedback Minimum and Maximum Values, and Changes to Active Pull- Changes to Output Voltage Accuracy Parameter and Voltage Feedback Minimum and Maximum Values in Table 3; Changes Added Thermal Resistance Values for TSSOP Package, Table 6 .. 7 10/11—Rev. 0 to Rev. A Change to Table 1, Low UVLO Input Voltage Falling Parameter, Change to Table 2, Output Voltage Accuracy Parameter, Test Change to Table 2, Line Regulation Parameter, Symbols Change to Table 2, Load Regulation Parameter, Symbols Changes to Table 2, Reversed the R PFET and RNFET Symbols for the SW On Resistance Parameter and Changes to Typ and Max Changes to Table 3, Output Accuracy Parameter, Test Changes to Table 3, Line Regulation Parameter, Symbols Change to Table 3, Changes to Dropout Voltage Parameter and Change to Table 4, BUCK1, BUCK2 Output Capacitor Moved Power Dissipation and Thermal Considerations Change to V Changes to Input and Output Capacitor Properties Section .... 21 6/11—Revision 0: Initial Version

Rev. E | Page 4 of 28 SPECIFICATIONS GENERAL SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VAVIN, VIN1, VIN2 2.3 5.5 V THERMAL SHUTDOWN Threshold TSSD TJ rising 150 °C Hysteresis TSSD-HYS 20 °C START-UP TIME1 BUCK1, LDO1, LDO2 tSTART1 250 µs BUCK2 tSTART2 300 µs EN1, EN2, EN3, EN4, MODE INPUTS Input Logic High VIH 1.1 V Input Logic Low VIL 0.4 V Input Leakage Current VI-LEAKAGE 0.05 1 µA INPUT CURRENT All Channels Enabled ISTBY-NOSW No load, no buck switching 108 175 µA All Channels Disabled ISHUTDOWN TJ = −40°C to +85°C 0.3 1 µA VIN1 UNDERVOLTAGE LOCKOUT High UVLO Input Voltage Rising UVLOVIN1RISE 3.9 V High UVLO Input Voltage Falling UVLOV IN1 FAL L 3.1 V Low UVLO Input Voltage Rising UVLOVIN1RISE 2.275 V Low UVLO Input Voltage Falling UVLOVIN1FAL L 1.95 V 1 Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 from 0 V to VAVIN to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.

Rev. E | Page 5 of 28 BUCK1 AND BUCK2 SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔVOUT1/VOUT1, ΔVOUT2/VOUT2 PWM mode; ILOAD1 = ILOAD2 = 0 mA −1.8 +1.8 % Line Regulation (ΔVOUT1/VOUT1)/ΔVIN1, (ΔVOUT2/VOUT2)/ΔVIN2 PWM mode −0.05 %/V Load Regulation (ΔVOUT1/VOUT1)/ΔIOUT1, (ΔVOUT2/VOUT2)/ΔIOUT2 ILOAD = 0 mA to 1200 mA, PWM mode −0.1 %/A VOLTAGE FEEDBACK VFB1, VFB2 Models with adjustable outputs 0.491 0.5 0.509 V OPERATING SUPPLY CURRENT MODE = ground BUCK1 Only IIN ILOAD1 = 0 mA, device not switching, all other channels disabled 44 μA BUCK2 Only IIN ILOAD2 = 0 mA, device not switching, all other channels disabled 55 μA BUCK1 and BUCK2 IIN ILOAD1 = ILOAD2 = 0 mA, device not switching, LDO channels disabled 67 μA PSM CURRENT THRESHOLD IPSM PSM to PWM operation 100 mA SW CHARACTERISTICS SW On Resistance RNFET VIN1 = VIN2 = 3.6 V; LFCSP package 155 240 mΩ RPFET VIN1 = VIN2 = 3.6 V; LFCSP package 205 310 mΩ RNFET VIN1 = VIN2 = 5.5 V; LFCSP package 137 204 mΩ RPFET VIN1 = VIN2 = 5.5 V; LFCSP package 162 243 mΩ RNFET VIN1 = VIN2 = 3.6 V; TSSOP package 156 237 mΩ RPFET VIN1 = VIN2 = 3.6 V; TSSOP package 194 270 mΩ RNFET VIN1 = VIN2 = 5.5 V; TSSOP package 137 202 mΩ RPFET VIN1 = VIN2 = 5.5 V; TSSOP package 154 212 mΩ Current Limit ILIMIT1, ILIMIT2 pFET switch peak current limit 1600 1950 2300 mA ACTIVE PULL-DOWN RPDWN-B VIN1= VIN2 = 3.6 V; Channel disabled 75 Ω OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO1 AND LDO2 SPECIFICATIONS 1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN3, VIN4 1.7 5.5 V OPERATING SUPPLY CURRENT Bias Current per LDO2 IVIN3BIAS/IVIN4BIAS IOUT3 = IOUT4 = 0 µA 10 30 µA IOUT3 = IOUT4 = 10 mA 60 100 µA IOUT3 = IOUT4 = 300 mA 165 245 µA Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2, VIN3, and VIN4 LDO1 or LDO2 Only IOUT3 = IOUT4 = 0 µA, all other channels disabled 53 µA LDO1 and LDO2 Only IOUT3 = IOUT4 = 0 µA, buck channels disabled 74 µA

Rev. E | Page 6 of 28 Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔVOUT3/VOUT3, ΔVOUT4/VOUT4 100 µA < IOUT3 < 300 mA, 100 µA < IOUT4 < 300 mA −1.8 +1.8 % Line Regulation (ΔVOUT3/VOUT3)/ΔVIN3, (ΔVOUT4/VOUT4)/ΔVIN4 IOUT3 = IOUT4 = 1 mA −0.03 +0.03 %/V Load Regulation3 (ΔVOUT3/VOUT3)/ΔIOUT3, (ΔVOUT4/VOUT4)/ΔIOUT4 IOUT3 = IOUT4 = 1 mA to 300 mA 0.001 0.003 %/mA VOLTAGE FEEDBACK VFB3, VFB4 0.491 0.5 0.509 V DROPOUT VOL TAGE4 VDROPOUT VOUT3 = VOUT4 = 5.2 V, IOUT3 = IOUT4 = 300 mA 50 mV VOUT3 = VOUT4 = 3.3 V, IOUT3 = IOUT4 = 300 mA 75 140 mV VOUT3 = VOUT4 = 2.5 V, IOUT3 = IOUT4 = 300 mA 100 mV VOUT3 = VOUT4 = 1.8 V, IOUT3 = IOUT4 = 300 mA 180 mV CURRENT-LIMIT THRESHOLD5 ILIMIT3, ILIMIT4 335 600 mA ACTIVE PULL-DOWN RPDWN-L Channel disabled 600 Ω OUTPUT NOISE Regulator LDO1 NOISELDO1 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 100 µV rms Regulator LDO2 NOISELDO2 10 Hz to 100 kHz, VIN4 = 5 V, VOUT4 = 1.2 V 60 µV rms POWER SUPPLY REJECTION RATIO PSRR Regulator LDO1 10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 60 dB 100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 62 dB 1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 63 dB Regulator LDO2 10 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 54 dB 100 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 57 dB 1 MHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 64 dB 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 This is the input current into VIN3/VIN4, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS TA = −40°C to +125°C, unless otherwise specified. Table 5. Parameter Symbol Min Typ Max Unit NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings CMIN1, CMIN2 4.7 40 µF BUCK1, BUCK2 Output Capacitor Ratings CMIN1, CMIN2 10 40 µF LDO1, LDO21 Input and Output Capacitor Ratings CMIN3, CMIN4 1.0 µF CAPACITOR ESR RESR 0.001 1 Ω 1 The minimum input and output capacitance should be greater than 1.0 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.

Dissipation and Thermal Considerations section. soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance

Figure 46. Functional Block Diagram function of the current load and the output capacitor value. bucks operate synchronized to each other. values (see the Ordering Guide section). current due to the charging of the output capacitors.

Figure 48. BUCK1 External Output Voltage Setting enters an idle mode, which improves conversion efficiency. output voltage by adjusting the peak inductor current threshold. is below the PSM current threshold. low sets the bucks to operate in auto PSM/PWM. the PSM current threshold for entry to and exit from the PSM. switching frequency when both bucks are in PWM mode. BUCK1 pFET starts conducting. discharge, preventing a runaway of output current. connected to the input of the converter. current from reversing direction and flowing out of the load.

allowing overshoot on the output voltage. pull-downs during regulator activation and deactivation. and FB3 must be connected to the top of the capacitor on VOUT3. Figure 49. LDO1 External Output Voltage Setting used in applications where noise performance is critical.

large load variation when working in PSM mode (see Figure 51). capacitor, a low ESR capacitor is recommended. Table 10. Suggested 10 μF Capacitors Table 11. Suggested 4.7 μF Capacitors Table 12. Suggested 1.0 μF Capacitors Figure 51. Processor System Power Management with PSM/PWM Control

Rev. E | Page 23 of 28 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5034 is a highly efficient µPMU, and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maxi- mum loading condition, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5034 turns off all the regulators, allowing the device to cool down. When the die temperature falls below 130°C, the ADP5034 resumes normal operation. This section provides guidelines to calculate the power dissi- pated in the device and ensure that the ADP5034 operates below the maximum allowable junction temperature. The efficiency for each regulator on the ADP5034 is given by 100%×= IN OUT P Pη (1) where: η is the efficiency. PIN is the input power. POUT is the output power. Power loss is given by PLOSS = PIN − POUT (2a) or PLOSS = POUT (1− η)/η (2b) Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor and, from this, use Equation 3 to calculate the power dissipation in the ADP5034 buck converter. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on each LDO can be calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the two LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of V IN, VOUT, and IO U T. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDO provided by Equation 12. BUCK REGULATOR POWER DISSIPATION The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on one of the ADP5034 buck regulators. PL is the inductor power losses. The inductor losses are external to the device, and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL ≈ IOUT1(RMS)2 × DCRL (4) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. 12+1)(1 rII OUT1RMSOUT ×= (5) where r is the normalized inductor ripple current. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6) where: L is the inductance. fSW is the switching frequency. D is the duty cycle. D = VOUT1/VIN1 (7) ADP5034 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transi- tion losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. P DBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the P-MOSFET and the N-MOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT1(RMS)2 (9) where RDSON-P is approximately 0.2 Ω, and RDSON-N is approxi- mately 0.16 Ω at 25°C junction temperature and VIN1 = VIN2 = 3.6 V. At VIN1 = VIN2 = 2.3 V , these values change to 0.31 Ω and 0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V , the values are 0.16 Ω and 0.14 Ω, respectively.

Rev. E | Page 24 of 28 Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance. For the ADP5034, the total of (CGATE-P + CGATE-N) is approximately 150 pF . The transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near V OUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW . For the ADP5034, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimat- ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation The power loss of a LDO regulator is given by PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. The total power dissipation in the ADP5034 simplifies to PD = PDBUCK1 + PDBUCK2 + PDLDO1 + PDLDO2 (13) JUNCTION TEMPERATURE In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) (14) Refer to Table 7 for the thermal resistance values of the LFCSP and TSSOP packages. A very important factor to consider is that θJA is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. The exposed pad should be connected to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by T J = TC + (PD × θJC) (15) where TC is the case temperature and θJC is the junction-to-case thermal resistance provided in Table 7. When designing an application for a particular ambient temperature range, calculate the expected ADP5034 power dissipation (P D) due to the losses of all channels by using the Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. The reliable operation of the converter and the two LDO regulators can be achieved only if the estimated die junction temperature of the ADP5034 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) are highly affected by increas- ing the junction temperature. Additional information about product reliability can be found from the ADI Reliability Handbook, which can be found at www.analog.com/reliability_handbook.

Rev. E | Page 25 of 28 PCB LAYOUT GUIDELINES Poor layout can affect ADP5034 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to the UG-271 and UG-439 user guide.

• Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side to help with thermal dissipation.
• Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
• Connect VIN1, VIN2, and AVIN together close to the IC using short tracks.

COMPLIANT TOJEDEC STANDARDS MO-220-WGGD-8.

0.20 REF

0.25 MIN

0.05 MAX

0.02 NOM

Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

1.20 MAX

Figure 55. 28-Lead Thin Shrink Small Outline with Exposed Pad Package [TSSOP_EP]

Rev. E | Page 28 of 28 ORDERING GUIDE Model1 Temperature Range Output Voltage (V)2 UVLO3 Active Pull- Down4 Package Description Package Option ADP5034ACPZ-R2 −40°C to +125°C Adjustable Low Enabled on buck channels only 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-24-10 ADP5034ACPZ-R7 −40°C to +125°C Adjustable Low Enabled on buck channels only 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-24-10 ADP5034ACPZ-1-R7 −40°C to +125°C VOUT1 = 1.2 V VOUT2 = 3.3 V VOUT3 = 2.8 V VOUT4 = 1.8 V Low Enabled on buck channels only 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-24-10 ADP5034ACPZ-2-R7 −40°C to +125°C Adjustable High Enabled on buck channels only 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-24-10 ADP5034ACPZ-3-R7 −40°C to +125°C Adjustable High Enabled on all channels 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-24-10 ADP5034AREZ −40°C to +125°C Adjustable Low Enabled on all channels 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 ADP5034AREZ-R7 −40°C to +125°C Adjustable Low Enabled on all channels 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 ADP5034AREZ-1 −40°C to +125°C Adjustable High Enabled on all channels 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 ADP5034AREZ-1-R7 −40°C to +125°C Adjustable High Enabled on all channels 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 ADP5034-1-EVALZ Evaluation Board for ADP5034ACPZ-R7 ADP5034RE-EVALZ Evaluation Board for ADP5034AREZ-R7 1 Z = RoHS Compliant Part. 2 For additional options, contact a local sales or distribution representative. Additional options available are: 3 UVLO: low or high. 4 BUCK1, BUCK2, both LDO1 and LDO2: Active pull-down resistor is programmable to be either enabled or disabled. ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09703-0-5/13(E)