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Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO ADP5022 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

FEATURES

Input voltage range: 2.4 V to 5.5 V Tiny 16-ball, 2 mm × 2 mm WLCSP package Overcurrent and thermal protection Soft start Factory programmable undervoltage lockout on VDDA system supply of either 2.2 V or 3.9 V Factory programmable default output voltages for all 3 channels Buck1 and Buck2 key specifications Current mode architecture for excellent transient response

3 MHz operating frequency

Uses tiny multilayer inductors and capacitors Forced PWM and auto PWM/PSM modes Out-of-phase operation for reduced input filtering 100% duty cycle low dropout mode 24 μA typical quiescent current per channel, no switching LDO key specifications Stable with 1 μF ceramic output capacitors High PSRR 60 dB up to 10 KHz Low output noise 65 μV rms output noise at VOUT3 = 3.3 V Low dropout voltage: 150 mV @ 150 mA load 11 μA typical ground current at no load

APPLICATIONS

Multivoltage power for processors, ASICS, FPGAs, and RF chipsets GENERAL DESCRIPTION The ADP5022 is a micro power management unit (micro PMU) that combines two high performance buck regulators and a low dropout regulator (LDO) in a tiny 16-ball 2.08 mm × 2.08 mm WLCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space required. When the MODE pin is set high, the buck reg- ulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators automatically switch operating modes, depending on the load current level. At higher output loads, the buck regulators operate in PWM mode. When the load current falls below a predefined threshold, the regulators operate in power save mode (PSM), improving the light-load efficiency. The two bucks operate out-of-phase to reduce the input capacitor requirement and noise. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5022 LDO extends the battery life of portable devices. The LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator in the ADP5022 has a dedicated, independent enable pin. A high voltage level applied to the enable pin activates the respective regulator. The default output voltages are factory programmable and can be set to a wide range of options. 4.7µF 4.7µF VIN1 VIN3 EN1 ON OFF PWM PWM/PSM VIN = 2.4V TO 5.5V SW1 VOUT1 PGND1 MODE 10µF 1µF VOUT1 @ 600mA 1µH 1µH EN_BK1 BUCK1 MODE 1µF VIN2 EN2 VDDA ON OFF SW2 VOUT2 VOUT3 AGND PGND2 10µF VOUT2 @ 600mA EN_BK2 BUCK2 MODE EN3 ON OFF VOUT3 @ 150mA EN_LDO1 LDO1 ADP5022 08253-001 INDUCTOR INDUCTOR L1 COUT_1 COUT_2 COUT_3 C4C3 08253-0614.7mm 5.0mm Figure 1. Typical Applications Circuit Figure 2. Typical PCB Layout

Rev. A | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

11/09—Revision A: Initial Version

Rev. A | Page 3 of 28 SPECIFICATIONS VDDA = VIN1 = VIN2 = 3.6 V , VIN3 = (VOUT3 + 0.5 V) or 2.4 V , whichever is greater, VIN3 ≤ VIN1, TJ = −40°C to +125°C, unless otherwise noted.1 Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE System and Buck Input Supplies Voltage Range VDDA, VIN1, and VIN2 Low UVLO level models 2.4 5.5 V High UVLO level models 4.5 5.5 V LDO Input Supply Voltage Range VIN3 2.3 5.5 V SHUTDOWN CURRENT I GND-SD EN1 = EN2 = EN3 = GND 0.5 μA EN1 = EN2 = EN3 = GND TJ = −40°C to +85°C 2 μA THERMAL SHUTDOWN Thermal Shutdown Threshold TSDTH T J rising 150 °C Thermal Shutdown Hysteresis TSDHYS 20 °C EN1, EN2, EN3, MODE INPUTS EN1, EN2, EN3, MODE Input Logic High VIH VDDA = VIN1 = VIN2 1.2 V EN1, EN2, EN3, MODE Input Logic Low VIL VDDA = VIN1 = VIN2 0.4 V EN1, EN2, EN3, MODE Input Leakage Current VI-LEAKAGE Pin at (VDDA = VIN1 = VIN2) or GND 0.05 1 μA STANDBY CURRENT All Channels Enabled, No Load ISTBY 80 μA All Channels Enabled, No Load, No Buck Switching ISTBY-NOSW 59 85 μA VIN3 UNDERVOLTAGE LOCKOUT Input Voltage Rising UVLOVIN3RISE 2.20 V Input Voltage Falling UVLOVIN3FALL 1.45 V VDDA UNDERVOLTAGE LOCKOUT Input Voltage Rising UVLOVDDARISE High UVLO level (factory programmed) 4.15 V Low UVLO level (factory programmed) 2.35 V Input Voltage Falling UVLOVDDAFALL High UVLO level (factory programmed) 3.40 V Low UVLO level (factory programmed) 2.00 V 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control.

Rev. A | Page 4 of 28 BUCK1 AND BUCK2 SPECIFICATIONS VDDA = VIN1 = VIN2 = 3.6 V , VIN3 = (VOUT3 + 0.5 V) or 2.4 V , whichever is greater, VIN3 ≤ VIN1, TJ = −40°C to +125°C, unless otherwise noted.1 Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OPERATING SUPPLY CURRENT Buck1 Only IGND1 ILOAD1 = 0 mA, device not switching, EN1 = VDDA, EN2 = EN3 = GND 24 μA Buck2 Only IGND2 ILOAD2 = 0 mA, device not switching, EN2 = VDDA, EN1 = EN3 = GND 32 μA Buck1 and Buck2 Only IGND1-2 ILOAD1 = ILOAD1 = 0 mA, device not switch- ing, EN1 = EN2 = VDDA, EN3 = GND 48 64 μA OUTPUT VOLTAGE ACCURACY VOUT1, VOUT2 PWM mode, VIN1 = VIN2 = 2.4 V to 5.5 V, ILOAD1 = ILOAD2 = 0 mA − 600 mA −3 +3 % POWER SAVE MODE TO PWM CURRENT THRESHOLD IPSM-PWM 105 mA PWM TO POWER SAVE MODE CURRENT THRESHOLD IPWM-PSM 100 mA SW CHARACTERISTICS, BUCK1 and BUCK2 PFET On Resistance RPFET Typical at VIN1 = VIN2 = 3.6 V 165 275 mΩ Typical at VIN1 = VIN2 = 5.0 V 125 mΩ NFET On Resistance RNFET Typical at VIN1 = VIN2 = 3.6 V 125 220 mΩ Typical at VIN1 = VIN2 = 5.0 V 100 mΩ Current Limit ILIMIT1, ILIMIT2 PFET switch peak current limit 750 950 1050 mA OSCILLATOR FREQUENCY FSW 2.5 3.0 3.5 MHz START-UP TIME2 From Shutdown State TSTARTUP12-SD 250 μs 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. 2 Start-up time is defined as the time from a rising edge on EN1/EN2 to VOUT1/VOUT2 reaching 90% of their nominal value.

Rev. A | Page 5 of 28 LDO SPECIFICATIONS VDDA = VIN1 = VIN2 = 3.6 V , VIN3 = (VOUT3 + 0.5 V) or 2.3 V , whichever is greater, VIN3 ≤ VIN1, IOUT3 = 10 mA; CIN3 = COUT3 = 1 μF, TJ = −40°C to +125°C, unless otherwise noted.1 Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OPERATING SUPPLY CURRENT2 I VIN3-GND IOUT3 = 0 μA 11 21 μA IOUT3 = 10 mA 16 29 μA IOUT3 = 150 mA 31 43 μA OUTPUT VOLTAGE ACCURACY VOUT3 100 μA < IOUT3 < 150 mA, VIN3 = (VOUT3 + 0.5 V) to 5.5 V −2 +2 % REGULATION Line Regulation ∆VOUT3/∆VIN3 VIN3 = (VOUT3 + 0.5 V) to 5.5 V, IOUT = 1 mA −0.03 +0.03 %/ V Load Regulation3 ∆VOUT3/∆I OUT3 I OUT3 = 1 mA to 150 mA 0.002 0.0075 %/mA DROPOUT VOLTAGE4 V DROPOUT VOUT3 = 3.0 V, IOUT3 = 10 mA 7 mV VOUT3 = 3.0 V, IOUT3 = 150 mA 110 150 mV START-UP TIME5 From Shutdown State TSTARTUP3-SD 200 μs CURRENT-LIMIT THRESHOLD6 I LIMIT3 160 240 350 mA OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 65 μV rms 10 Hz to 100 kHz, VIN3= 5 V, VOUT3 = 2.4 V 52 μV rms 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.2 V 40 μV rms POWER SUPPLY REJECTION RATIO PSRR 10 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 60 dB 10 kHz, VIN3 = 5 V, VOUT3 = 2.3 V 66 dB 10 kHz, VIN3 = 5 V, VOUT3 = 1.2 V 70 dB 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. 2 LDO operating supply current is the current drawn from VIN3 to AGND when the LDO is enabled. Whenever any regulator channel is enabled, current is drawn from VIN1 to AGND. This current is 8 μA typical and is included in the IGND1, IGND2, and IGND1-2 specifications. 3 Based on an end-point calculation using 1 mA and 150 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 5 Start-up time is defined as the time between the rising edge of EN3 to VOUT3 being at 90% of its nominal value. 6 Current-limit threshold is defined as the current at which VOUT3 drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.

Wafer Level Chip Scale Package. soldered on a circuit board. Table 5. Thermal Resistance

Figure 3. Pin Configuration Table 6. Pin Function Descriptions A1 VOUT3 LDO Output Voltage and Sensing Input. A3 VIN3 LDO Input Supply (VIN3 ≤ VIN1 = VIN2 = VDDA). A4 VDDA Supply Input for the Housekeeping Block and UVLO Sensing. B1 VIN1 Buck1 Input Supply (VIN1 = VIN2 = VDDA). B2 EN1 Buck1 Activation. Set EN1 = high: turn on Buck1. Set EN1 = low: turn off Buck1. B3 EN2 Buck2 Activation. Set EN2 = high: turn on Buck2. Set EN2 = low: turn off Buck2. B4 VIN2 Buck2 Input Supply (VIN2 = VIN1 = VDDA). C1 SW1 Buck1 Switching Node. C2 EN3 LDO Activation. Set EN3 = high: turn on LDO. EN3 = low: turn off LDO. C3 MODE Buck1/Buck2 Operating Mode: MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. C4 SW2 Buck2 Switching Node. D1 PGND1 Dedicated Power Ground for Buck1. D2 VOUT1 Buck1 Output Voltage Sensing Input. D3 VOUT2 Buck2 Output Voltage Sensing Input. D4 PGND2 Dedicated Power Ground for Buck2.

Figure 48. Functional Block Diagram a small power management solution. transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other.

Rev. A | Page 17 of 28 Thermal Protection In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off the converters and the LDO. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included so that when thermal shutdown occurs, the bucks and LDO do not return to opera- tion until the on-chip temperature drops below 130°C. When coming out of thermal shutdown, soft start is initiated. Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on VDDA drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on VDDA rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for USB applications. For these models, the device hits the turn-off threshold when the input supply drops to 3.65 V typical. Enable/Shutdown When all three enable pins are held low, the device is in shutdown mode, and the input current remains below 2 μA. BUCK SECTION The two bucks use a fixed frequency and high speed current mode architecture. The bucks operate with an input voltage of 2.4 V to 5.5 V . Control Scheme The bucks operate with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency but shift to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM Mode In PWM mode, the bucks operate at a fixed frequency of 3 MHz set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Power Save Mode (PSM) The bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enter power save mode, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. PSM Current Threshold The PSM current threshold is set to 100 mA. The bucks employ a scheme that enables this current to remain accurately con- trolled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. The PSM current threshold is optimized for excellent efficiency over all load currents. Oscillator/Phasing of Inductor Switching The ADP5022 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ADP5022 ensures that when both bucks are in PWM mode, they operate out-of-phase, whereby the Buck2 PFET starts conducting exactly half a clock period after the Buck1 PFET starts conducting.

Rev. A | Page 18 of 28 Enable/Shutdown The bucks start operation with soft start when the EN1 or EN2 pin is toggled from logic low to logic high. Pulling the EN1 or EN2 pin low disables that channel. Short-Circuit Protection The bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possi- bility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. Soft Start The bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Current Limit Each buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a drop in input voltage or with an increase in load current, the buck may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. Maintaining regulation is dependent on the input voltage, load current, and output voltage. This can be calculated from the following equation: V IN(MIN) = VOUT(MAX) + ILOAD(MAX) × (RDS(on)MAX + RL) where: VOUT(MAX) is the nominal output voltage plus the maximum tolerance. ILOAD(MAX) is the maximum load current plus inductor ripple current. R DS(on)MAX is the maximum P-channel switch RDS(on). RL is the DC resistance of the inductor. LDO SECTION The LDO is a low quiescent current, low dropout linear regulator and provides up to 150 mA of output current. Drawing a low 30 μA quiescent current (typical) at full load makes the LDO ideal for battery-operated portable equipment. The LDO operates with an input voltage of 2.3 V to 5.5 V . It also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with just a small 1 μF ceramic input and output capacitor. Internally, the LDO consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is con- trolled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, reducing the current flowing to the output. LDO Undervoltage Lockout The ADP5022 integrates an undervoltage lockout function on the VIN3 input voltage, which ensures that the LDO output drive is disabled whenever VIN3 is below a threshold of approximately 2.0 V . Where the ADP5022 is configured to supply VIN3 from either VOUT1 or VOUT2, this ensures that the LDO powers up safely in this cascaded configuration.

Table 8. Suggested 10 μF Capacitors when working in PSM mode, see Figure 50. Figure 50. Processor System Power Management with PSM/PWM Control capacitor, a low ESR capacitor is recommended. Table 9. Suggested 4.7 μF Capacitors or less is recommended to ensure stability of the ADP5022. required, increase the input capacitor to match it. Table 10. Suggested 1.0 μF Capacitors

component tolerance, and voltage. poor temperature and dc bias characteristics. CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. ture range and is not a function of package or voltage rating. Substituting these values into the following equation. temperature and tolerance at the chosen output voltage. behavior of the capacitors are evaluated for each application. Figure 51. Capacitance vs. Voltage Characteristic

Rev. A | Page 22 of 28 PCB LAYOUT GUIDELINES Poor layout can affect ADP5022 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines:

  • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas.
  • Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference.
  • Maximize the size of ground metal on the component side to help with thermal dissipation.
  • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.

0.04 NOM

Figure 57. 16-Ball Wafer Level Chip Scale Package [WLCSP]

Rev. A | Page 26 of 28 NOTES

Rev. A | Page 27 of 28 NOTES

Rev. A | Page 28 of 28 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D08253-0-11/09(A)