ADP5003

ADP5003 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 29

Technical content

Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Low noise, dc power supply system ►High efficiency buck for first stage conversion ►High PSRR, low noise LDO regulator to remove switching ripple ►Adaptive LDO regulator headroom control option for optimal efficiency and PSRR across full load range ►3 A, low noise, buck regulator ►Wide input voltage range: 4.2 V to 15 V ►Programmable output voltage range: 0.6 V to 5.0 V ►0.3 MHz to 2.5 MHz internal oscillator ►0.3 MHz to 2.5 MHz SYNC frequency range ►3 A, low noise, NFET LDO regulator (active filter) ►Wide input voltage range: 0.65 V to 5 V ►Programmable output voltage range: 0.6 V to 3.3 V ►Differential point of load remote sensing ►3 µV rms output noise (independent of output voltage) ►PSRR > 50 dB (to 100 kHz) with 400 mV headroom at 3 A ►Ultrafast transient response ►Power-good output ►Precision enable inputs for both the buck regulator and LDO ►−40°C to +125°C operating junction temperature range ►32-lead, 5 mm × 5 mm, LFCSP

APPLICATIONS

►Low noise power for high speed analog-to-digital converter (ADC) and digital-to-analog converter (DAC) designs ►Powering RF transceivers and clocking ICs FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADP5003 integrates a high voltage buck regulator and an ultralow noise low dropout (LDO) regulator in a small, 5 mm × 5 mm, 32-lead LFCSP package to provide highly efficient and quiet regulated supplies. The buck regulator is optimized to operate at high output currents up to 3 A. The LDO is capable of a maximum output current of 3 A and operates efficiently with low headroom voltage while maintaining high power supply rejection. The ADP5003 can operate in one of two modes. Adaptive mode allows the LDO to operate with an optimized headroom by adjusting the buck output voltage internally in response to the LDO load current. Alternatively, the ADP5003 can operate in independent mode, where both regulators operate separately from each other, and where the output voltages are programmed using resistor dividers. The LDO regulator output can be accurately controlled at the point of load (POL) using remote sensing that compensates for the printed circuit board (PCB) trace impedance while delivering high output currents. Each regulator is activated via a dedicated precision enable input. The buck switching frequency can be synchronized to an external signal, or programmed with an external resistor. Safety features in the ADP5003 include thermal shutdown (TSD), input undervoltage lockout (UVLO) and independent current limits for each regulator. The ADP5003 is rated for a −40°C to +125°C operating junction temperature range.

analog.com Rev. B | 2 of 29 Adaptive Headroom Controller Specifications....5 Setting the Switching Frequency for the Setting the Output Voltage for the Buck Selecting the Inductor for the Buck Regulator..21 Selecting the Output Capacitor for the Buck Designing the Compensation Network for Selecting the Input Capacitor for the Buck Setting the Switching Frequency for the Buck Regulator Using Adaptive Headroom Setting the Output Voltage for the LDO Regulator Using Adaptive Headroom Selecting the Inductor for the Buck Regulator Using Adaptive Headroom Selecting the Output Capacitors for the Buck Regulator Using Adaptive Headroom Designing the Compensation Network for the Buck Regulator Using Adaptive Selecting the Input Capacitor for the Buck Regulator Using Adaptive Headroom Recommended External Components for

REVISION HISTORY

8/2022—Rev. A to Rev. B Changes to Designing the Compensation Network for the Buck Regulator Using Adaptive Headroom

analog.com Rev. B | 3 of 29 VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT VOLTAGE RANGE VPVIN1, VPVINSYS 4.2 15 V VPVIN2 0.65 5 V THERMAL SHUTDOWN Threshold TSD 155 °C TJ rising Hysteresis TSD-HYS 15 °C SYNC INPUT Input Logic High VIH 1.1 V Low VIL 0.4 V Input Leakage Current VI-LEAKAGE 1 µA ADAPTIVE MODE INPUT (VSET1) Input Rising Threshold VADPR 2.5 V Input Hysteresis VADPH 16 mV PRECISION ENABLING High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V EN1, EN2 Pull-Down Resistance RENPD 1.5 MΩ INPUT CURRENT Both Channels Enabled ISTBY-NOSW 0.5 1 mA No load, not switching Both Channels Disabled ISHUTDOWN 5 10 µA TJ = −40°C to +125°C REFOUT CHARACTERISTICS Output Voltage VREFOUT 2.0 V Accuracy −0.5 +0.5 % VREG AND VREG_LDO CHARACTERISTICS Output Voltage VREG, VREG_LDO 5 V Accuracy −2 +2 % Current Limit1 10 mA POWER-GOOD PIN (PWRGD) Power Good Threshold PWRGDF 80 85 90 % Applies to VOUT1 and VFB2P to VFB2N Hysteresis PWRGDFH 2.5 % Output Voltage Level VOL 25 50 mV PWRGD pin sink current = 1 mA Deglitch Time tPWRGDD 60 µs PVINSYS UNDERVOLTAGE LOCKOUT (UVLO) Input Voltage Rising UVLOPVINSYSRISE 4.2 V Falling UVLOPVINSYSFALL3.9 V 1 Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground. BUCK REGULATOR SPECIFICATIONS VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.

analog.com Rev. B | 4 of 29 Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS Programmable Output Voltage Range1 VPVOUT1 0.6 5.0 V Buck Regulator Gain ABUCK 2.5 VPVOUT1/VVSET1 Error Amplifier Transconductance gm1 509 600 661 µS Buck Output Voltage Accuracy2 −1 +1 % VOUT1 load current (ILOAD1) = 10 mA Regulation Line (ΔVPVOUT1/VPVOUT1)/ΔVPVIN1 0.004 %/V ILOAD1 = 10 mA Load (ΔVPVOUT1/VPVOUT1)/ΔILOAD1 0.04 %/A 0 mA ≤ ILOAD1 ≤ 3 A, VPVIN1 = 12 V Total Output Voltage Accuracy ±1.5 % 4.2 V ≤ VPVIN1 ≤ 15 V, 1 mA ≤ ILOAD1 ≤ 3 A OPERATING SUPPLY CURRENT IIN 3.8 mA ILOAD1 = 0 mA, LDO disabled, buck switching SW1 CHARACTERISTICS SW1 On Resistance RPFET 130 200 mΩ VPVIN1 = 15 V (PVIN1 to SW1) RNFET 60 100 mΩ VPVIN1 = 15 V (SW1 to PGND1) Current Limit Threshold ILIMIT1 3.5 A Negative channel field effect transistor (NFET) switch valley current limit −1 A Negative current limit Slew Rate SLEWSW1 1.6 V/ns VPVIN1 = 15 V, ILOAD1 = 1 A Minimum On Time3 tMIN_ON 35 ns Minimum Off Time tMIN_OFF 100 128 ns BUCK REGULATOR ACTIVE PULL DOWNRPDWN-B 90 Ω Channel disabled BUCK REGULATOR SOFT START (SS)tSSBUCK 2 ms HICCUP TIME tHICCUP 33 ms VSETx ADJUSTABLE INPUT BIAS CURRENTIVSET1, IVSET2 10 150 nA OSCILLATOR Internal Switching Frequency 1 fSW1 2.25 2.5 2.75 MHz RRT ≤ 71.2 kΩ Internal Switching Frequency 2 fSW2 0.26 0.3 0.34 MHz RRT = 600 kΩ SYNC Frequency Range fSYNC 0.3 2.5 MHz Minimum Pulse Width Positive 20 ns Negative 10 ns 1 The switching frequency, minimum on time, and minimum off time may limit the output voltage range. 2 The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error. 3 The minimum on time indicates the minimum high-side turn on time to ensure fixed frequency switching. LDO SPECIFICATIONS VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, LDO headroom voltage (VHR) = 300 mV, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS Programmable Output Voltage Range1 VLDO 0.6 3.3 V VVFB2P-VFB2N LDO Gain ALDO 1.65 VLDO/VVSET2 Output Voltage Accuracy2 −1 +1 % VOUT2 load current (ILOAD2) = 150 mA Regulation

analog.com Rev. B | 5 of 29 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Line (ΔVLDO/VLDO)/ΔVPVIN2 0.007 %/V (VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V, ILOAD2 = 100 mA Load (ΔVLDO/VLDO)/ΔILOAD2 0.08 %/A 10 mA ≤ ILOAD2 ≤ 3 A Total Output Voltage Accuracy ±1.5 % (VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V, 10 mA ≤ ILOAD2 ≤ 3 A OPERATING SUPPLY CURRENT IGND 1.8 2.5 mA ILOAD2 = 0 μA 2.3 mA ILOAD2 = 3 A MINIMUM VOLTAGE REQUIREMENTS ILOAD2 = 3 A PVINSYS to PVOUT23 VPVINSYS-PVOUT2 1.5 V VREG_LDO to PVOUT24 VVREG_LDO-PVOUT2 1.35 V Required to drive NFET Dropout5 VDROPOUT 100 mV CURRENT-LIMIT THRESHOLD6 ILIMIT2 3.1 4.5 A LDO SOFT START (SS) TIME tSSLDO 400 µs LDO ACTIVE PULL-DOWN RPDWNLDO 300 Ω Channel disabled OUTPUT NOISE NPVOUT2 3 µV rms 10 Hz to 100 kHz, ILOAD2 = 1 A LDO POWER SUPPLY REJECTION RATIOPSRRLDO VPVIN2 = VPVOUT2 + 0.3 V, ILOAD2 = 1A VPVOUT2 = 1.3 V 87 dB 1 kHz 82 dB 10 kHz 61 dB 100 kHz 38 dB 1000 kHz VPVOUT2 = 3.3 V 89 dB 1 kHz 83 dB 10 kHz 61 dB 100 kHz 37 dB 1000 kHz 1 Limited by minimum PVINSYS to PVOUT2 and VREG_LDO to PVOUT2 voltage. 2 The LDO output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error. 3 PVINSYS must be higher than PVOUT2 by at least VPVINSYS-PVOUT2 to keep the LDO regulating. 4 PVOUT2 must be lower than VREG_LDO by at least VVREG_LDO-PVOUT2 to keep the LDO regulating. 5 The dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage. 6 The current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is the current that causes the output voltage to drop to 90% of 1.0 V or 0.9 V. ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments HEADROOM VOLTAGE (PVIN2 − PVOUT2) VHR 160 mV ILOAD2 = 1 mA 280 mV ILOAD2 = 1.5 A 400 mV ILOAD2 = 3 A

ing conditions for extended periods may affect product reliability. environment. Careful attention to PCB thermal design is required. Table 6. Thermal Resistance recommended in the Layout Considerations section. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 7. Pin Function Descriptions 1, 31, 32 PGND1 Buck Regulator Dedicated Power Ground. 2 VOUT1 Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor. 4 EN2 LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn off the LDO regulator. frequency from 300 kHz to 2.5 MHz. 6 to 8 PVIN2 LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2. 9 to 11 PVOUT2 LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2. 14 VBUF Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N. 15 AGND2 LDO Dedicated Analog Ground. 17 VSET2 LDO Regulator Output Voltage Configuration Input. 19 VSET1 Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom control. 20 PWRGD Power-Good Digital Output (Open-Drain NFET Pull-Down Driver). 21 COMP1 Buck Regulator External Compensation Pin. 22 RT Resistor Adjustable Frequency Programming Input. 25 PVINSYS System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1. 26, 27 PVIN1 Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1. 28 to 30 SW1 Buck Regulator Switching Output. EPAD Exposed Thermal Pad. Connect the exposed thermal pad to AGND1.

Figure 3. Buck Efficiency vs. Load Current, VPVIN1 = 5 V, fSW = 600 kHz at Figure 4. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, fSW = 600 kHz at Figure 5. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, VPVOUT1 = 3.3 V at Figure 6. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 5 V, fSW = 600 Figure 7. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V, fSW = 600 Figure 8. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V, VPVOUT2 =

3.3 V at Various Buck Switching Frequencies

analog.com Rev. B | 14 of 29 POWER MANAGEMENT UNIT The ADP5003 is a micropower management unit combining a step- down (buck) dc-to-dc converter and an ultralow noise low dropout linear (LDO) regulator. The high switching frequency and 5 mm × 5 mm, 32-lead LFCSP package allow a compact power management solution. Adaptive Headroom Control The ADP5003 features a scheme to control the LDO headroom voltage to ensure optimal operating efficiency while maintaining a consistent power supply rejection ratio (PSRR) across the full range of the LDO load current. The scheme works by varying the headroom voltage across the LDO NFET with respect to the LDO load current. Lower and upper limits prevent the headroom from approaching zero volts at light loads and from increasing more than necessary at high loads. Precision Enable/Shutdown The ADP5003 has individual enable pins (EN1 and EN2) to control the regulators. The precision enable function allows a precise turn on point for the regulators to allow the possibility of external sequencing. A voltage level higher than VTH_H applied to the EN1 or EN2 pin activates a regulator, whereas a level below VTH_L turns off a regulator. The buck is controlled by EN1, and the LDO is controlled by the EN2 pin. When both EN1 and EN2 fall below VTH_S, the ADP5003 enters shutdown mode. Undervoltage Lockout (UVLO) To protect against the input voltage being too low, UVLO circuitry is integrated into the system. If the input voltage on PVINSYS drops to less than the UVLOPVINSYSFALL threshold, all channels shut down. The device is enabled again when the voltage on PVINSYS rises to more than the UVLOPVINSYSRISE threshold, provided the enable pins remain active. Thermal Shutdown (TSD) In the event that the junction temperature rises above TSD, the thermal shutdown circuit turns off both regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or a high ambient temperature. A hysteresis value of TSD-HYS is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temper- ature drops below TSD − TSD-HYS. When emerging from thermal shutdown, both regulators restart with soft start control. Active Pull Down Both regulators have active pull-down resistors discharging the respective output capacitors when the regulators are disabled. The pull-down resistors are connected between VOUT1 to AGND1 and PVOUT2 to AGND2. Active pull-down resistors are disabled when the regulators are turned on. When the enable pins are asserted low, or a TSD or UVLO event occurs, the active pull-down resistors enable to quickly discharge the output capacitors. The pull-down resistors remain engaged until the enable pins are asserted high, the fault event is no longer present, or the VREG supply voltage falls to less than the voltage required (approximately 1 V) to guarantee that the pull-down resis- tor remains enabled. Soft Start (SS) Both regulators have an internal soft start function that ramps the output voltage in a controlled manner on startup, thereby limiting the inrush current. The soft start function reduces the risk of noise spikes and voltage drops on the upstream supplies. Power-Good The ADP5003 has a dedicated power-good, open-drain, output (PWRGD). PWRGD indicates whether one or more regulators are outside the voltage limits specified by the power-good lower limit (PWRGDF) and the power-good upper limit (PWRGDF + PWRGDFH). When either one or both of the regulator outputs are outside the power-good limits, the PWRGD output pulls low. PWRGD will continue to pull low, provided the VREG supply volt- age remains above approximately 1 V. When in adaptive mode, PWRGD only monitors the LDO output, and when in standalone mode, PWRGD only monitors the regula- tor/regulators that are enabled. BUCK REGULATOR Control Scheme The buck regulator operates with a fixed frequency, emulated peak current mode, pulse-width modulation (PWM) control architecture, where the duty cycle of the integrated switches is adjusted and regulates the output voltage. At the start of each oscillator cycle, the positive channel field effect transistor (PFET) switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the emulated current sense signal crosses the peak inductor current threshold, which turns off the PFET switch and turns on the NFET synchronous rectifier. Turning on the NFET synchronous rectifier creates a negative voltage across the inductor, which causes the inductor current to decrease. The synchronous rectifier stays on for the remainder of the cycle. By adjusting the peak inductor current threshold, the buck regulator can regulate the output voltage.

Figure 40. Short-Circuit Response (Current Limit and Hiccup Mode) with low headroom voltage and an output current up to 3 A.

5 V while providing excellent line and load transient response using

10 µF ceramic input and output capacitors. Figure 41. LDO Startup to maintain a constant output current. more precise supply scheme at the point of load. Figure 42. Differential Remote Sensing is not critical, it is recommended to use a 10 kΩ to 300 kΩ resistor. The resistor must be pulled to a voltage level no greater than 5.5 V.

VOUT_MAX is the maximum output voltage. IOUT_MAX is the maximum output current. tMIN_OFF is the minimum off time. improve the load transient response. because of their poor temperature and dc bias characteristics. CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst case capacitor temperature coefficient. DCBIASCO is the dc bias derating at the output voltage. Tolerance is the worst case component tolerance. behavior of the capacitors for each application. fSW is the switching frequency. VRIPPLE is the allowed peak-to-peak voltage ripple. RESR is the effective series resistance of the capacitor. ture and dc bias effects is 22 µF. The minimum capacitance recommended for the LDO is 10 µF. Table 8. Recommended Output Capacitors

capacitor as close as possible to the relevant supply pin. maximum load current for optimal transient response and efficiency. VPVIN1 is the input voltage. VPVOUT1 is the output voltage. D is the duty cycle (D = VVOUT1/VPVIN1). ΔIL is the inductor ripple current. fSW is the switching frequency. ILOAD1 is the output current. ΔIL is the inductor ripple current. Table 9. Recommended Inductors

peak current mode control, small signal circuit. Figure 46. Simplified Peak Current Mode Control, Small Signal Circuit the optional CCP and RC contribute an optional pole.

1. Determine the cross frequency (fC). Generally, fC is between
2. Use the following equation to calculate RC:

CPVOUT1 is the output capacitance.

1. Place the compensation zero at the domain pole (fP). Determine

RESR is the equivalent series resistance of the output capacitor.

1. CCP is optional. It can cancel the zero caused by the ESR of the

the ground plane with several vias. θJC is the junction to case thermal resistance provided in Table 6. (MTBF) is highly affected by increasing the junction temperature. PDBUCK = (VPVIN1 × IPVIN1) − (VPVOUT1 × ILOAD1). PDLDO = ((VPVIN2 − VPVOUT2) × ILOAD2) + (VPVIN2 × IGND).

dures and the external components required for the buck regulator. Table 10 lists the design requirements for this example. Table 10. Example Design Requirements for the Buck Regulator efficiency due to lower switching losses. to 2.5 MHz by connecting a resistor from the RT pin to ground. standard resistor value of RT = 294 kΩ. VPVOUT1 is the buck output voltage. ABUCK is the buck regulator gain. D is the duty cycle (D = VPVOUT1/VPVIN1). value is 3.3 µH; therefore, ΔIL is 1 A. The calculated peak current for the inductor is 3.5 A. The calculated capacitance, COUT_MIN, is 8.7 µF. KUV and KOV are factors (typically set to 2). ΔVOUT_UV is the allowable undershoot on the output voltage. ΔVOUT_OV is the allowable overshoot on the output voltage. It is recommended to use two 22 µF ceramic capacitors.

requirements for this example. Table 11. Example Design Requirements for the Buck Regulator Using Therefore, select standard resistor RT = 294 kΩ. VPVOUT2 is the LDO output voltage. ALDO is the LDO regulator gain. VPVOUT1 = VPVOUT2 + VHR = 1.7 V. D is the duty cycle (D = VVOUT1/VPVIN1). value is 2.2 µH; therefore, ΔIL is 1.1 A. The calculated peak current for the inductor is 3.55 A. 18 to calculate the capacitance. output of the buck and a single 10 µF for the output of the LDO. therefore, fC is set to 10 kHz. Figure 48 shows the load transient waveform.

Figure 48. 0.6 A to 2.4 A Load Transient for 2.5 V Output, fSW = 600 kHz, L = (VPVOUT2 ± 100 mV at an ~60% step transient). Table 12. Recommended External Components for Buck Applications up to 3 A Operation (±5% Tolerance at an ~60% Step Transient)

Table 13. Recommended Buck External Components for Adaptive Headroom Applications up to 3 A Operation (VPVOUT2 ± 100 mV at an ~60% Step Transient)

►Keep high current loops as short and wide as possible. connecting them each as close as possible to the point of load. Keep them as short as possible and away from noise sources. AGND1 and PGND1 separate on the top layer of the board. This separation avoids pollution of AGND1 with switching noise. between the input and output capacitors. ►Connect the negative terminal of CVBUF to the VFB2N pin. Figure 53. Example Outline Layout

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]