ADP4000 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 37
Technical content
Features
- PMBus Interface
- Supports Both VR11 and VR11.1 Specifications
- Digitally Programmable 0.375 V to 1.6 V Output
- Additional 200 mV Offset Programmable (Max 1.8 V Output)
- Selectable 1-, 2-, 3-, 4-, 5-, or 6-Phase Operation
- Fast-Enhanced PWM FlexModet
- TRDET to Improve Load Release
- Active Current Balancing Between All Output Phases
- Supports On- -The- -Fly (OTF) VID Code Changes
- Supports PSI– Power Saving Mode
- This is a Pb- -Free Device Typical Applications
- Servers
- Desktop PC’s
- POLs (Memory) This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com PIN ASSIGNMENT
48 VCC3
45 VID0
44 VID1
43 VID2
42 VID3
41 VID4
40 VID5
(Not to Scale) PIN 1 INDICATOR 1ALERT 2FAULT
47 PWRGD
38 VID7
37 VCC
39 VID6
46 PSI
Device* Package Shipping †
ORDERING INFORMATION
ADP4000JCPZ- -REEL LFCSP482500/Tape & Reel ADP4000JCPZ- -RL7 LFCSP48 750/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z’ suffix indicates Pb- -Free package. MARKING DIAGRAM ADP4000 JCPZ #YYWW XXXXX CCCCC LFCSP40 CASE 932AD xx = Device Code # = Pb- -Free Package YYWW = Date Code XXX = Assembly Lot CCC = Country of Origin 16FBRTN 17COMP 18FB 19CSREF 20CSSUM 21CSCOMP 22ILIMFS 13RT 14RAMPADJ 15TRDET 24OD1 23ODN
Figure 1. Block Diagram
9 IMON
Figure 2. Application Schematic
http://onsemi.com ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage Range (Note 1) VIN - - 0 . 3t o6 V FBRTN VFBRTN - - 0 . 3t o+0 . 3V V PWM2 to PWM6, Rampadj - - 0 . 3t oVIN +0 . 3 V S W 1t oS W 6 - - 5t o+ 2 5V V SW1 to SW6 (<200 ns|) -- 1 0 t o + 2 5 V V All other Inputs and Outputs - - 0 . 3t oVIN +0 . 3 V Storage Temperature Range TSTG - -65 to 150 °C Operating Ambient Temperature Range 0t o8 5 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV ESD Capability, Machine Model (Note 2) ESDMM 100 V Moisture Sensitivity Level MSL 3 -- Lead Temperature Soldering Reflow (SMD Styles Only), Pb- -Free Versions (Note 3) TSLD 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to Electrical Characteristics and Application Information for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC- -Q100- -002 (EIA/JESD22- -A114) ESD Machine Model tested per AEC- -Q100- -003 (EIA/JESD22- -A115) Latchup Current Maximum Rating:≤150 mA per JEDEC standard: JESD78 3. For additional information on our Pb- -Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Thermal Characteristics, LFCSP , 7 mm * 7 mm (Note 1) Thermal Resistance, Junction- -to- -Air (Note 4) Thermal Resistance, Junction- -to- -Lead 2 (Note 4) RθJA RΨJL °C/W 4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. OPERATING RANGES(Note 1) Characteristic Symbol Min Max Unit Output Voltage (Adjustable Version Only) (Note 5) VOUT 0.375 1.8 V Ambient Temperature TA 0 85 °C 5. Maximum limit for VOUT =V OUT(NOM) - - 10%.
http://onsemi.com PIN ASSIGNMENT Pin No. Pin Name Description 1 ALERT ALERT Output. Open drain output that asserts low when the VR exceeds a programmable limit. 2 FAULT FAULTOutput. Open drain output that asserts low when a fault has occurred. This fault can be due to VR or current- -limit, crowbar, or undervoltage. The trip points are loaded into registers. 3 SDA Digital Input Output. PMBus serial data bi- -directional pin. Requires PMBus pullup. 4 SCL Digital Input. PMBus serial bus clock open drain input. Requires PMBus pullup. 5 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 6 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
7 ADD/
PMBus Address Input. Connect a resistor to ground to select one of 8 addresses. This input is reconfigured after startup as an analog voltage monitor, VSENSE2. 8 VSENSE1 Analog Input. Measures an input voltage between 0 and 2.0 V and reports this back over the PMBus interface. 9 IMON Total Current Output Pin. 10 TTSENSE VR Temperature Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. 11 VRHOT VR HOT Output. Open drain output that signals when the temperature at the monitoring point connected to TTSENSE exceeds the VRHOT temperature threshold. 12 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IILIMFS, and ITH(X). 13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. 14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. 15 TRDET Transient Detect. This output is asserted low whenever a load release is detected 16 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. 17 COMP Error Amplifier Output and Compensation Point. 18 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. 19 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the Power- -Good and crowbar functions. This pin should be connected to the common point of the output inductors. 20 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 21 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. 22 ILIMFS Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal current sensing signal for current- -limit and IMON. This value can be over- -written using PMBus interface. 23 ODN Output Disable Logic Output for PSIoperation. This pin is actively pulled low when PSIis low, otherwise it functions in the same way as OD1. 24 OD1 Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high- -side and low- -side outputs should go low. 25 to 30 SW6 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 31 to 36 PWM6 to PWM1 Logic- -Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3121. Connecting PWM6 to V CC disables PWM6, connecting PWM5 to VCC disables PWM5 and PWM6, etc. This means the ADP4000 can be setup to operate as a 1- - 2- -, 3- -, 4- -, 5- -, or 6- -phase controller. 37 VCC Supply Voltage for the Device. A 340Ω resistor should be placed between the 12 Vsystem supply and the VCC pin. The internal shunt regulator maintains VCC =5 . 0V . 38 to 45 VID7 to VID0 Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 V. 46 PSI Power State Indicator. Pulling this pin low places the controller in lower power state operation. 47 PWRGD Power- -Good Output. Open- -drain output that signals when the output voltage is outside of the proper operating range. 48 VCC3 3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3 V LDO.
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ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN - - GND, for typical values TA =2 5°C, for min/max values TA =0 °Ct o8 5°C; unless otherwise noted. (Notes 6 and 7) Parameter Test Conditions Symbol Min Typ Max Unit Reference Current Reference Bias Voltage VIREF 1.75 1.8 1.85 V Reference Bias Current RIREF = 121 kΩ IIREF 15 mA Error Amplifier Output Voltage Range VCOMP 0 4.4 V Accuracy Relative to nominal DAC output, referenced t oF B R T N( s e eF i g u r e2 ) In startup VFB VFB(BOOT) -- 7 1.093 1.1 1.107 mV V Load Line Positioning Accuracy -- 7 7 -- 8 0 -- 8 3 mV Load Line Range - -350 0 mV Load Line Attenuation 0 100 % Differential Non- -linearity -- 1 . 0 +1.0 LSB Input Bias Current IFB 14.2 16 17.7 mA Offset Accuracy VR Offset Register = 111111, VID = 1.0 V VR Offset Register = 011111, VID = 1.0 V - -193.75 193.75 mV FBRTN Current IFBRTN 100 200 mA Output Current FB forced to VOUT -- 3 % ICOMP 500 mA Gain Bandwidth Product COMP = FB GBW(ERR) 20 MHz Slew Rate COMP = FB 25 V/ms BOOT Voltage Hold Time Internal Timer tBOOT 2.0 ms VID Inputs Input Low Voltage VID(X) VIL(VID) 0.3 V Input High Voltage VID(X) VIH(VID) 0.8 V Input Current IIN(VID) -- 5 . 0 mA VID Transition Delay Time VID code change to FB change 200 ns No CPU Detection Turn- -Off Delay Time VID code change to PWM going low 5.0 ms Oscillator Frequency Range fOSC 0.25 9.0 MHz Frequency Variation TA =2 5°C, RT = 270 kΩ, 6- -phase TA =2 5°C, RT = 130 kΩ, 6- -phase TA =2 5°C, RT =6 8 kΩ, 6- -phase fPHASE 225 245 500 850 265 kHz Output Voltage RT = 500 kΩ to GND VRT 1.93 2.03 2.13 V RAMPADJ Output Voltage RAMPADJ - - FB, VFB =1 . 0V , IRAMPADJ = - -150mA VRAMPADJ -- 5 0 +50 mV RAMPADJ Input Current Range IRAMPADJ 5.0 60 mA Current Sense Amplifier Offset Voltage CSSUM - - CSREF (see Figure 4) VOS(CSA) -- 1 . 0 +1.0 mV Input Bias Current, CSREF CSREF = 1.0 V IBIAS(CSREF) -- 2 0 +20 mA Input Bias Current, CSSUM CSREF = 1.0 V IBIAS(CSSUM) -- 1 0 +10 nA Gain Bandwidth Product CSSUM = CSCOMP GBW(CSA) 10 MHz Current Sense Amplifier Slew Rate CCSCOMP =1 0p F 10 V/ms Input Common- -Mode Range CSSUM and CSREF 0 3.0 V Output Voltage Range 0.05 3.0 V Output Current ICSCOMP 500 mA Current- -Limit Latchoff Delay Time Internal Timer 8.0 ms 6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested.
http://onsemi.com VIN = (5.0 V) FBRTN - - GND, for typical values TA =2 5°C, for min/max values TA =0 °Ct o8 5°C; unless otherwise noted. (Notes 6 and 7) Parameter UnitMaxTypMinSymbolTest Conditions PSI Input Low Voltage 0.3 V Input High Voltage 0.8 V Input Current -- 5 mA Assertion Timing Fsw = 300kHz 3.3 ms Deassertion Timing Fsw = 300kHz 825 ns TRDET Output Low Voltage IOUT =- - 6m A VOL 150 300 mV IMON Clamp Voltage 1.0 1.15 V Accuracy 10 x (CSREF - - CSCOMP)/RILIM -- 3 . 0 3.0 % Output Current 800 mA Offset -- 5 . 5 5.5 mV Current- -Limit Comparator ILIM Bias Current CSREF - - CSCOMP)/RILIM, (CSREF - - CSCOMP) = 150 mV, RILIM =7 . 5kΩ ILIM 22 mA Current- -Limit Threshold Current 4/3 x IIREF ICL 22 mA Current Balance Amplifier Common- -Mode Range VSW(X)CM - -600 +200 mV Input Resistance SW(X) = 0 V RSW(X) 12 18 21 kΩ Input Current SW(X) = 0 V ISW(X) 8.0 12 18 mA Input Current Matching SW(X) = 0 V ΔISW(X) -- 6 . 0 +6.0 % Phase Balance Adjustment Range Low Phase Bal Registers = 00000 -- 2 5 % Phase Balance Adjustment Range High Phase Bal Registers = 11111 +25 % Delay Timer Internal Timer Delay Time Register = 011 2.0 ms Timer Range Low Delay Time Register = 000 0.5 ms Timer Range High Delay Time Register = 111 4.0 ms Soft- -Start Internal Timer Soft- -Start Slope Register = 010 0.5 V/ms Timer Range Low Soft- -Start Slope Register = 000 0.1 V/ms Timer Range High Soft- -Start Slope Register = 111 1.5 V/ms Enable Input Input Low Voltage VIL(EN) 0.3 V Input High Voltage VIH(EN) 0.8 V Input Current IIN(EN) -- 1 . 0 mA Delay Time EN > 0.8 V, Internal Delay tDELAY(EN) 2.0 ms ODN and OD1Outputs Output Low Voltage IOD(SINK) = - -400mA VOL(ODN/1) 160 500 mV Output High Voltage IOD(SOURCE) = 400mA VOL(ODN/1) 4.0 5.0 V ODN /O D 1Pulldown Resistor 60 kΩ 6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested.
http://onsemi.com VIN = (5.0 V) FBRTN - - GND, for typical values TA =2 5°C, for min/max values TA =0 °Ct o8 5°C; unless otherwise noted. (Notes 6 and 7) Parameter UnitMaxTypMinSymbolTest Conditions Power- -Good Comparator Undervoltage Threshold Relative to Nominal DAC Output VPWRGD(UV) - -600 - -500 - -400 mV Undervoltage Adjustment Range LowPWRGD_LO Register = 000 - -500 mV Undervoltage Adjustment Range HighPWRGD_LO Register = 111 - -150 mV Overvoltage Threshold Relative to DAC Output, PWRGD_Hi = 00 VPWRGD(OV) 200 300 400 mV Overvoltage Adjustment Range Low PWRGD_Hi Register = 11 150 mV Overvoltage Adjustment Range HighPWRGD_Hi Register = 00 300 mV Output Low Voltage IPWRGD(SINK) =- - 4m A VOL(PWRGD) 150 300 mV Power Good Delay Time During Soft- -Start Internal Timer 2.0 ms VID Code Changing 100 250 ms VID Code Static 200 ns Crowbar Trip Point Relative to DAC Output, PWRGD_Hi = 00 VCROWBAR 200 300 400 mV Crowbar Adjustment Range PWRGD_Hi Register 150 300 mV Crowbar Reset Point Relative to FBRTN 250 300 350 mV Crowbar Delay Time Overvoltage to PWM going low tCROWBAR VID Code Changing 100 250 ms VID Code Static 400 ns PWM Outputs Output Low Voltage IPWM(SINK) = - -400mA VOL(PWM) 160 500 mV Output High Voltage IPWM(SOURCE) = 400mA VOH(PWM) 4.0 5.0 V PMBus Interface Logic High Input Voltage VIH(SDA,SCL) 2.1 V Logic Low Input Voltage VIH(SDA,SCL) 0.8 V Hysteresis 500 mV SDA Output Low Voltage ISDA =- - 6m A VOL 0.4 V Input Current VIH;I IL -- 1 1.0 mA Input Capacitance CSCL, SDA 5.0 pF Clock Frequency fSCL 400 kHz SCL Falling Edge to SDA Valid Time 1.0 ms ALERT,F A U L TOutputs Output Low Voltage IOUT =- - 6m A VOL 0.4 V Output High Leakage Current VOH =5 . 0V VOH 1.0 mA TTSENSE Inputs TTSENSE Voltage Range Internally Limited 0 3.0 V Source Current RIREF = 121 kΩ ITH -- 11 0 - -125 - -140 mA VRHOT Output Low Voltage IVRHOT(SINK) =- - 4 m A 150 300 mV Input Voltage Conversion Range 0 2.0 V ADC Resolution LSB Weighting 2.0 mV Analog / Digital Converter ADC Input Voltage Range 0 2.0 V ADC Resolution 1.95 mV Total Unadjusted Error (TUE) 1.0 % Differential Non- -linearity (DNL) 8B i t s 1.0 LSB 6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested.
http://onsemi.com VIN = (5.0 V) FBRTN - - GND, for typical values TA =2 5°C, for min/max values TA =0 °Ct o8 5°C; unless otherwise noted. (Notes 6 and 7) Parameter UnitMaxTypMinSymbolTest Conditions Analog / Digital Convertercont. Conversion Time, Voltage Channel Averaging Enabled (32 averages) 80 ms Round Robin Cycle Time TBD ms ADD Input ADD Output Current IADD =2 / 3 * IIREF IADD 10 mA Address 000 Threshold 0.1 V Address 001 Threshold 0.15 0.225 V Address 010 Threshold 0.3 0.45 V Address 011 Threshold 0.5 0.675 V Address 100 Threshold 0.75 0.9 V Address 101 Threshold 1.0 1.25 V Address 110 Threshold 1.35 1.7 V Address 111 Threshold 1.8 V Supply VCC VCC 4.7 5.25 5.75 V DC Supply Current (see Figure 2) VSYSTEM = 13.2 V, RSHUNT = 340Ω IVCC 20 25 mA UVLO Turn- -On Current 6.5 11 mA UVLO Threshold Voltage VCC Rising VUVLO 9.5 V UVLO Turn- -Off Voltage VCC Falling 4.1 V VCC3 Output Voltage IVCC3 =1 m A VCC3 3.0 3.3 3.6 V 6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested. TYPICAL CHARACTERISTICS 500 1000 1500 2000 2500 3000 13 20 30 43 50 68 75 82 130 180 270 395 430 500 680 850 RT (kΩ) Frequency (Hz) PWM1 Figure 3.ADP4000 RT vs Frequency
a differential input for the current-limit comparator. The CPU current can also be monitored over the PMBus. circuit component values over the PMBus. and the current- -limit protection is tripped. Where RL = DCR of the Inductor. that ILIMFS must equal 22mA at that load. closest 1% resistor value is 6.8 kΩ. resolution is 3.3%. Table 3 gives some examples codes. Table 3. Current- -Limit toggling the EN pin low for a short time. waveforms are shown in Figure 9. Figure 9. Overcurrent Latchoff Waveforms
the current set by the ILIMFS resistor. should be chosen as follows. This gives a value of 4.54 kΩ for RMON. can be adjusted between 0% and 100% of the external RCSA. Table 4. Loadline Commands information used for positioning as described in the section. the PMBus Phase Bal SW(x) commands (0xE3 to 0xE8). logic according to the voltages listed in VID Code Table.
- Program the required VID Code to the
- Set the VID_EN bit (Bit 3) in the VR Config 1 A
(0xD2) and on the VR Config 1B (0xD3). voltage for the internal PWM ramps. VOUT_TRIM (0xDB) and VOUT_CAL (0xDC) Commands. a p p l i e dw h e nB i t5=1 . Table 5. Offset Codes CR is the internal ramp capacitor value (= 5pF). however noise rejection and stability degrades. change can be positive or negative. be limited to prevent large inrush currents.
provides the soft- -start values. Table 6. Transition Rate Codes number of phases to ramp up the output current. components such as the input filter and MOSFET’s. then its possible for one phase to carry most of the currrent. randomize the phase sequence. The IREF pin is used to set an internal current reference. ground programs the current based on the 1.8 V output. no CPU mode, or whenever the EN pin is pulled low. is programmed using Bits <2:0> of Command code 0xE1. The following is a table of the programmable values. Table 7. PWRGD High Limits Table 8. PWRGD Low Limits efficiency at lighter loads.
number of phases enabled can be changed over the PMBus. Table 9. # Phases Enabled DuringPSI Phase 3 will be enabled during PSI. threshold of approximately 300 mV . protecting the microprocessor from being destroyed. phases that are shut down during low power operation. capacitors through the inductors. ALERT and FAULTlevels through the PMBus interface.
Figure 10. Typical Shunt Resistor Value and Power the 12 V input supply is 12 V±10%, VIN(MAX)= 13.2 V). RSHUNT is the shunt resistor value. under the control of a master controller. thresholds for each possible PMBus address. Table 10. Setting Up the PMBus Address
- When all data bytes have been read or written,
the tenth clock pulse to assert a stop condition.
- The master sends the 7-bit slave address followed
- The slave asserts ACK on SDA
- The slave sends the byte count N.
- The master asserts ACK on SDA.
- The slave sends the first data byte
- The master asserts ACK on SDA.
- The slave sends the remainder of the data byes, the
master asserts an ACK on SDA after each data byte.
- After the last data byte the master asserts a No
- The master asserts a STOP condition on SDA.
Figure 20. Block Write to a Command Coder device from locking or holding the PMBus expecting data. feature, so it can be disabled. Bit 3 SMB_TO_EN = 1; PMBus timeout enabled. Bit 3 TODIS = 0; PMBus timeout disabled (default). critical ADP4000 register settings, the lock bit can be set. are locked see the register map. (ON_OFF_Config) in Table 11. EN). The other two options are margin high and margin low. VOUT_MARGIN_LOW VID Code (0x26). temperature measurement Read_Temperature1 (0x8D). w o r s et h a na nA L E R Tcondition. and 0xFA in Table 11 for more details.
http://onsemi.com Limits. The ADP4000 uses Linear Mode. Linear Mode can be decoded as follows: X = Y*2^N Where X = the value (for example if this is current then it would be Amps, Temperature it would be°Ce t c ) .T h e register readback is 16 Bits, the 5 MSB’s are the Exponent (=N) and the 11 LSB’s are the mantissa (=Y). Both the mantissa and exponent are 2’s compliment values, if the MSB are 1 then they are negative values. IOUT_CAL_GAIN and IOUT_CAL_OFFSET The ADP4000 measures the voltage on the Imon pin and stores that in the READ_IOUT Command (0x8C). However the PMBus spec says this register should read back Amps. Therefore the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands need to be programmed to convert the Imon voltage into current in Amps. The following equation is used: READ_IOUT = Imon Voltage×IOUT_CAL_GAIN (eq. 19) +IOUT_CAL_OFFSET The IOUT_CAL_GAIN defaults to 1 and IOUT_CAL_OFFSET defaults to 0 which means the Imon voltage is stored in the READ_IOUT Command.
http://onsemi.com VR11 VID CODES for the ADP4000 OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 OFF 0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 1.60000 0 0 0 0 0 0 1 0 1.59375 0 0 0 0 0 0 1 1 1.58750 0 0 0 0 0 1 0 0 1.58125 0 0 0 0 0 1 0 1 1.57500 0 0 0 0 0 1 1 0 1.56875 0 0 0 0 0 1 1 1 1.56250 0 0 0 0 1 0 0 0 1.55625 0 0 0 0 1 0 0 1 1.55000 0 0 0 0 1 0 1 0 1.54375 0 0 0 0 1 0 1 1 1.53750 0 0 0 0 1 1 0 0 1.53125 0 0 0 0 1 1 0 1 1.52500 0 0 0 0 1 1 1 0 1.51875 0 0 0 0 1 1 1 1 1.51250 0 0 0 1 0 0 0 0 1.50625 0 0 0 1 0 0 0 1 1.50000 0 0 0 1 0 0 1 0 1.49375 0 0 0 1 0 0 1 1 1.48750 0 0 0 1 0 1 0 0 1.48125 0 0 0 1 0 1 0 1 1.47500 0 0 0 1 0 1 1 0 1.46875 0 0 0 1 0 1 1 1 1.46250 0 0 0 1 1 0 0 0 1.45625 0 0 0 1 1 0 0 1 1.45000 0 0 0 1 1 0 1 0 1.44375 0 0 0 1 1 0 1 1 1.43750 0 0 0 1 1 1 0 0 1.43125 0 0 0 1 1 1 0 1 1.42500 0 0 0 1 1 1 1 0 1.41875 0 0 0 1 1 1 1 1 1.41250 0 0 1 0 0 0 0 0 1.40625 0 0 1 0 0 0 0 1 1.40000 0 0 1 0 0 0 1 0 1.39375 0 0 1 0 0 0 1 1 1.38750 0 0 1 0 0 1 0 0 1.38125 0 0 1 0 0 1 0 1 1.37500 0 0 1 0 0 1 1 0 1.36875 0 0 1 0 0 1 1 1 1.36250 0 0 1 0 1 0 0 0 1.35625 0 0 1 0 1 0 0 1 1.35000 0 0 1 0 1 0 1 0 1.34375 0 0 1 0 1 0 1 1 1.33750 0 0 1 0 1 1 0 0 1.33125 0 0 1 0 1 1 0 1
http://onsemi.com VR11 VID CODES for the ADP4000 OUTPUT VID0VID1VID2VID3VID4VID5VID6VID7 1.32500 0 0 1 0 1 1 1 0 1.31875 0 0 1 0 1 1 1 1 1.31250 0 0 1 1 0 0 0 0 1.30625 0 0 1 1 0 0 0 1 1.30000 0 0 1 1 0 0 1 0 1.29375 0 0 1 1 0 0 1 1 1.28750 0 0 1 1 0 1 0 0 1.28125 0 0 1 1 0 1 0 1 1.27500 0 0 1 1 0 1 1 0 1.26875 0 0 1 1 0 1 1 1 1.26250 0 0 1 1 1 0 0 0 1.25625 0 0 1 1 1 0 0 1 1.25000 0 0 1 1 1 0 1 0 1.24375 0 0 1 1 1 0 1 1 1.23750 0 0 1 1 1 1 0 0 1.23125 0 0 1 1 1 1 0 1 1.22500 0 0 1 1 1 1 1 0 1.21875 0 0 1 1 1 1 1 1 1.21250 0 1 0 0 0 0 0 0 1.20625 0 1 0 0 0 0 0 1 1.20000 0 1 0 0 0 0 1 0 1.19375 0 1 0 0 0 0 1 1 1.18750 0 1 0 0 0 1 0 0 1.18125 0 1 0 0 0 1 0 1 1.17500 0 1 0 0 0 1 1 0 1.16875 0 1 0 0 0 1 1 1 1.16250 0 1 0 0 1 0 0 0 1.15625 0 1 0 0 1 0 0 1 1.15000 0 1 0 0 1 0 1 0 1.14375 0 1 0 0 1 0 1 1 1.13750 0 1 0 0 1 1 0 0 1.13125 0 1 0 0 1 1 0 1 1.12500 0 1 0 0 1 1 1 0 1.11875 0 1 0 0 1 1 1 1 1.11250 0 1 0 1 0 0 0 0 1.10625 0 1 0 1 0 0 0 1 1.10000 0 1 0 1 0 0 1 0 1.09375 0 1 0 1 0 0 1 1 1.08750 0 1 0 1 0 1 0 0 1.08125 0 1 0 1 0 1 0 1 1.07500 0 1 0 1 0 1 1 0 1.06875 0 1 0 1 0 1 1 1 1.06250 0 1 0 1 1 0 0 0 1.05625 0 1 0 1 1 0 0 1 1.05000 0 1 0 1 1 0 1 0 1.04375 0 1 0 1 1 0 1 1
http://onsemi.com VR11 VID CODES for the ADP4000 OUTPUT VID0VID1VID2VID3VID4VID5VID6VID7 1.03750 0 1 0 1 1 1 0 0 1.03125 0 1 0 1 1 1 0 1 1.02500 0 1 0 1 1 1 1 0 1.01875 0 1 0 1 1 1 1 1 1.01250 0 1 1 0 0 0 0 0 1.00625 0 1 1 0 0 0 0 1 1.00000 0 1 1 0 0 0 1 0 0.99375 0 1 1 0 0 0 1 1 0.98750 0 1 1 0 0 1 0 0 0.98125 0 1 1 0 0 1 0 1 0.97500 0 1 1 0 0 1 1 0 0.96875 0 1 1 0 0 1 1 1 0.96250 0 1 1 0 1 0 0 0 0.95625 0 1 1 0 1 0 0 1 0.95000 0 1 1 0 1 0 1 0 0.94375 0 1 1 0 1 0 1 1 0.93750 0 1 1 0 1 1 0 0 0.93125 0 1 1 0 1 1 0 1 0.92500 0 1 1 0 1 1 1 0 0.91875 0 1 1 0 1 1 1 1 0.91250 0 1 1 1 0 0 0 0 0.90625 0 1 1 1 0 0 0 1 0.90000 0 1 1 1 0 0 1 0 0.89375 0 1 1 1 0 0 1 1 0.88750 0 1 1 1 0 1 0 0 0.88125 0 1 1 1 0 1 0 1 0.87500 0 1 1 1 0 1 1 0 0.86875 0 1 1 1 0 1 1 1 0.86250 0 1 1 1 1 0 0 0 0.85625 0 1 1 1 1 0 0 1 0.85000 0 1 1 1 1 0 1 0 0.84375 0 1 1 1 1 0 1 1 0.83750 0 1 1 1 1 1 0 0 0.83125 0 1 1 1 1 1 0 1 0.82500 0 1 1 1 1 1 1 0 0.81875 0 1 1 1 1 1 1 1 0.81250 1 0 0 0 0 0 0 0 0.80625 1 0 0 0 0 0 0 1 0.80000 1 0 0 0 0 0 1 0 0.79375 1 0 0 0 0 0 1 1 0.78750 1 0 0 0 0 1 0 0 0.78125 1 0 0 0 0 1 0 1 0.77500 1 0 0 0 0 1 1 0 0.76875 1 0 0 0 0 1 1 1 0.76250 1 0 0 0 1 0 0 0 0.75625 1 0 0 0 1 0 0 1
http://onsemi.com VR11 VID CODES for the ADP4000 OUTPUT VID0VID1VID2VID3VID4VID5VID6VID7 0.75000 1 0 0 0 1 0 1 0 0.74375 1 0 0 0 1 0 1 1 0.73750 1 0 0 0 1 1 0 0 0.73125 1 0 0 0 1 1 0 1 0.72500 1 0 0 0 1 1 1 0 0.71875 1 0 0 0 1 1 1 1 0.71250 1 0 0 1 0 0 0 0 0.70625 1 0 0 1 0 0 0 1 0.70000 1 0 0 1 0 0 1 0 0.69375 1 0 0 1 0 0 1 1 0.68750 1 0 0 1 0 1 0 0 0.68125 1 0 0 1 0 1 0 1 0.67500 1 0 0 1 0 1 1 0 0.66875 1 0 0 1 0 1 1 1 0.66250 1 0 0 1 1 0 0 0 0.65625 1 0 0 1 1 0 0 1 0.65000 1 0 0 1 1 0 1 0 0.64375 1 0 0 1 1 0 1 1 0.63750 1 0 0 1 1 1 0 0 0.63125 1 0 0 1 1 1 0 1 0.62500 1 0 0 1 1 1 1 0 0.61875 1 0 0 1 1 1 1 1 0.61250 1 0 1 0 0 0 0 0 0.60625 1 0 1 0 0 0 0 1 0.60000 1 0 1 0 0 0 1 0 0.59375 1 0 1 0 0 0 1 1 0.58750 1 0 1 0 0 1 0 0 0.58125 1 0 1 0 0 1 0 1 0.57500 1 0 1 0 0 1 1 0 0.56875 1 0 1 0 0 1 1 1 0.56250 1 0 1 0 1 0 0 0 0.55625 1 0 1 0 1 0 0 1 0.55000 1 0 1 0 1 0 1 0 0.54375 1 0 1 0 1 0 1 1 0.53750 1 0 1 0 1 1 0 0 0.53125 1 0 1 0 1 1 0 1 0.52500 1 0 1 0 1 1 1 0 0.51875 1 0 1 0 1 1 1 1 0.51250 1 0 1 1 0 0 0 0 0.50625 1 0 1 1 0 0 0 1 0.50000 1 0 1 1 0 0 1 0 OFF 1 1 1 1 1 1 1 0 OFF 1 1 1 1 1 1 1 1
Table 11. PMBus Commands for the ADP4000
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W 4 1 ADP4000 has an SMBus ALERT pin and ARA is supported. 3:0 000 Reserved 0x20 R 0x20 VOUT_MODE 1 The ADP4000 supports VID mode for programming the output voltage. 0x21 R/W 0x00 VOUT_COMMAND 2 Sets the output voltage using VID. 0x25 R/W 0x0020 VOUT_MARGIN_ HIGH
2 Sets the output voltage when operation command is set to Margin
High. Programmed in VID Mode. 0x26 R/W 0x00B2 VOUT_MARGIN_ LOW Low. Programmed in VID Mode. 0x38 R/W 0x0001 IOUT_CAL_GAIN 2 Sets the ratio of voltage sensed to current output. Scale is Linear and is expressed in 1/Ω 0x39 R/W 0x0000 IOUT_CAL_OFFSET 2 This offset is used to null out any offsets in the output current sensing circuitry. Programmed in Linear mode and units are Amps. 0x4A R/W 0x0064 IOUT_OC_WARN_ LIMIT 2 This sets the high current- -limit. Once this limit is exceeded IOUT_OC_WARN_LIMIT bit is set in the Status_IOUT register and an ALERT is generated. This limit is set in Amps and programmed in Linear Mode. 0x4F R/W 0x0055 OT_FAULT_LIMIT 2 This sets the temperature limit above which the Over Temp Fault Bit gets set in the Status_TEMPERATURE Register and the FAULT Output gets asserted. This limit is set using Linear Mode in°C. 0x51 R/W 0x0046 OT_WARN_LIMIT 2 This sets the temperature limit above which the Over Temp Warn Bit gets set in the Status_TEMPERATURE Register and the ALERTOutput gets asserted. This limit is set using Linear Mode in°C. 0x52 R/W 0x0000 UT_WARN_LIMIT 2 This sets the temperature limit below which the Under Temp Warn Bit gets set in the Status_TEMPERATURE Register and the ALERTOutput gets asserted. This limit is set using Linear Mode in°C. 0x55 R/W 0x0010 VIN_OV_FAULTLIMIT 2 This sets the input over voltage fault limit. Once exceeded the VIN Overvoltage Fault Bit, Bit 7, gets set in the Status Input Register and the FAULToutput is asserted. This limit is set using Linear Mode, in V. 0x57 R/W 0x0010 VIN_OV_WARN LIMIT 2 This sets the input over voltage warn limit. Once exceeded the VIN Overvoltage Warn Bit, Bit 6, gets set in the Status Input Register and the ALERT output is asserted. This limit is set using Linear Mode, in V. 0x58 R/W 0x0000 VIN_UV_WARN LIMIT 2 This sets the input under voltage warn limit. Once exceeded the VIN Undervoltage Warn Bit, Bit 5, gets set in the Status Input Register and the ALERT output is asserted. This limit is set using Linear Mode, in V. 0x68 R/W 0x012C POUT_OP_ FAULT LIMIT 2 This sets the output power over power fault limit. Once exceeded Bit 1 of the Status I OUT Command gets set and the FAULToutput gets asserted (if not masked). This limit is set using Linear Mode in W. 0x6A R/W 0x012C POUT_OP_ WARN LIMIT 2 This sets the output power over power warn limit. Once exceeded Bit 0 of the Status I OUT Command gets set and the ALERToutput gets asserted (if not masked). This limit is set using Linear Mode in W. 0x78 R 0x00 STATUS BYTE 1 Bit Name Comment
7 BUSY A fault was declared because the
ADP4000 was busy and unable to respond.
6 OFF This bit is set whenever the
ADP4000 is not switching.
5 VOUT_OV This bit gets set whenever the
ADP4000 goes into OVP mode.
4 IOUT_OC This bit gets set whenever the
ADP4000 latches off due to an over current event.
3 VIN_UV This bit gets set when the input
voltage falls below its programmed FAULT limit.
2 TEMP This bit gets set when the
Temperature, as measured using the THERMISTOR, exceeds its THERM and/or high or low limits.
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W
1 CML A Communications, memory or
logic fault has occurred.
0 None of the Above A fault has occurred which is not
one of the above. 0x79 R 0x0000 STATUS WORD 2 Byte Bit Name Description Low 7 Res Reserved Low 6 OFF This bit is set whenever the ADP4000 is not switching. Low 5 VOUT _OV This bit gets set whenever the ADP4000 goes into OVP mode. Low 4 IOUT _OC This bit gets set whenever the ADP4000 latches off due to an over current event. Low 3 Res Reserved Low 2 TEMP This bit gets set when the Temperature, as measured using the THERMISTOR, exceeds its THERM and/or high or low limits. Low 1 CML A Communications, memory or logic fault has occurred. Low 6 None of the Above A fault has occurred which is not one of the above. High 7 VOUT This bit gets set whenever the measured output voltage goes outside its power good limits or an OVP event has taken place, i.e. any bit in Status V OUT is set. High 6 Iout/Pout This bit gets set whenever the measured output current or power exceeds its warning limit or goes into OCP . i.e. any bit in Status I OUT is set. High 5 INPUT This bit gets set if the input voltage, as measured on VSENSE1 goes outside its programmed limits. i.e. any bit in Status VINPUT is set. High 4 MFR A manufacturer specific warning or fault has occurred. High 3 POWER _GOOD The Power- -Good signal is deasserted. Same as Power- -Good in General Status. High 2 Res Reserved High 1 OTHER A Status bit in Status Other is asserted. High 0 Res Reserved 0x7A R 0x00 STATUS VOUT 1 Bit Name Description
7 VOUT_
This bit gets set whenever an OVP Event takes place.
6 VOUT_
This bit gets set whenever the measured output voltage goes above its Power- -Good limit.
5 VOUT_
This bit gets set whenever the measured output voltage goes below its Power- -Good limit.
4 VOUT_
Not applicable.
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W
3 VOUT_MAX
Not supported, Can’t program an output greater than max VID as there are no bits to program it. 2 TON_MAX_FAULT Not supported.
1 TOFF_MAX_
Not supported.
0 VOUT_TRACKING_
Not supported. 0x7B R 0x00 STATUS IOUT 1 Bit Name Description
7 IOUT Overcurrent
This bit gets set if the ADP4000 latches off due to an OCP Event.
6 Reserved Reserved
5 IOUT Overcurrent
This bit gets set if IOUT exceeds its programmed high warning limit.
4 Reserved Reserved
3 Reserved Reserved
2 Reserved Reserved
1 POUT Over- -Power
This bit gets set if the measured POUT exceeds the FAULT Limit.
0 POUT Over- -Power
This bit gets set if the measured POUT exceeds the Warn Limit. 0x7C R 0x00 STATUS INPUT 1 Bit Name Description
7 VIN Overvoltage
This bit gets set when the input voltage goes above its programmed FAULT limit.
6 VIN Overvoltage
This bit gets set when the input voltage goes above its programmed high limit.
5 Undervoltage
This bit gets set when the input voltage falls below its programmed low limit.
1 Reserved Reserved
0 Reserved Reserved
0x7D R 0x00 STATUS_ TEMPERATURE
1 Bit Name Description
7 Overtemperature
This bit gets asserted when the temperature measured by the Thermistor connected to TTSENSE exceeds its THERM/FAULT Limit.
6 Overtemperature
This bit gets asserted when the temperature measured by the Thermistor connected to TTSENSE exceeds its High Temperature Limit.
5 Undertemperature
This bit gets asserted when the temperature measured by the Thermistor connected to TTSENSE exceeds its Low Temperature Limit.
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W 0x7E R 0x00 STATUS CML 1 Bit Name Description
7 Invalid or
6 Invalid or
5 PEC Failed Supported
4 Memory Fault
3 Processor Fault
1 A communication
occurred. Supported
0 Other memory or
occurred. Not Supported 0x80 R 0x00 STATUS_ALERT 1 Bit Name Description
7 Reserved Reserved
5 VSENSE2 FAULT Gets asserted when VSENSE2
exceeds it programmed FAULT limits.
4 VSENSE2 OV
Gets asserted when VSENSE2 exceeds it programmed OV WARN limits.
3 VSENSE2 OV
Gets asserted when VSENSE2 exceeds it programmed UV WARN limits.
2 VMON WARN Gets asserted when VSENSE2
exceeds it programmed WARN limits.
1 VMON FAULT Gets asserted when VSENSE2
exceeds it programmed FAULT limits. 0x88 R 0x00 READ_VIN 2 Readback input voltage (measured using VSENSE1). Voltage is read back in Linear Mode 0x8B R 0x00 READ_VOUT 2 Readback output voltage. Voltage is read back in VID Mode. 0x8C R 0x00 READ_IOUT 2 Readback output current. Current is read back in Linear Mode (Amps). 0x8D R 0x00 READ_ TEMPERATURE1 2 Readback temperature 1. Thermistor, connected to TTSENSE is the sense element. Temperature is read back in Linear Mode°C. 0x96 R 0x00 READ_POUT 2 Readback Output Power, read back in Linear Mode in W’s. 0x99 R 0x41 MFR_ID 1 0x41 Readback using the Block command with the Byte count equal to 1. 0x9A R 0x4000 MFR_MODEL 2 0x4000 Readback using the Block command with the Byte count equal to 2. 0x9B R 0x01 MFR_REVISION 1 0 Readback using the Block command with the Byte count equal to 1.
Table 12. Manufacturer Specific Command Codes for the ADP4000 1 Reset Resets all registers to their POR Value. Has no effect if Lock bit is set.
0 Lock Logic 1 locks all limit values to their
5 Reserved Reserved
2 FAULT_EN Enable the FAULTpin, Default = 1
1 ALERT_EN Enable the ALERTpin
0 ENABLE_
3 VID_EN When the VID_EN bit is set to 1, the VID
2 LOOP_EN When the LOOP_EN bit is set to 1 in
control loop output pin is COMP .
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W
1 CLIM_EN When CLIM_EN is set to 1, the
current- -limit time out latchoff functions normally. When this bit is set to 0 in both registers, the current- -limit latchoff is disabled. In this state, the part can be in current- -limit indefinitely. 0xD3 R/W 0x52 VR Config 1B 1 This register is for security reasons. It has the same format as register 0xD2. Bits need to be set in both registers for the function to take effect. 0xD4 R/W 0x03 Ton Delay 1 This resister sets TD1, TD3 and TD5 delays for the soft- -start sequence. The current- -limit latchoff timer is 4 times the programmed delay time. 000 = 0.5 ms 001 = 1 ms 010 = 1.5 ms 011 = 2 ms = default 100 = 2.5 ms 101 = 3 ms 1 1 0=3 . 5m s 111 = 4 ms 0xD5 R/W 0x02 Ton Rise 1 This register sets the soft- -start voltage slew rate, and hence TD2 and TD4, of the soft- -start sequence. 000 = 0.1 V/ms 001 = 0.3 V/ms 010 = 0.5 V/ms = default 011 = 0.7 V/ms 100 = 0.9 V/ms 101 = 1.1 V/ms 1 1 0=1 . 3V / m s 111 = 1.5 V/ms 0xD6 R/W 0x01 Ton Transition 1 This register sets the slew rate during a dynamic VID. 000 = 1 V/ms 001 = 3 V/ms = default 010 = 5 V/ms 0 1 1=7V / m s 100 = 9 V/ms 101 = 11 V/ms 110 = 13 V/ms 111 = 15 V/ms 0xD7 R 0x00 VSENSE2 Voltage 2 This is a 16 bit value that reports back the voltage on the VSENSE2 Pin. Can be configured to measure the input Voltage Current. 16 Bit Value between 0 and 2.0 V. Voltage is reported using Linear Mode. 0xD8 R 0x00 EN/VTT Voltage 2 This is a 16 bit value that reports back the voltage on the VTT Pin. Voltage is reported using Linear Mode. 0xDA R 0x00 VMON Voltage 2 This is a 16 bit value that reports back the voltage measured between FB and FBRTN. Voltage is reported using Linear Mode. 0xDB R/W 0x00 VOUT_TRIM 1 Offset Command Code for VOUT,m a x±200 mV. 0xDC R/W 0x00 VOUT_CAL 1 Offset Command Code for VOUT,m a x±200 mV. 0xDE R/W 0x10 Load Line Calibration 1 This value sets the internal load line attenuation DAC calibration value. The maximum load line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.33% change in the load line. 00000 = No Load Line 10000 = 50% of external load line 11111 =100% of external Load Line 0xDF R/W 0x00 Load Line Set 1 This value sets the internal load line attenuation DAC value. The maximum load line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.33% change in the load line. 00000 = No Load Line 10000 = 50% of external load line 11111 =100% of external Load Line
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W 0xE0 R/W 0x00 PWRGD Hi Threshold 1 This value sets the PWRGD Hi Threshold and the CROWBAR Threshold: Code = 00, PWRGD HI = 300 mV (default) Code = 01, PWRGD HI = 250 mV Code = 10, PWRGD HI = 200 mV Code = 11, PWRGD HI = 150 mV 0xE1 R/W 0x00 PWRGD Lo Threshold 1 This value sets the PWRGD Lo Threshold: Code = 000, PWRGD Lo = -500 mV (default) Code = 001, PWRGD Lo = -450 mV Code = 010, PWRGD Lo = -400 mV Code = 011, PWRGD Lo = -350 mV Code = 100, PWRGD Lo = -300 mV Code = 101, PWRGD Lo = -250 mV Code = 110, PWRGD Lo = -200 mV Code = 111, PWRGD Lo = -150 mV 0xE2 R/W 0x10 Current- -Limit Threshold 1 This value sets the internal current- -limit adjust value. The default current- -limit is programmed using a resistor to ground on the LIMIT pin. The value of this register adjusts this value by a percentage between 50% and 146.7%. Each LSB represents a 3.33% change in the threshold. 11111 =146.7% of external current- -limit 10000 = 100% of external current- -limit (default) 00000 = 50% of external current- -limit 0xE3 R/W 0x10 Phase Bal SW1 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by±25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE4 R/W 0x10 Phase Bal SW2 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by±25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE5 R/W 0x10 Phase Bal SW3 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by±25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE6 R/W 0x10 Phase Bal SW4 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by±25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE7 R/W 0x10 Phase Bal SW5 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by±25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE8 R/W 0x10 Phase Bal SW6 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by±25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xEE R/W 0x0050 VRHOT RESET LIMIT 2 This is the temperature below which the VTHOT will de- -assert. 0xEF R/W 0x0002 VSENSE2 High Limit 2 VSENSE2 voltage high limit. 0xF0 R/W 0x0000 VSENSE2 Low Limit 2 VSENSE2 voltage low limit. 0xF1 R/W 0x0002 VSENSE2 FAULTLimit 2 VSENSE2 voltage FAULTlimit. 0xF5 R/W 0x0002 VMON FAULTLimit 2 VMON FAULTLimit.
http://onsemi.com Cmd Code Comment# Byte DescriptionDefaultR/W 0xF6 R/W 0x0002 VMON Warn Limit 2 VMON Warn Limit. 0xF7 R/W 0x07CE TTSENSE Gain 2 Gain information used to convert TTSENSE Voltage to temperature. 0xF8 R/W 0x007B TTSENSE Offset 2 Offset information used to convert TTSENSE Voltage to temperature. 0xF9 R/W 0x00 Mask ALERT 1 Bit Name Description
7 Mask VOUT Masks any ALERTcaused by bits in
Status VOUT Register.
6 Mask IOUT Masks any ALERTcaused by bits in
Status IOUT Register.
5 Mask Input Masks any ALERTcaused by bits in
Status Input Register.
4 Mask
Masks any ALERTcaused by bits in Status Temperature Register.
3 Mask CML Masks any ALERTcaused by bits in
Status CML Register.
2 VMON Masks any ALERTcaused by VMON
exceeding its high or low limit.
1 VSENSE2 Masks any ALERTcaused by VSENSE2
exceeding its high or low limit.
0 Mask POUT Masks any ALERTcaused by POUT
exceeding its programmed limit. 0xFA R/W 0x00 Mask FAULT 1 Bit Name Description
7 Mask VOUT Masks any FAULTcaused by bits in
Status VOUT Register.
6 Mask IOUT Masks any FAULTcaused by bits in
Status IOUT Register.
5 Mask Input Masks any FAULTcaused by bits in
Status Input Register. Masks any FAULTcaused by bits in Status Temperature Register.
3 Mask CML Masks any FAULTcaused by bits in
Status CML Register.
2 VMON Masks any FAULTcaused by VMON
exceeding its high or low limit.
1 VSENSE2 Masks any FAULTcaused by VSENSE2
exceeding its high or low limit.
0 Mask POUT Masks any FAULTcaused by POUT
exceeding its programmed limit. 0xFB R/W 0x00 General Status 1 Bit Name Description
7 FAULT
6 ALERT
5 POWER- -GOOD Replaced by Bit 3 of the Status Word
Command.
4 RDY
0xFC R 0x00 Phase Status 1 Bit Name Description
7 Phase 6 This bit is set to 1 when Phase 6 is
enabled.
6 Phase 5 This bit is set to 1 when Phase 5 is
enabled.
5 Phase 4 This bit is set to 1 when Phase 4 is
enabled.
4 Phase 3 This bit is set to 1 when Phase 3 is
enabled.
3 Phase 2 This bit is set to 1 when Phase 2 is
enabled.
http://onsemi.com PACKAGE DIMENSIONS LFCSP48 7x7, 0.5P CASE 932AD- -01 ISSUE O SEATING NOTE 4 M 0.20 C (A3) A b 48X L48X BOTTOM VIEW INDICATOR TOP VIEW SIDE VIEW D A B E 0.20 C PIN ONE REFERENCE 0.10 C 0.08 C C e A0.10 BC 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 7.00 BSC D2 4.95 5.25 E 7.00 BSC 5.25E2 4.95 e 0.50 BSC H -- -- -- 1 2 K 0 . 2 5 -- -- -- PLANE L 0.30 0.50 M -- -- -- 0 . 6 0 D1 6.75 BSC E1 6.75 BSC H PIN 1 M4X K NOTE 3 DIMENSIONS: MILLIMETERS 0.50 5.14 0.28 5.14 48X 0.63 48X 7.30 7.30 *For additional information on our Pb- -Free strategy and solder details, please download the ON Semiconductor Solderinga Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* PITCH PACKAGE OUTLINE ON Semiconductorand are registered trademarks of Semiconductor Com ponents Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guaranteeregarding the suitability of its products for any particular purpose,nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800- -282- -9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center ADP4000/D FlexMode is a trademark of Analog Devices, Inc. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303- -675- -2175 or 800- -344- -3860 Toll Free USA/Canada Fax: 303- -675- -2176 or 800- -344- -3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca l Sales Representative