ADP3196JCPZ-RL

ADP3196 AD | Alldatasheet

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6-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3196 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±10 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.3750 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for next generation AMD processors VRM modules GENERAL DESCRIPTION The ADP31961 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a

12 V main supply into the core supply voltage required by high

performance Advanced Micro Devices, Inc. (AMD) processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.3750 V and 1.55 V . This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3196 supports a programmable slope function to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. This can be disabled by connecting Pin LLSET to Pin CSREF. 1Protected by U.S. Patent Number 6,683,441; others patents pending. FUNCTIONAL BLOCK DIAGRAM VCC PRECISION REFERENCE DELAY GND ADP3196 EN DELAY ILIMIT PWRGD RAMPADJRT PWM2 PWM3 PWM4 SW3 SW2 SW1 CSREF CSCOMP SW4 CSSUM FB PWM1 VID5 VID4 VID3 VID2 VID0VID1 COMP FBRTN VID DAC 800mV – CSREF 1.8V CURRENT MEASUREMENT AND LIMIT CROWBAR CURRENT LIMIT CMP CMP CMP –CMPCURRENT BALANCING CIRCUIT 2-/3-/4-PHASE DRIVER LOGIC ENSET RESET RESET RESET RESET OD SS IREF THERMAL THROTTLING CONTROL TTSENSE VRMHOT VRM_OFF LLSET UVLO SHUTDOWN SHUNT REGULATOR IMON DAC – 250mV OSCILLATOR SOFT START CONTROL 131231 393534 3836 37 06371-001 Figure 1. Functional Block Diagram system supply through a series resistor.

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 20 SPECIFICATIONS VCC = 5 V , FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter Symbol Conditions Min Typ Max Unit REFERENCE CURRENT Reference Bias Voltage VIREF 1.5 V Reference Bias Current IIREF RIREF = 100 kΩ 14.25 15 15.75 μA ERROR AMPLIFIER Output Voltage Range2 VCOMP 0.05 4.4 V Accuracy VFB Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 2) −10 10 mV Load Line Positioning Accuracy CSREF – LLSET = 80 mV −78 −80 −82 mV Differential Nonlinearity −1 +1 LSB Input Bias Current IFB IFB = 0.5 × IIREF −9 −7.5 −6 μA FBRTN Current IFBRTN 65 200 μA Output Current ICOMP FB forced to VOUT – 3% 500 μA Gain Bandwidth Product GBW(ERR) COMP = FB 20 MHz Slew Rate COMP = FB 25 V/μs LLSET Input Voltage Range VLLSET Relative to CSREF −250 +250 mV LLSET Input Bias Current ILLSET −10 +10 nA VID INPUTS Input Low Voltage VIL(VID) VID(X), VIDSEL 0.6 V Input High Voltage VIH(VID) VID(X), VIDSEL 1.4 V Input Current IIN(VID) −10 μA VID Transition Delay Time2 VID code change to FB change 400 ns OSCILLATOR Frequency Range2 fOSC 0.25 4 MHz Frequency Variation fPHASE TA = 25°C, RT = 205 kΩ, 4 phase 180 200 220 kHz TA = 25°C, RT = 118 kΩ, 4 phase 400 kHz TA = 25°C, RT = 55 kΩ, 4 phase 800 kHz Output Voltage VRT RT = 243 kΩ to GND 1.9 2.0 2.1 V RAMPADJ Output Voltage VRAMPADJ RAMPADJ – FB, DAC = 1.55 V −50 +50 mV RAMPADJ Input Current Range IRAMPADJ 1 50 μA CURRENT SENSE AMPLIFIER Offset Voltage VOS(CSA) CSSUM – CSREF (see Figure 3) −1.0 +1.0 mV Input Bias Current IBIAS(CSSUM) −10 +10 nA Gain Bandwidth Product GBW(CSA) CSSUM = CSCOMP 10 MHz Slew Rate CCSCOMP = 10 pF 10 V/μs Input Common-Mode Range CSSUM and CSREF 0 3.5 V Output Voltage Range 0.05 3.5 V Output Current ICSCOMP 500 μA Current Limit Latch-Off Delay Time tOC(DELAY) CDELAY = 10 nF 8 ms IMON Output IMON 10 × (CSREF – CSCOMP) > 50mV −6 +6 % CURRENT BALANCE AMPLIFIER Common-Mode Range VSW(X)CM −600 +200 mV Input Resistance RSW(X) SW(X) = 0 V 10 17 26 kΩ Input Current ISW(X) SW(X) = 0 V 8 12 20 μA Input Current Matching ΔISW(X) SW(X) = 0 V −4 +4 % CURRENT LIMIT COMPARATOR ILIMIT Bias Current IILIMIT IILIMIT = 2/3 × IIREF 9 10 11 μA ILIMIT Voltage VILIMIT RILIMIT = 121kΩ (VILIMIT = IILIMIT × RILIMIT) 1.09 1.21 1.33 V Maximum Output Voltage 3 V Current Limit Threshold Voltage VCL VCSREF – VCSCOMP, RILIMIT = 121 kΩ 80 100 125 mV Current Limit Setting Ratio VCL/IILIMIT 82.6 mV/V

Rev. 0 | Page 4 of 20 Parameter Symbol Conditions Min Typ Max Unit DELAY TIMER Normal Mode Output Current IDELAY IDELAY = IIREF 12 15 18 µA Output Current in Current Limit IDELAY(CL) IDELAY(CL) = 0.25 × IIREF 3.0 3.75 4.5 µA Threshold Voltage VDELAY(TH) 1.6 1.7 1.8 V SOFT START Output Current (Startup) ISS(STARTUP) During startup, ISS(STARTUP) = 0.25 × IIREF 3 3.75 4.5 μA Output Current (DAC Code Change) ISS(DAC) DAC code change, ISS(DAC) = 1.25 × IIREF 15 18.75 22.5 μA ENABLE INPUT Threshold Voltage VTH(EN) 750 800 850 mV Hysteresis VHYS(EN) 80 100 125 mV Input Current IIN(EN) −1 μA Delay Time tDELAY(EN) EN > 950 mV, CDELAY = 10 nF 2 ms OD OUTPUT Output Low Voltage VOL(OD) 160 500 mV Output High Voltage VOH(OD) 4 5 V OD Pull-Down Resistor 60 kΩ THERMAL THROTTLING CONTROL TTSENSE Voltage Range Internally limited 0 5 V TTSENSE Bias Current −135 −123 −111 μA TTSENSE VRM_OFF Threshold Voltage 1.06 1.105 1.15 V TTSENSE VRMHOT Threshold Voltage 765 810 855 mV TTSENSE Hysteresis 50 mV VRM_OFF Output Low Voltage VOL(VRFAN) I VRFAN (SINK) = −4 mA 150 300 mV VRMHOT Output Low Voltage VOL(VRHOT) I VRHOT (SINK) = −4 mA 150 300 mV POWER-GOOD COMPARATOR Overvoltage Threshold VPWRGD(OV) Relative to nominal DAC output; DAC = 0.5 V to 1.55 V 200 250 300 mV Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V 190 250 310 mV Undervoltage Threshold VPWRGD(UV) Relative to nominal DAC output; DAC = 0.5 V to 1.55 V −300 −250 −200 mV Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V −310 −250 −190 mV Output Low Voltage VOL(PWRGD) IPWRGD(SINK) = −4 mA 150 300 mV Power-Good Delay Time During Soft Start2 CDELAY = 10 nF 2 ms VID Code Changing 100 250 μs VID Code Static 200 ns Crowbar Trip Point VCROWBAR Relative to FBRTN 1.75 1.8 1.85 V Crowbar Delay Time tCROWBAR Overvoltage to PWM going low VID Code Changing 100 250 μs VID Code Static 400 ns PWM OUTPUTS Output Low Voltage VOL(PWM) IPWM(SINK) = −400 μA 160 500 mV Output High Voltage VOH(PWM) IPWM(SOURCE) = 400 μA 4.0 5 V POWER SUPPLY VSYSTEM = 12 V, RSHUNT = 340Ω (see Figure 2) VCC VCC 4.65 5 5.55 V DC Supply Current IVCC 25 mA UVLO Turn On Current 6.5 11 mA UVLO Threshold Voltage VUVLO VCC rising 9 UVLO Threshold Voltage VUVLO VCC falling 4.1 V 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production.

Rev. 0 | Page 6 of 20 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VCC −0.3 V to +6 V FBRTN −0.3 V to +0.3 V PWM3 – PWM4, RAMPADJ −0.3 V to VCC + 0.3 V SW1 – SW4 −5 V to +25 V <200 ns −10 V to +25 V All Other Inputs and Outputs −0.3 V to VCC + 0.3 V Storage Temperature −65°C to +150°C Operating Ambient Temperature Range 0°C to 85°C Operating Junction Temperature 125°C Thermal Impedance (θJA) 100°C/W Lead Temperature Soldering (10 sec) 300°C Infrared (15 sec) 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages referenced to GND. ESD CAUTION

23 SW3

24 SW2

25 SW1

27 PWM4

28 PWM3

29 PWM2

30 PWM1

22 SW4

21 IMON

1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN

ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND. Figure 5. Pin Configuration Table 3. Pin Function Descriptions 1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 3 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. this pin and the output voltage sets the no load offset point. 5 COMP Error Amplifier Output and Compensation Point. ramp-up time and the VID on-the-fly slew rate. latch-off delay time, EN delay time, and PWRGD delay time. TTSENSE exceeds the VRM_OFF threshold. signal) output from the CPU. the temperature at the desired thermal monitoring point. currents together to measure the total output current. current sense amplifier and the positioning loop response time. 18 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Rev. 0 | Page 8 of 20 Pin No. Mnemonic Description 19 OD Output Disable Logic Output. This pin is actively pulled low when the ADP3196 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. 20 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, IILIMIT and ITTSENSE. 21 IMON Analog Output. Represents total load current. 22 to 25 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 26, 32, 33, 40 NC No Connection. 27 to 30 PWM4 to PMW1 Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A. Connecting the PWM3 and/or PWM4 outputs to the ADP3196 VCC pin causes that phase to turn off, allowing the ADP3196 to operate as a 2-, 3-, or 4-phase controller. 31 VCC A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. 34 to 39 VID5 to VID0 Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4).

Figure 6. Master Clock Frequency vs. RT

4-phase synchronous buck CPU core supply power converters. currents and low voltages demanded by today’s microprocessors. as the inductors and MOSFETs.

• Balancing currents and thermals between phases
• High speed response at the lowest possible switching frequency and output decoupling
• Minimizing thermal switching losses by utilizing lower frequency operation
• Tight load line regulation and accuracy
• High current output due to 4-phase operation
• Reduced output ripple due to multiphase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component selection
• Flexibility in operation for tailoring design to low cost or high performance START-UP SEQUENCE The ADP3196 follows the start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first four clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the Phase Detection Sequence section. Then, the soft start ramp is enabled (TD2) and the output comes up to the programmed DAC Voltage. After TD2 has been completed and the PWRGD masking time (equal to VID on-the-fly masking) is finished, a second ramp on the DELAY pin sets the PWRGD blanking (TD3). ADP3196 EN VCC_CORE DELAY VR READY (ADP3196 PWRGD) CPU VID INPUTS TD1 TD2 TD3 0.8V VDELAY(TH) (1.7V) SS VVID VVID SUPPLY UVLO THRESHOLD VID INVALID VID VALID 06371-006

Figure 7. System Start-Up Sequence on at the same time to allow overlapping phases.

Rev. 0 | Page 11 of 20 MASTER CLOCK FREQUENCY The clock frequency of the ADP3196 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 4. If PWM4 is tied to VCC, then divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are tied to VCC, then divide by 2. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3196 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of ±10 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. Pin FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. Pin FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3196 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system as follows:

• Output inductor DCR sensing without a thermistor for lowest cost
• Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature
• Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. An additional resistor divider connected between CSREF and CSCOMP , with the midpoint connected to LLSET, can be used to set the load line required by the microprocessor. The current information is then given as CSREF – LLSET. This difference signal is used internally to offset the VID DAC for voltage positioning. The difference between CSREF and CSCOMP is then used as a differential input for the current-limit comparator. This allows the load line to be set independent of the current-limit threshold. In the event that the current-limit threshold and load line are not independent, the resistor divider between CSREF and CSCOMP can be removed and the CSCOMP pin can be directly connected to the LLSET pin. To disable voltage positioning entirely (that is, no load line), connect LLSET to CSREF. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is determined by external resistors to make it extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the LLSET pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed forward response. CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3196 has individual inputs (SW1 to SW4) for each phase that are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning described previously in the Output Current Sensing section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an intentional current imbalance, if desired, such as when one phase has better cooling and can support higher currents. Resistors R SW1 through RSW4 (see Figure 11) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, therefore, ensure that placeholders are provided in the layout. To increase the current in any given phase, make RSW for that phase larger (make RSW = 0 for the hottest phase and do not change during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first.

Rev. 0 | Page 14 of 20 DYNAMIC VID The ADP3196 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3196 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 μs to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. POWER-GOOD MONITORING The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 200 μs to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time (TD3) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS pin is within 50 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V . The PWRGD delay time is set, therefore, by a current of IREF charging a capacitor from 0 V to 1.7 V . OUTPUT CROWBAR To protect the load and output components of the supply, the PWM outputs are driven low which turns on the low-side MOSFETs when the output voltage exceeds the upper crowbar threshold. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. OUTPUT ENABLE AND UVLO For the ADP3196 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, the EN pin must be higher than its 0.8 V threshold, and the DAC code must be valid. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the ADP3196 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and forces PWRGD, and OD signals low. In the application circuit, the OD pin should be connected to the OD inputs of the ADP3120A drivers. Grounding OD disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. THERMAL MONITORING The ADP3196 includes a thermal monitoring circuit to detect when a point on the VR has exceeded two different user- defined temperatures. The thermal monitoring circuit requires an NTC thermistor to be placed between TTSENSE and GND. A fixed current of 8 × IREF (normally giving 123 μA) is sourced out of the TTSENSE pin and into the thermistor. The current source is internally limited to 5 V . An internal circuit compares the TTSENSE voltage to a 1.105 V and a 0.81 V threshold and outputs an open-drain signal at the VRM_OFF and VRMHOT outputs, respectively. The VRM_HOT open-drain output goes high once the voltage on the TTSENSE pin goes below the VRM_HOT thresholds and signals the system that an overtemperature event has occurred. The VRM_OFF output asserts when the voltage on the TTSENSE pin exceeds the VRM_OFF threshold. Because the TTSENSE voltage changes slowly with respect to time, 50 mV of hysteresis is built into these comparators. The thermal monitoring circuitry does not depend on EN and is active when UVLO is above its threshold. When UVLO is below its threshold, VRFAN and VRHOT are forced low.

Table 4. VID Codes

Rev. 0 | Page 16 of 20 1FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. 2CONNECT NEAR EACH INDUCTOR. 4 5 BST IN VCC DRVH SW PGND DRVL ADP3196 4 5 BST IN VCC DRVH SW PGND DRVL ADP3120A ADP3120A ADP3120A 4 5 BST IN VCC DRVH SW PGND DRVL PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT TTSENSE 1nF CB 630pF RB 2kΩ RTH1 100kΩ, 5% NTC RLIM 160kΩ RIREF 100kΩ RCS2 88.7kΩ RCS1 35.7kΩ RPH3 140kΩ RPH4 140kΩ RPH2 140kΩ RPH1 140kΩ RSW41 RSW31 RSW21 RSW11 RT 130kΩ RA 18.7kΩ CFB 16pF CDLY 18nF CSS 10nF 100µF (C3 OPTIONAL) + C4 1µF 680Ω 12V 680Ω 1kΩ VIN 12V VIN RTN C1 C2 0.1µF 1nF CCS1 1nF 5% NPO CCS2 1nF 5% NPO C22 4.7µF C18 4.7µF 1nF CA 630pF POWER GOOD VTT I/O VRM_OFF VRMHOT 1µF 169kΩ 2.2Ω 370nH 18A 2700µF/16V/3.3A×2 SANYO MV-WX SERIES + + C14 4.7µF 1N4148 1N4148 1N4148 C21 18nF 2.2Ω C17 18nF 2.2Ω C13 18nF Q10 IPD09N03L IPD09N03L IPD09N03L IPD09N03L Q11 IPD09N03L Q12 IPD09N03L C23 10nF C24 4.7µF C19 10nF C15 10nF C20 4.7µF 280nH/1.4mΩ 280nH/1.4mΩ IPD09N03L IPD09N03L IPD09N03L C16 4.7µF 280nH/1.4mΩ 4 5 BST IN OD VCC DRVH SW PGND DRVL ADP3120A C10 4.7µF 1N4148 2.2Ω 18nF C25 C32 C11 10nF IPD09N03L IPD09N03L IPD09N03L 560µF/4V × 7 SANYO SEPC SERIES 5mΩ EACH C12 4.7µF 280nH/1.4mΩ RTH2 100kΩ, 5% NTC 10Ω2 10Ω2 10Ω2 10Ω2 ++ VCC(CORE) 0.375V TO 1.55V 100A TDC VCC(SENSE) VSS(SENSE) VCC(CORE) RTN 10µF × 8 MLCC 06371-010 OD OD OD FROM CPU NC Figure 11.Typical 4-Phase Application Circuit

Rev. 0 | Page 17 of 20 LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1-ounce copper trace has a resistance of ~0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3196) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3196 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3196 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microproc- essor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (described in the Power Circuitry Recommendations section). Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal perform- ance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.

0.20 REF

0.05 MAX

0.02 NOM

0.80 MAX

0.65 TYP

0.60 MAX

0.25 MIN

Figure 12. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 19 of 20 NOTES

Rev. 0 | Page 20 of 20 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06371-0-10/06(0)