ADP3194

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Technical content

6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller ADP3194

FEATURES

Selectable 2-, 3-, or 4-phase operation Up to 1 MHz per phase ±9.5 mV worst-case differential sensing error ov er temperature Logic-level PWM outputs for interface to external high po wer drivers PWM Flex-ModeTM architecture for excellent load transient performance Active current balancing between all output phases Built-in power good/crowbar blank ing supports OTF VID code changes 6-bit digitally programmable 0.8375 V to 1.6 V output Programmable short circuit protection with programmable la tch-off delay

APPLICATIONS

Desktop PC power supplies for Next-generation Intel® processors VRM modules Games consoles FUNCTIONAL BLOCK DIAGRAM VCC GND ADP3194 EN DELAY ILIMIT PWRGD RTRAMPADJ PWM2 FB PWM3 PWM4 SW1 CSSUM CSCOMP SW2 SW3 SW4 CSREF PWM1 VID4 VID3 VID2 VID1 VID5VID0FBRTN COMP DAC + 150mV DAC – 250mV CSREF EN CROWBAR CURRENT LIMIT RESET RESET RESET RESET 2-/3-/4-PHASE DRIVER LOGIC ENSET CURREN T- BALANCING CIRCUIT OSCILLATOR DELAY UVLO SHUTDOWN AND BIAS CURRENT- LIMIT CIRCUIT SOFT START PRECISION REFERENCE VID DAC CMP CMP CMP CMP 28 1314 1 2 3 4 657 06022-001 SHUNT REGULATOR Figure 1. Functional Block Diagram

5 V or 12 V main supply into the core supply voltage required

fly (OTF) output voltage changes requested by the CPU. nge of 0°C to +85°C and are available in a 28-lead TSSOP . 1 Protected by U. S. Patent Number 6,683,441; other patents pending. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

Rev. 0 | Page 2 of 32 TABLE OF CONTENTS Design Comparison Trade-Off Between DCR and Sense

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 32 SPECIFICATIONS VCC = 5 V , FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1 Table 1. Parameter Symbol Conditions Min Typ Max Unit ERROR AMPLIFIER Output Voltage Range VCOMP 0 VCC V Accuracy V FB Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP; VOUT < 1 V −8.0 +8.0 mV Accuracy V FB Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP; VOUT > 1 V −9 5 +9.5 mV Line Regulation ΔVFB VCC = 4.75 V to 5 25 V 0.05 % Input Bias Current IFB 14 15.5 17 μA FBRTN Current IFBRTN 100 140 μA Output Current IO(ERR) FB forced to VOUT – 3% 500 μA Gain Bandwidth Product GBW(ERR) COMP = FB 20 MHz Slew Rate CCOMP = 10 pF 25 V/μs VID INPUTS Input Low Voltage VIL(VID) 0.4 V Input High Voltage VIH(VID) 0.8 V Input Current, Input Voltage Low IIL(VIDX) VID(X) = 0 V –25 –35 μA Input Current, Input Voltage High IIH(VIDX) VID(X) = 1.25 V 5 15 μA Pull-Up Resistance RVID 35 60 85 kΩ Internal Pull-Up Voltage 1.0 1.2 V VID Transition Delay Time2 VID code change to FB change 400 ns No CPU Detection Turn-Off Delay Time2 VID code change to 11111 to PWM going low 400 ns OSCILLATOR Frequency Range2 fOSC 0.25 4.5 MHz Frequency Variation fPHASE T A = +25°C, RT = 247 kΩ, 4-phase 1.55 2 2.45 MHz TA = +25°C, RT = 138 kΩ, 4-phase 3 MHz TA = +25°C, RT = 84 kΩ, 4-phase 4 MHz Output Voltage VRT R T = 100 kΩ to GND 1.8 2.0 2.3 V RAMPADJ Output Voltage VRAMPADJ RAMPADJ – FB –50 +50 mV RAMPADJ Input Current Range IRAMPADJ 0 100 μA CURRENT SENSE AMPLIFIER Offset Voltage VOS(CSA) CSSUM – CSREF –1.5 +1.5 mV Input Bias Current IBIAS(CSSUM) –10 +10 nA Gain Bandwidth Product GBW(CSA) 10 MHz Slew Rate CCSCOMP = 10 pF 10 V/μs Input Common-Mode Range CSSUM and CSREF 0 3 V Positioning Accuracy ΔVFB –77 –80 –83 mV Output Voltage Range 0.05 VCC V Output Current ICSCOMP 500 μA CURRENT BALANCE CIRCUIT Common-Mode Range VSW(X)CM –600 +200 mV Input Resistance RSW(X) SW(X) = 0 V 12 20 28 kΩ Input Current ISW(X) SW(X) = 0 V 5 11 17 μA Input Current Matching3 ΔISW(X) SW(X) = 0 V –5 +5 %

Rev. 0 | Page 4 of 32 Parameter Symbol Conditions Min Typ Max Unit CURRENT LIMIT COMPARATOR Output Voltage Normal Mode VILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ 2.8 3 3.3 V Shutdown Mode VILIMIT(SD) EN < 0.4 V, IILIMIT = –100 μA 400 mV Output Current, Normal Mode IILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ 12 μA Maximum Output Current2 60 μA Current Limit Threshold Voltage VCL V CSREF – VCSCOMP, RILIMIT = 250 kΩ 105 125 145 mV Current Limit Setting Ratio VCL/IILIMIT 10.4 mV/μA DELAY Normal Mode Voltage VDELAY(NM) RDELAY = 250 kΩ 2.8 3 3.3 V DELAY Overcurrent Threshold VDELAY(OC) R DELAY = 250 kΩ 1.6 1.9 2.2 V Latch-Off Delay Time tDELAY R DELAY = 250 kΩ, CDELAY = 12 nF 1 5 ms SOFT START Output Current, Soft Start Mode IDELAY(SS) During startup, DELAY < 2.8 V 15 20 25 μA Soft Start Delay Time tDELAY(SS) R DELAY = 250 kΩ, CDELAY = 12 nF , VID code = 011111 1 ms ENABLE INPUT Input Low Voltage VIL(EN) 0.4 V Input High Voltage VIH(EN) 0.8 V Input Current IIL(EN) –1 +1 μA POWER GOOD COMPARATOR Undervoltage Threshold VPWRGD(UV) Relative to nominal DAC output –180 –250 –300 mV Overvoltage Threshold VPWRGD(OV) Relative to nominal DAC output 90 150 200 mV Output Low Voltage VOL(PWRGD) I PWRGD(SINK) = 4 mA 225 400 mV Power Good Delay Time During Soft Start RDELAY = 250 kΩ, CDELAY = 12 nF , VID code = 011111 1 ms VID Code Changing 100 250 μs VID Code Static 200 ns Crowbar Trip Point VCROWBAR Relative to nominal DAC output 90 150 200 mV Crowbar Reset Point Relative to FBRTN 450 550 650 mV Crowbar Delay Time tCROWBAR Overvoltage to PWM going low VID Code Changing Blanking time 100 250 μs VID Code Static 400 ns PWM OUTPUTS Output Low Voltage VOL(PWM) I PWM(SINK) = –400 μA 160 500 mV Output High Voltage VOH(PWM) I PWM(SOURCE) = +400 μA 4.0 5 V SUPPLY—ADP3194 VSYSTEM = 12 V, RSHUNT = 300 Ω VCC VCC 4.75 5 V DC Supply Current 20 30 mA UVLO Threshold Voltage VUVLO VCC rising 6.3 7 8.0 V UVLO Hysteresis 0.9 V 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design, not production tested. 3 Relative current matching from each phase to the average of all four phases.

Rev. 0 | Page 5 of 32 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VCC –0.3 V to +6 V VID4 to VID0, VID5 –0.3 V to +6 V FBRTN –0.3 V to +0.3 V SW1 to SW4 −5 V to +25 V All Other Inputs and Outputs –0.3 V to VCC + 0.3 V Storage Temperature Range –65°C to +150°C Operating Ambient Temperature Range 0°C to +85°C Operating Junction Temperature 125°C Thermal Impedance (θJA) 100°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in co mbination. Unless otherwise specified, all other voltages are referenced to GND. ESD CAUTION

Figure 2. Pin Configuration Table 3. Pin Function Descriptions r PWM outputs and pulling the PWRGD output low. 7 FBRTN Feedback Return. VID DAC and error amplifier r eference for remote sensing of the output voltage. this pin and the output voltage sets the no-load offset point. 9 COMP Error Amplifier Output and C ompensation Point. 11 EN Power Supply Enable Input. Pulling this pin to GND d isables the PWM outputs and pulls the PWRGD output low. between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. currents together to measure the total output current. load line and the positioning loop response time. 19 GND Ground. All internal biasing and the logic output signals of the devic e are referenced to this ground. ADP3194 to operate as a 2-, 3-, or 4-phase controller. 28 VCC A 300 Ω resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V.

Rev. 0 | Page 8 of 32 THEORY OF OPERATION The ADP3194 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 6-bit VRD/VRM 10- and 10.1-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3194 ensures a stable, high pe rformance topology for

• Bal ancing currents and thermals between phases
• H igh speed response at the lowest possible switching frequency and output decoupling
• Minimizin g thermal switching losses due to lower frequency operation
• T ight load line regulation and accuracy
• H igh current output for up to 4-phase operation
• R educed output ripple due to multiphase cancellation
• PC b oard layout noise immunity
• E ase of use and design due to independent component selection
• Flexi bility in operation for tailoring design to low cost or high performance STARTUP SEQUENCE During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3194 operate as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation, and grounding the PWM3 pin and the PWM4 pin programs 2-phase operation. When the ADP3194 are enabled, the controller outputs a volt- age on PWM3 and PWM4, which is approximately 675 mV . An internal comparator checks each pin’s voltage vs. a threshold of 300 mV . If the pin is grounded, it is below the threshold, and the phase is disabled. The output resistance of the PWM pins is approximately 5 kΩ during this detection time. Any external pull-down resistance connected to the PWM pins should not be less than 25 kΩ to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval that occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 kΩ r esistance is removed and it switches between 0 V and 5 V . If the PWM output is grounded, it remains off. The PWM outputs are logic-level devices intended for driving external gate drivers, such as the ADP3120A. Because each phase is monitored inde- pendently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time for overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ADP3194 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phas e, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the fre- quency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3194 differential sense compares a high accuracy VID DAC and a precision reference to implement a low offset error amplifier. This maintains a worst-case specification of ±9.5 mV differential sensing error over their full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. Connect FB through a resistor to the regulation point, usually the remote sense pin of the microprocessor. Connect FBRTN directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3194 provide a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system: Output inductor DCR sensing without a thermistor for l owest cost, Output inductor DCR sensing with a thermistor for im proved accuracy with tracking of inductor temperature, Sense resistors for highest accuracy measurements.

Rev. 0 | Page 9 of 32 The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resis- tor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF − CSCOMP . This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors, so it can be made extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to equal the droop imped- ance of the regulator multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous imple- mentations and allows an enhanced feed-forward response. CURRENT-CONTROL MODE AND THERMAL BALANCE The ADP3194 has individual inputs for each phase, which are used for monitoring the current in each phase. This informa- tion is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal bal- ancing during operation. This current-balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. Resistor R SW1 through Resistor RSW4 (see the typical application circuit in Figure 19 and Figure 20) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure that place- holders are provided in the layout. To increase the current in any given phase, make RSW for this phase larger (make RSW = 0 for the hottest phase, and do not change during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. VOLTAGE CONTROL MODE A high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of the current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termi- nation voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor (R B) and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through R B is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP . SOFT START The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current-limit latch-off time. In UVLO, or when EN is logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is logic high, the DELAY capacitor is charged with an internal 20 μA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of the VID DAC and C DLY, with a secondary effect from RDLY. See the Application Information section for detailed information on setting CDLY. If EN is taken low or if VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft start cycle. Figure 7 shows a typical soft start sequence for the ADP3194.

Figure 7. Typical Start-Up Waveforms formation section discusses the selection of CDLY and RDLY. if the short is removed before the 1.8 V threshold is reached. (>1 MΩ) resistor should be connected from DELAY to VCC.

1.8 V t

internal 20 μA current source. the low-side MOSFETs through the current balance circuitry. Figure 8. Overcurrent Latch-Off Waveforms current to the load. This is commonly referred to as VID OTF. A VID OTF can occur under either light or heavy load conditions. change can be positive or negative. hange and ignores the DAC inputs for a minimum of 400 ns. event. Each VID change resets the internal timer.

Table 4. VID Codes for the ADP3194

Rev. 0 | Page 12 of 32 POWER GOOD MONITORING The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in Table 4. These limits are based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if all of the VID DAC inputs are high, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 250 μs to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time based on the DELAY ramp. The PWRGD pin is held low until the DELAY pin reaches 2.6 V . The time between when the PWRGD undervoltage threshold is reached and when the DELAY pin reaches 2.6 V provides the turn-on delay time. This time is incorporated into the soft start ramp. To ensure a 1 ms delay time on PWRGD, the soft start ramp must also be >1 ms. See the Application Information section for detailed information on setting C DLY. OUTPUT CROWBAR As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 550 mV . Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output over- voltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. OUTPUT ENABLE AND UVLO For the ADP3194 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is logic low, the ADP3194 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3120A drivers. Grounding ILIMIT disables the drivers so that both the DRVH and DRVL are also grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors.

Rev. 0 | Page 13 of 32

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10.1-compliant CPU application are as follows:

• Inp ut voltage (V IN) = 12 V
• VID s etting voltage (V VID) = 1.300 V
• Du ty cycle (D) = 0.108
• N ominal output voltage at no load (V ONL) = 1.281 V
• N ominal output voltage at 101 A load (V OFL) = 1.159 V
• S tatic output voltage drop based on a 1.2 mΩ load line (RO) from no load to full load (VD) = VONL − VOFL = 1.281 V − 1.159 V = 121.2 mV
• Ma ximum output current (I O) = 120 A
• M aximum output current step (ΔI O) = 85 A
• N umber of phases (n) = 4
• Sw itching frequency per phase (f SW) = 1.125 MHz SETTING THE CLOCK FREQUENCY The ADP3194 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and/or the input and output capaci- tors. With n = 4 for four phases, a clock frequency of 4 MHz sets the switching frequency (f SW) of each phase to 1 MHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 3 sho ws that to achieve 4 MHz oscillator frequency, the correct value for RT is 84 kΩ. 3 MHz oscillator frequency, the correct value for RT is 138 kΩ. 2 MHz oscillator frequency, the correct value for RT is 247 kΩ. Alternatively, the value for RT can be calculated using Ω −× ×= k 79pF 6 . 4 SW T f nR (1) where 4.6 pF and 79 kΩ are internal IC component values. For go od initial accuracy and frequency stability, a 1% resistor is recommended. SOFT START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES Because the soft start and current-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 μA internal current source. The value of R DLY has a second-order impact on the soft start time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 kΩ, this effect is minor. The value for CDLY can be approximated by VID SS DLY VID DLY V t R VC ×⎟⎟ ×− μ =2A 20 (2) where tSS is the desired soft start time. Assuming an RDLY of 390 kΩ and a desired soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY is chosen, RDLY can be calculated for the current-limit latch- off time by DLY DELAY DLY C tR ×= 96 . 1 (3) If the result for RDLY is less than 200 kΩ, a smaller soft start time should be considered by recalculating Equation 2, or a longer latch- off time should be used. RDLY should never be less than 200 kΩ. In this example, a delay time of 9 ms results in RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ. INDUCTOR SELECTION The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs; but it allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current a nd reduced conduction losses but requires larger inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. ( ) L f DVI SW VID R × − ×= 1 (4) Equation 5 can be used to determine the minimum inductance b ased on a given output ripple voltage. ( )( ) RIPPLESW OVID V f D n R VL × Solving Equation 5 for a 10 mV p-p output ripple voltage yields () nH 80 2mV 4 . 4 Hz M 125 . 1 108 . 0 1mΩ2 1. V 1.3 =× −××≥L If the resulting ripple voltage is less than it was designed for, make th e inductor smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling.

Rev. 0 | Page 14 of 32 The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 280 nH inductor is a good starting point and gives a calculated ripple current of 3.68 A. The inductor should not saturate at the peak current of 31.84 A and should be able to handle the sum of the power dissipation caused by the average current of 30 A in the winding and core loss. DESIGNING AN INDUCTOR Once the inductance is known, the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core ma terial. Several possibilities for providing low core loss at high frequencies include the powder cores (for example, Kool-Mμ® from Magnetics, Inc. or from Micrometals) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Avoid low frequency powdered iron cores due to their high core loss, espe- cially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type such a s a potentiometer core, PQ, U, or E core or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for q uickly designing a power inductor, such as Magnetic Designer Software™ by Intusoft and Designing Magnetic Components for High-Frequency DC-DC Converters, by William T . McLyman, KG Magnetics, Inc., ISBN 1883107008. Selecting a Standard Inductor Power inductor manufacturers can provide design consulta- tion and deliver power inductors optimized for high power applications upon request. Such manufacturers include Coilcraft, Coiltronics, Sumida Electric Company, and Vishay Intertechnology. SENSE RESISTOR A dedicated sense resistor can be used for current sensing. An advantage to this is the fact that there is much less temperature variation than using the DCR method. Therefore, a thermistor is not required. The trade-off is that a sense resistor is required for each phase. So, one thermistor is saved, but four sense resistors are needed in a four phase design. Also, there is extra power dissi- pation due to the sense resistor in series with the power delivery. SENSE RESISTOR SELECTION The resistance value of the sense resistor must be chosen to minimize the conduction loss, but be large enough for accurate current measurement. The lower the resistance, the lower the signal to noise ratio that appears at the ADP3194 input. This directly affects the current sense accuracy. A sense resistor of 1 mΩ is chosen. The power loss in the resistor is calculated as: SENSERS R I P× =2 (6) If the design has 30 A per phase, then: mW 900 Ω m 1 A 30 A 30=××=RSP This results in a 900mW conduction loss through the sense r esistor in a 30 A per phase design. Therefore, a 1 mΩ, 1 W sense resistor is chosen. There is a parasitic inductance (LP) associated with the sense resistor. This value can be found on the data sheet of the sense resistor. A typical value is of the order of 2.2 nH. OUTPUT DROOP RESISTANCE–SENSE RESISTOR The design requires the regulator output voltage measured at the CPU pins to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (R O). The output current is measured by summing the voltage across ea ch inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations: SENSE X PH CS O RR RR × = (7) CSSENSE P CS R R LC ×= (8) where RSENSE is the resistance of the sense resistor. The user has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 kΩ, and then solve for RPH(X) by rearranging Equation 6. CS O SENSE X PH RR RR × =) ( (9) kΩ5 . 82kΩ100mΩ2 . 1 mΩ0 . 1 ) ( = × =X PHR Next, use Equation 8 to solve for CCS. pF 220kΩ100mΩ0 . 1 nH 2 . 2 =×=CSC Therefore, set RCS equal to 100 kΩ, CCS equal to 220 pF, and RPH equal to 82.5 kΩ.

Rev. 0 | Page 16 of 32 COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Also, to determine what is required, use some simple design guidelines that are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capaci- ta nce. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18 of Size 1206 being the physical limit. Additional ceramic capacitors can be placed along the outer edge of the socket as well. Combined ceramic values of 200 μF to 400 μF are recommended, us ually made up of multiple 10 μF or 22 μF capacitors. Select the number of ceramic capacitors, and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bu lk capacitance (CX) when considering the VID OTF voltage stepping of the output (Voltage Step VV in Time tV with error of VERR). A lower limit is based on meeting the capacitance for load release for a given maximum load step, ∆IO, and a max- imum allowable overshoot. The total amount of load release voltage is given as ΔVO = ΔIO × RO + ΔVrl where ΔVrl is the maximum allowable overshoot voltage. ×⎟⎟ Δ Δ+ × Z VID O rl O O MIN X C VI VR n I LC Δ (11) Z O V VID V VID V O 2MAX X CL nKR V VtV V R nK LC − −⎟⎟ ⎛ × + × × = 11 ) ( (12) V ERR V Vn K1 where To meet the conditions of these equations and transient re sponse, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID OTF specification and may require the use of a smaller inductor or more phases (and may need the switching frequency to increase to keep the out-put ripple the same). This example uses 18, 22 μF 1206 MLC capacitors (C Z = 396 μF). The VID on-the-fly step change is 450 mV in 230 μs with a settling error of 2.5 mV . The maximum allowable load release overshoot for this example is 50 mV , so solving for the bulk capacitance yields mF 16 . 2 μF 396 V 3 . 185 mV 50mΩ2 . 1 4 A 85 nH 280 ) ( = ×⎟⎟ + × A C MIN X mF 5 . 40 μF 396 1nH 280 mV 450 mΩ2 . 1 6 . 4 4 V 3 . 1 μs 2501 V 3 . 1mΩ2 . 1 6 . 4 4 mV 450 nH 280 22) ( = − −⎟⎟ × × × ×+ ××× × ×≤MAX XC where K = 4.6. Using four 560 μF Al-Poly capacitors with a typical ESR of 5 mΩ eac h yields CX = 2.24 mF with an RX = 1.25 mΩ. One last check should be made to ensure that the ESL of the bu lk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using () nH 14 . 1 2mΩ2 . 1 μF 3962 = ×× ≤ × × ≤ X OZX L Q R C L (13) where Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is approximately 175 pH for the four A1-Polys capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capaci- tors may need to be increased if there is excessive ringing. For this multimode control techniq ue, all ceramic designs can be used as long as the conditions of Equation 11, Equation 12, and Equation 13 are satisfied.

Rev. 0 | Page 17 of 32 RAMP RESISTOR SELECTION The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following equation is used for determining the optimum value: kΩ118pF 5 Ω m 33 . 6 5 3 nH 0 28 0.2 =× × × × × × R RDSD R R R C R A L AR (14) where: AR is the internal ramp amplifier gain AD is the current balancing amplifier gain RDS is the total low-side MOSFET on resistance CR is the internal ramp capacitor value. The internal ramp voltage magnitude can be calculated by using () VV f C R V D AV R SWR R VIDR R m 0 5 3MHz 125 . 1 pF 5 Ω k 118 V 1.3 0.108 1 0.2 =× × × − ×= × × × − ×= (15) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of 3 in the denominator of Equation 14 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. COMP PIN RAMP A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: × × × × − ×− OXSW R RT R C f n D n VV 1 21 (16) In this example, the overall ramp signal is 390 mV . CURRENT-LIMIT SETPOINT To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3194 is set with a 3 V source (V LIM) across RLIM with a gain of 10.4 mV/μA (ALIM). RLIM can be found using OLIM LIMLIM LIM R I VAR × ×= (17) For values of RLIM greater than 500 kΩ, the current limit can be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, choosing a peak current limit of 185 A for ILIM results in RLIM = 140 kΩ. The limit of the per-phase current-limit described earlier is determined by () 2 R MAXDSD BIASRMAXCOMP PHLIM I R A V VV I +× − − ≅ (18) For the ADP3194, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V , the COMP pin bias voltage (VBIAS) is 1.2 V , and the current- balancing amplifier gain (AD) is 5. Using VR of 0.35 V and RDS(MAX) of 7 mΩ, the per-phase peak current limit is calculated to be 51.8 A. Although this number may seem high, this current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur. This limit can be adjusted by changing the ramp voltage (V R), but make sure not to set the per-phase limit lower than the average per-phase current (ILIM/n). The per-phase initial duty cycle limit is determined by RT BIASMAXCOMP MAX V VV D D × = (19) In this example, the maximum duty cycle is 0.46. FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3194 allows the best pos- sible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output imped- ance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (R O). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and allows minimization of the output decoupling.

Rev. 0 | Page 18 of 32 With the multimode feedback structure of the ADP3194, the feedback compensation must be set to make the converter’s output impedance, working in parallel with the output decoup- ling, to meet this goal. Several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for. A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 20 to Equation 28 yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Layout and Component Placement section). The first step is to compute the time constants for all of the poles and zeros in the system: VIDOX RT VID RTSENSE DSDOE V R C n V D n L V V RR A R n R × × × +×+ × + × = 1 2 (20) X O O X OXA R R R R ( ) XOX B C R R R T× −′+ = (22) E VID SW DSD RT C R V f R AL V T × ×− × (23) () OZOX OZX D R C R R C R C CT × + − × × ×= ' (24) where: R' is the PCB resistance from the bulk capacitors to the ceramics RDS is the total low-side MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.39 V , R' is approximately 0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and LX is 175 pH for the four Al-Poly capacitors. The compensation values can then be solved using the following equations: B E A O A R R T R nC × ××= (25) A C A C TR = (26) B B B R TC = (27) A D FB R TC = (28) These are the starting values, prior to tuning the design, to account for layout and other parasitic effects (see the Layout and Component Placement section). The final values selected after tuning are CA = 3.3 nF, RA = 7.32 kΩ, CB = 1 nF, CFB = 33 pF.

Rev. 0 | Page 20 of 32 TUNING THE ADP3194 1. Build a circuit based on the compensation values computed from the equations used in the example. 2. Hook up the dc load to circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. DC Load Line Setting 3. Measure the output voltage at no load (VNL). Verify it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2, using Equation 30 and Equation 31. () () FLHOTNL FLCOLDNL OLD CS2NEW CS2 V V VVRR − −×= (30) 5. Repeat Step 4 until the cold and hot voltage measurements remain the same. 6. Measure the output voltage from no load to full load, using 5 Amps steps. Compute the load line slope for each change, and then average to get the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mΩ, use the following to adjust the RPH values: () () O OMEAS OLD PHNEW PH R RRR × = (31) 8. Repeat Step 6 and Step 7 to check the load line, and repeat adjustments if necessary. 9. Once the dc load line adjustment is complete, do not change R PH, RCS1, RCS2, or RTH for the remainder of the procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. () () () C 25 1 °°° −×−+ × THTHOLD CS1NEW CS2OLD CS1THOLD CS1 THOLD CS1 NEW CS1 RR RR RRR RRR ( 3 2 )

DCR method instead of sense resistor method. while too small a value can lead to increased measurement error. needed for temperature changes of the inductor’s winding. of NTC thermistors, Resistor RCS1 and Resistor RCS2 are needed. Figure 18. Temperature Compensation Circuit Values RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. NTC should also have an initial tolerance of better than 5%. emperatures. The temperatures that work well are 50°C and 90°C. (RTH(90°C)/RTH(25°C)). The NTC’s relative value is always 1 at 25°C. chosen. From this, calculate that r1 = 0.9112 and r2 = 0.7978.

Rev. 0 | Page 24 of 32 OUTPUT DROOP RESISTANCE–DCR METHOD The design requires the regulator output voltage measured at the CPU pins to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). The output current is measured by summing the voltage across ea ch inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with RPH(X) (summers), RCS, and CCS (filter). The output resistance of the regulator is set by the following equations: L X PH CS O RR RR × = (40) CSL CS R R LC ×= (41) where RL is the DCR of the output inductors. The user has the flexibility of choosing either RCS or RPH(X). It is best to select RCS (equal to 100 kΩ) and then solve for RPH(X) by rearranging Equation 6. () CS O L XPH RR RR × = (42) () kΩ5 . 82kΩ100mΩ2 . 1 mΩ0 . 1 = × =X PHR Next, use Equation 41 to solve for CCS. nF 8 . 2Ω k 100 Ω m 0 . 1 nH 280 =×=CSC It is best to have a dual location for CCS in the layout, so that standard values can be used in parallel to get as close as possible to the value desired. For accuracy, C CS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of 2.2 nF and 560 pF in parallel. POWER MOSFETS This section is only applicable if power MOSFETs need to be selected. For this example, the N-channel power MOSFETs have been se lected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3120A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With V GATE ~10 V , logic-level threshold MOSFETs (VGS(TH)°< 2.5 V) are recommended. The maximum output current (IO) determine1s the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3194, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFET s (n SF). With conduction losses being dominant, the following equation shows the total power bein g dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO): () ()SF DS SF R SF O SF Rn I n n ID P × ⎛× +⎟⎟ ⎛× − = 11 (43) Knowing the maximum output current being designed for and t he maximum allowed power dissipation, it is possible to find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Thus, for this example (119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C, so be certain to account for this temperature when making this selection. This example uses two lower-side MOSFET s at 4.8 mΩ each at 120 °C. Another important factor for the synchronous MOSFET is the i nput capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should n ot exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3120A). The output impedance of the driver is approximately 2 Ω,and the typical MOSFET input gate resistances are about 1 Ωto 2 Ω, so a total gate capacitance of less than 6000 pF should be adhered to. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET has to be able to handle two ma in power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off and to the current and the voltage that are being switched. Basing the switching speed on the rise and fall time of the gate dr iver impedance and MOSFET input capacitance, the follow- ing equation provides an approximate value for the switching loss per main MOSFET: () ISS MF G MF O CC SWMFS Cn nRn where: nMF is the total number of main MOSFETs, RG is the total gate resistance (2 Ω for the ADP3120A and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω), CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not really help the switching loss per MOSFET because the additional gate capaci- tance slows switching. The best way to reduce switching loss is to use lower gate capacitance devices.

Rev. 0 | Page 25 of 32 The conduction loss of the main MOSFET is given by the following equation: () ()MF DS MF R MF MF C Rn I n nD P × ⎛× = O 1I (45) where RDS(MF) is the on resistance of the MOSFET. Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses. For this example, an NTD40N03L was selected as the main MOSFET (eight total; nMF = 8), with a CISS = 584 pF (maximum) and RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L was selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ (maximum at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. These numbers comply with the guideline to limit the power dissipation to 1 W per MOSFET. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the Q G for the MOSFETs and is given by the following equation: () CCCCGSFSFGMFMF SW DRV V I Q n Q nn fP × + × + × ××= 2 (45) where: QGMF is the total gate charge for each main MOSFET QGSF is the total gate charge for each synchronous MOSFET The standby dissipation factor for the driver is ICC × VCC. For the ADP3120A, the maximum dissipation should be less than 400 mW . In this example (with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC) 297 mW is found in each driver, which is below the 400 mW dissipation limit. See the ADP3120A data sheet for more details.

Rev. 0 | Page 26 of 32 LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal per- formance of a switching regulator in a PC system. GENERAL RECOMMENDATIONS For good results, a PCB with at least four layers is recom- mended. This allows the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output power; and wide inter- connection traces in the remainder of the power delivery current paths. Each square unit of 1 ounce copper trace has a resistance of 0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, vias sh ould be used liberally to create several parallel current paths. Then, the resistance and inductance introduced by these current paths is minimized, and the via current rating is not exceeded. If critical signal lines, including the output voltage sense lines of th e ADP3194, must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making the signal ground noisier. Use an analog ground plane around and under the ADP3194 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and not tied to any other power circuitry. This prevents power currents from flowing in the ground plane. Locate the components around the ADP3194 close to the con- t roller with short traces. The most important traces to keep short, and away from other traces, are the FB pin and the CSSUM pin. Connect the output capacitors as close as possible to the load (or connector), for example, a microprocessor core that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path lo op, as described in the Power Circuitry Recommendations secti on. POWER CIRCUITRY RECOMMENDATIONS The switching power path should be routed on the PCB to encom- pass the shortest possible length in order to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. Whenever a power dissipating component, (for example, a p ower MOSFET), is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. This improves current rating through the vias and also improves thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat-sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short d istance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should b e used as one of the inner layers extending fully under all the power components. SIGNAL CIRCUITRY RECOMMENDATIONS The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential-mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be Kelvin connected through a 10 Ω resistor to the center point of the copper bar, which is the V CORE common node for the inductors of all the phases (see Figure 19 and Figure 20).

3.9 K5 10

3.9 K6 9

3.9 K1 14

3.9 K2 13

Figure 19. Typical Applications Schematic Part 1

Figure 20. Typical Applications Schematic Part 2

1.20 MAX

6.40 BSC

Figure 21. 28-Lead Thin Shrink S mall Outline Package [TSSOP]

Rev. 0 | Page 30 of 32 NOTES

Rev. 0 | Page 31 of 32 NOTES

Rev. 0 | Page 32 of 32 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06022-0-10/06(0)