ADP3193A ONSEMI | Alldatasheet

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Technical content

8-Bit, Programmable, 2- to 3-Phase, Synchronous Buck Controller ADP3193A ©2008 SCILLC. All rights reserved. Publication Order Number: February 2008 – Rev. 1 ADP3193A/D

FEATURES

Selectable 2- or 3-phase operation at up to 1 MHz per phase ±7.7 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Fast enhanced PWM (FEPWM) flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.5 V to 1.6 V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for Next generation Intel® processors VRM modules GENERAL DESCRIPTION The ADP3193A1 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a

12 V main supply into the core supply voltage required by high

performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.5 V and 1.6 V . This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relation- ship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. The ADP3193A also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3193A also provides accurate and reliable short-circuit protection, adjustable current limiting, and delayed power-good output that accommodates on-the-fly output voltage changes requested by the CPU. 1 Protected by U.S. Patent Number 6,683,441; other patents pending. FUNCTIONAL BLOCK DIAGRAM SHUNT REGULATOR VC DAC DAC +150mV 850mV DAC –350mV CSREF 2-/3-PHASE DRIVER LOGIC ENSET14 UVLO SHUTDOWN BOOT VOLTAGE AND SOFT START CONTROL DELAY RESET RESET RESET VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ADP3193A CMP CMP CMP CROWBAR CURRENT LIMIT CURRENT MEASUREMENT AND LIMIT PRECISION REFERENCE 23 9 10 GND EN DELAY ILIMIT PWRGD COMP FBRTN VIDSEL IREF PWM2 PWM3 SW3 SW2 SW1 CSREF CSCOMP CSSUM FB PWM1 SS OD VCC RAMPADJRT CURRENT BALANCING CIRCUIT OSCILLATOR 06652-001 Figure 1. The ADP3193A has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3193A is specified over the extended commercial temperature range of 0°C to 85°C and is available in a 32-lead LFCSP .

Rev. 1 | Page 2 of 29 | www.onsemi.com TABLE OF CONTENTS

REVISION HISTORY

02/08—Rev 1: Conversion to ON Semiconductor 05/07—Revision 0: Initial Version

Rev. 1 | Page 3 of 29 | www.onsemi.com SPECIFICATIONS VCC = 5 V , FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter Symbol Conditions Min Typ Max Unit REFERENCE CURRENT Reference Bias Voltage V IREF 1.5 V Reference Bias Current I IREF R IREF = 100 kΩ 14.25 15 15.75 μA ERROR AMPLIFIER Output Voltage Range2 V COMP 0 4.4 V Accuracy V FB Relative to nominal DAC output, referenced to FBRTN (see Figure 4) −7.7 +7.7 mV V FB(BOOT) In startup 1.092 1.1 1.108 V Differential Nonlinearity −1 +1 LSB Input Bias Current I FB I FB = IIREF 13.5 15 16.5 μA FBRTN Current I FBRTN 65 200 μA Output Current I COMP FB forced to VOUT − 3% 500 μA Gain Bandwidth Product GBW (ERR) COMP = FB 20 MHz Slew Rate COMP = FB 25 V/μs Boot Voltage Hold Time t BOOT C DELAY = 10 nF 2 ms VID INPUTS Input Low Voltage V IL(VID) VID(x), VIDSEL 0.4 V Input High Voltage V IH(VID) VID(x), VIDSEL 0.8 V Input Current I IN(VID) −1 μA VID Transition Delay Time2 VID code change to FB change 400 ns No CPU Detection Turn-Off Delay Time2 VID code change to PWM going low 5 μs OSCILLATOR Frequency Range2 f OSC 0.25 4 MHz Frequency Variation f PHASE T A = 25°C, RT = 210 kΩ, 3-phase 240 260 293 kHz T A = 25°C, RT = 100 kΩ, 3-phase 530 kHz T A = 25°C, RT = 40 kΩ, 3-phase 1000 kHz Output Voltage V RT R T = 243 kΩ to GND 1.9 2.0 2.1 V RAMPADJ Output Voltage V RAMP ADJ RAMPADJ − FB −50 +50 mV RAMPADJ Input Current Range I RAMP ADJ 1 50 μA CURRENT SENSE AMPLIFIER Offset Voltage V OS(CSA) CSSUM − CSREF (see Figure 4) −1.0 +1.0 mV Input Bias Current I BIAS(CSSUM) −10 +10 nA Gain Bandwidth Product GBW (CSA) CSSUM = CSCOMP 10 MHz Slew Rate C CSCOMP = 10 pF 10 V/μs Input Common-Mode Range CSSUM and CSREF 0 3.5 V Output Voltage Range 0.05 3.5 V Output Current I CSCOMP 500 μA Current Limit Latch-Off Delay Time t OC(DELAY) C DELAY = 10 nF 8 ms CURRENT BALANCE AMPLIFIER Common-Mode Range V SW(x)CM −600 +200 mV Input Resistance R SW(x) SW(x) = 0 V 10 17 26 kΩ Input Current I SW(x) SW(x) = 0 V 8 12 20 μA Input Current Matching ΔISW(x) SW(x) = 0 V −4 +4 %

Rev. 1 | Page 4 of 29 | www.onsemi.com Parameter Symbol Conditions Min Typ Max Unit CURRENT LIMIT COMPARATOR ILIMIT Bias Current I ILIMIT I ILIMIT = 2/3 × IIREF 9 10 11 μA ILIMIT Voltage V ILIMIT RILIMIT = 121 kΩ (VILIMIT = (IILIMIT × RILIMIT)) 1.09 1.21 1.33 V Maximum Output Voltage 3 V Current-Limit Threshold Voltage V CL V CSREF − VCSCOMP, RILIMIT = 121 kΩ 80 100 125 mV Current-Limit Setting Ratio V CL/VILIMIT 82.6 mV/V DELAY TIMER Normal Mode Output Current I DELAY IDELAY = IIREF 12 15 18 μA Output Current in Current Limit I DELAY(CL) I DELAY(CL) = 0.25 × IIREF 3.0 3.75 4.5 μA Threshold Voltage V DELAY(TH) 1.6 1.7 1.8 V SOFT START Output Current I SS During startup, I SS = IIREF 12 15 18 μA ENABLE INPUT Threshold Voltage V TH(EN) 800 850 900 mV Hysteresis V HYS(EN) 80 100 125 mV Input Current I IN(EN) −1 μA Delay Time t DELAY(EN) EN > 950 mV, C DELAY = 10 nF 2 ms OD OUTPUT Output Low Voltage V OL(OD) 160 500 mV Output High Voltage V OH(OD) 4 5 V POWER-GOOD COMPARATOR Undervoltage Threshold V PWRGD(UV) Relative to nominal DAC output −400 −350 −300 mV Overvoltage Threshold V PWRGD(OV) Relative to nominal DAC output 100 150 200 mV Output Low Voltage V OL(PWRGD) I PWRGD(SINK) = −4 mA 150 300 mV Power-Good Delay Time During Soft Start2 C DELAY = 10 nF 2 ms VID Code Changing 100 250 μs VID Code Static 200 ns Crowbar Trip Point V CROWBAR Relative to nominal DAC output 100 150 200 mV Crowbar Reset Point Relative to FBRTN 320 375 430 mV Crowbar Delay Time t CROWBAR Overvoltage to PWM going low VID Code Changing 100 250 μs VID Code Static 400 ns PWM OUTPUTS Output Low Voltage V OL(PWM) I PWM(SINK) = −400 μA 160 500 mV Output High Voltage V OH(PWM) I PWM(SOURCE) = 400 μA 4.0 5 V SUPPLY V SYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 4) VCC2 VCC 4.65 5 5.55 V DC Supply Current I VCC VSYSTEM = 13.2 V, RSHUNT = 340 Ω 25 mA UVLO Turn-On Current 6.5 11 mA UVLO Threshold Voltage V UVLO VCC rising 9 V UVLO Turn-Off Voltage VCC falling 4.1 V 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production.

Rev. 1 | Page 5 of 29 | www.onsemi.com ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VCC −0.3 V to +6 V FBRTN −0.3 V to +0.3 V PWM1 to PWM3, RAMPADJ −0.3 V to VCC + 0.3 V SW1 to SW3 −5 V to +25 V <200 ns −10 V to +25 V All Other Inputs and Outputs −0.3 V to VCC + 0.3 V Storage Temperature Range −65°C to +150°C Operating Ambient Temperature Range 0°C to 85°C Operating Junction Temperature 125°C Thermal Impedance (θJA) 32.6°C/W Lead Temperature Soldering (10 sec) 300°C Infrared (15 sec) 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. ESD CAUTION

24 VID7

23 VCC

22 PWM1

21 PWM2

20 PWM3

19 SW1

18 SW2

17 SW3

  1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN

ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND. Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 2 PWRGD Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range. 3 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. and the output voltage sets the no load offset point. 5 COMP Error Amplifier Output and Compensation Point. 6 SS Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time. delay time, boot voltage hold time, EN delay time, and PWRGD delay time. 8 ILIMIT Current-Limit Set Point. An external resistor from this pin to GND sets the current-limit threshold of the converter. 10 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp . and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. to measure the total output current. current sense amplifier and the positioning loop response time. 14 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. 16 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for I FB, IDELAY, ISS, and IILIMIT. 20 to 22 PWM3 to PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A. shunt regulator maintains VCC = 5 V. in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4). extended VR10 or VR11 inputs.

Figure 3. Master Clock Frequency vs. RT

Rev. 1 | Page 10 of 29 | www.onsemi.com MASTER CLOCK FREQUENCY The clock frequency of the ADP3193A is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 3. If PWM3 is tied to VCC, divide the master clock by 2 for the frequency of the remaining phases. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3193A includes differential sensing, high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst-case specification of ±7.7 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. FB should be connected through a resistor to the regulation point, usually the remote sensing pin of the micro- processor. FBRTN should be connected directly to the remote sensing ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3193A provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sensing element, such as the low-side MOSFET. Depending on the objectives of the system, this amplifier can be configured in several ways:

  • Output inductor DCR sensing without a thermistor for lowest cost.
  • Output inductor DCR sensing with a thermistor for improved accuracy in tracking inductor temperature.
  • Sensing resistor for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. The difference between CSREF and CSCOMP is also used as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA has a low offset input voltage and the sensing gain is set by the external resistor. CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3193A has individual inputs (SW1 to SW3) for each phase that are used to monitor the current. This information is combined with an internal ramp to create a current-balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning, as described in the Output Current Sensing section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feedforward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an inten- tional current imbalance, such as when one phase has better cooling and can support higher currents. Resistors R SW1 through RSW3 (see Figure 10) can be used for adjusting thermal balance in this 3-phase example. It is best to have the ability to add these resistors during the initial design; therefore, ensure that place- holders are provided in the layout. To increase the current in any given phase, enlarge R SW for that phase (make RSW = 0 for the hottest phase, and do not change it during balancing). Increasing RSW to only 500 Ω results in a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. VOLTAGE CONTROL MODE A high gain, high bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor R B and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF) from the FB pin flowing through R B is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with

DELAY pin timing capacitor with the start-up sequence timing. the short is removed before the 1.7 V threshold is reached. increase in the delay times. Figure 9. Overcurrent Latch-Off Waveforms change can be positive or negative. change and ignores the DAC inputs for a minimum of 400 ns. event. Each VID change resets the internal timer. prevent false signals during the time the output is changing. PWRGD masking time finishing, the PWRGD pin is held low. voltage, the capacitor on the DELAY pin begins to charge. falls below the release threshold of approximately 300 mV . protecting the microprocessor from being destroyed.

less than its respective threshold, the ADP3193A is disabled. capacitors through the inductors. Table 4. VR11 and VR10.x VID Codes for the ADP3193A

Rev. 1 | Page 14 of 29 | www.onsemi.com VR11 DAC Codes: VIDSEL = Hi gh VR10.x DAC Codes: VIDSEL = Low Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6 1 . 3 2 5 0 0 0 0 1 01 1 101010 1 11 1 . 3 1 8 7 5 0 0 1 01 1 111010 1 10 1 . 3 1 2 5 0 0 0 1 10 0 001011 0 01 1 . 3 0 6 2 5 0 0 1 10 0 011011 0 00 1 . 3 0 0 0 0 0 0 1 10 0 101011 0 11 1 . 2 9 3 7 5 0 0 1 10 0 111011 0 10 1 . 2 8 7 5 0 0 0 1 10 1 001011 1 01 1 . 2 8 1 2 5 0 0 1 10 1 011011 1 00 1 . 2 7 5 0 0 0 0 1 10 1 101011 1 11 1 . 2 6 8 7 5 0 0 1 10 1 111011 1 10 1 . 2 6 2 5 0 0 0 1 11 0 001100 0 01 1 . 2 5 6 2 5 0 0 1 11 0 011100 0 00 1 . 2 5 0 0 0 0 0 1 11 0 101100 0 11 1 . 2 4 3 7 5 0 0 1 11 0 111100 0 10 1 . 2 3 7 5 0 0 0 1 11 1 001100 1 01 1 . 2 3 1 2 5 0 0 1 11 1 011100 1 00 1 . 2 2 5 0 0 0 0 1 11 1 101100 1 11 1 . 2 1 8 7 5 0 0 1 11 1 111100 1 10 1 . 2 1 2 5 0 0 1 0 00 0 001101 0 01 1 . 2 0 6 2 5 0 1 0 00 0 011101 0 00 1 . 2 0 0 0 0 0 1 0 00 0 101101 0 11 1 . 1 9 3 7 5 0 1 0 00 0 111101 0 10 1 . 1 8 7 5 0 0 1 0 00 1 001101 1 01 1 . 1 8 1 2 5 0 1 0 00 1 011101 1 00 1 . 1 7 5 0 0 0 1 0 00 1 101101 1 11 1 . 1 6 8 7 5 0 1 0 00 1 111101 1 10 1 . 1 6 2 5 0 0 1 0 01 0 001110 0 01 1 . 1 5 6 2 5 0 1 0 01 0 011110 0 00 1 . 1 5 0 0 0 0 1 0 01 0 101110 0 11 1 . 1 4 3 7 5 0 1 0 01 0 111110 0 10 1 . 1 3 7 5 0 0 1 0 01 1 001110 1 01 1 . 1 3 1 2 5 0 1 0 01 1 011110 1 00 1 . 1 2 5 0 0 0 1 0 01 1 101110 1 11 1 . 1 1 8 7 5 0 1 0 01 1 111110 1 10 1 . 1 1 2 5 0 0 1 0 10 0 001111 0 01 1 . 1 0 6 2 5 0 1 0 10 0 011111 0 00 1 . 1 0 0 0 0 0 1 0 10 0 101111 0 11 1 . 0 9 3 7 5 0 1 0 10 0 111111 0 10 O f f N / A 1111 1 01 O f f N / A 1111 1 00 O f f N / A 1111 1 11 O f f N / A 1111 1 10 1 . 0 8 7 5 0 0 1 0 10 1 000000 0 01 1 . 0 8 1 2 5 0 1 0 10 1 010000 0 00 1 . 0 7 5 0 0 0 1 0 10 1 100000 0 11 1 . 0 6 8 7 5 0 1 0 10 1 110000 0 10 1 . 0 6 2 5 0 0 1 0 11 0 000000 1 01 1 . 0 5 6 2 5 0 1 0 11 0 010000 1 00 1 . 0 5 0 0 0 0 1 0 11 0 100000 1 11 1 . 0 4 3 7 5 0 1 0 11 0 110000 1 10 1 . 0 3 7 5 0 0 1 0 11 1 000001 0 01 1 . 0 3 1 2 5 0 1 0 11 1 010001 0 00 1 . 0 2 5 0 0 0 1 0 11 1 100001 0 11 1 . 0 1 8 7 5 0 1 0 11 1 110001 0 10 1 . 0 1 2 5 0 0 1 1 00 0 000001 1 01 1 . 0 0 6 2 5 0 1 1 00 0 010001 1 00 1 . 0 0 0 0 0 0 1 1 00 0 100001 1 11 0 . 9 9 3 7 5 0 1 1 00 0 110001 1 10

Rev. 1 | Page 15 of 29 | www.onsemi.com VR11 DAC Codes: VIDSEL = Hi gh VR10.x DAC Codes: VIDSEL = Low Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6 0 . 9 8 7 5 0 0 1 1 0 0 100001 0 0 01 0 . 9 8 1 2 5 0 1 1 0 0 101001 0 0 00 0 . 9 7 5 0 0 0 1 1 0 0 110001 0 0 11 0 . 9 6 8 7 5 0 1 1 0 0 111001 0 0 10 0 . 9 6 2 5 0 0 1 1 0 1 000001 0 1 01 0 . 9 5 6 2 5 0 1 1 0 1 001001 0 1 00 0 . 9 5 0 0 0 0 1 1 0 1 010001 0 1 11 0 . 9 4 3 7 5 0 1 1 0 1 011001 0 1 10 0 . 9 3 7 5 0 0 1 1 0 1 100001 1 0 01 0 . 9 3 1 2 5 0 1 1 0 1 101001 1 0 00 0 . 9 2 5 0 0 0 1 1 0 1 110001 1 0 11 0 . 9 1 8 7 5 0 1 1 0 1 111001 1 0 10 0 . 9 1 2 5 0 0 1 1 1 0 000001 1 1 01 0 . 9 0 6 2 5 0 1 1 1 0 001001 1 1 00 0 . 9 0 0 0 0 0 1 1 1 0 010001 1 1 11 0 . 8 9 3 7 5 0 1 1 1 0 011001 1 1 10 0 . 8 8 7 5 0 0 1 1 1 0 100010 0 0 01 0 . 8 8 1 2 5 0 1 1 1 0 101010 0 0 00 0 . 8 7 5 0 0 0 1 1 1 0 110010 0 0 11 0 . 8 6 8 7 5 0 1 1 1 0 111010 0 0 10 0 . 8 6 2 5 0 0 1 1 1 1 000010 0 1 01 0 . 8 5 6 2 5 0 1 1 1 1 001010 0 1 00 0 . 8 5 0 0 0 0 1 1 1 1 010010 0 1 11 0 . 8 4 3 7 5 0 1 1 1 1 011010 0 1 10 0 . 8 3 7 5 0 0 1 1 1 1 100010 1 0 01 0 . 8 3 1 2 5 0 1 1 1 1 101010 1 0 00 0.82500 0 1 1 1 1 1 1 0 N/A 0.81875 0 1 1 1 1 1 1 1 N/A 0.81250 1 0 0 0 0 0 0 0 N/A 0.80625 1 0 0 0 0 0 0 1 N/A 0.80000 1 0 0 0 0 0 1 0 N/A 0.79375 1 0 0 0 0 0 1 1 N/A 0.78750 1 0 0 0 0 1 0 0 N/A 0.78125 1 0 0 0 0 1 0 1 N/A 0.77500 1 0 0 0 0 1 1 0 N/A 0.76875 1 0 0 0 0 1 1 1 N/A 0.76250 1 0 0 0 1 0 0 0 N/A 0.75625 1 0 0 0 1 0 0 1 N/A 0.75000 1 0 0 0 1 0 1 0 N/A 0.74375 1 0 0 0 1 0 1 1 N/A 0.73750 1 0 0 0 1 1 0 0 N/A 0.73125 1 0 0 0 1 1 0 1 N/A 0.72500 1 0 0 0 1 1 1 0 N/A 0.71875 1 0 0 0 1 1 1 1 N/A 0.71250 1 0 0 1 0 0 0 0 N/A 0.70625 1 0 0 1 0 0 0 1 N/A 0.70000 1 0 0 1 0 0 1 0 N/A 0.69375 1 0 0 1 0 0 1 1 N/A 0.68750 1 0 0 1 0 1 0 0 N/A 0.68125 1 0 0 1 0 1 0 1 N/A 0.67500 1 0 0 1 0 1 1 0 N/A 0.66875 1 0 0 1 0 1 1 1 N/A 0.66250 1 0 0 1 1 0 0 0 N/A 0.65625 1 0 0 1 1 0 0 1 N/A 0.65000 1 0 0 1 1 0 1 0 N/A 0.64375 1 0 0 1 1 0 1 1 N/A 0.63750 1 0 0 1 1 1 0 0 N/A 0.63125 1 0 0 1 1 1 0 1 N/A

Rev. 1 | Page 16 of 29 | www.onsemi.com VR11 DAC Codes: VIDSEL = Hi gh VR10.x DAC Codes: VIDSEL = Low Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6 0.62500 1 0 0 1 1 1 1 0 N/A 0.61875 1 0 0 1 1 1 1 1 N/A 0.61250 1 0 1 0 0 0 0 0 N/A 0.60625 1 0 1 0 0 0 0 1 N/A 0.60000 1 0 1 0 0 0 1 0 N/A 0.59375 1 0 1 0 0 0 1 1 N/A 0.58750 1 0 1 0 0 1 0 0 N/A 0.58125 1 0 1 0 0 1 0 1 N/A 0.57500 1 0 1 0 0 1 1 0 N/A 0.56875 1 0 1 0 0 1 1 1 N/A 0.56250 1 0 1 0 1 0 0 0 N/A 0.55625 1 0 1 0 1 0 0 1 N/A 0.55000 1 0 1 0 1 0 1 0 N/A 0.54375 1 0 1 0 1 0 1 1 N/A 0.53750 1 0 1 0 1 1 0 0 N/A 0.53125 1 0 1 0 1 1 0 1 N/A 0.52500 1 0 1 0 1 1 1 0 N/A 0.51875 1 0 1 0 1 1 1 1 N/A 0.51250 1 0 1 1 0 0 0 0 N/A 0.50625 1 0 1 1 0 0 0 1 N/A 0.50000 1 0 1 1 0 0 1 0 N/A O f f 1 1 1 11 1 101111 1 10 O f f 1 1 1 11 1 111111 1 11

*FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. **CONNECT NEAR EACH INDUCTOR. Figure 10. Typical 3-Phase Application Circuit

Rev. 1 | Page 18 of 29 | www.onsemi.com

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 11 compliant CPU application are as follows:

  • Input voltage (VIN) = 12 V
  • VID setting voltage (VVID) = 1.400 V
  • Duty cycle (D) = 0.117
  • Nominal output voltage at no load (VONL) = 1.381 V
  • Nominal output voltage at 65 A load (VOFL) = 1.316 V
  • Static output voltage drop based on a 1.0 mΩ load line (RO) from no load to full load (VD) = VONL − VOFL = 1.381 V − 1.316 V = 65 mV
  • Maximum output current (IO) = 65 A
  • Maximum output current step (ΔIO) = 50 A
  • Maximum output current slew rate (SR) = 200 A/μs
  • Number of phases (n) = 3
  • Switching frequency per phase (fSW) = 330 kHz SETTING THE CLOCK FREQUENCY The ADP3193A uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses as well as to the sizes of the inductors, the input capacitors, and the output capacitors. With n = 3 for three phases, a clock frequency of 990 kHz sets the switching frequency (f SW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 3 shows that to achieve a 990 kHz oscillator frequency, the correct value for R T is 169 kΩ (closest 1% resistor is 169 kΩ). Alternatively, the value for RT can be calculated using pF6 ××= SW T fnR (1) where 6 pF is the internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. SOFT START DELAY TIME The value of CSS sets the soft start time. The ramp is generated with a 15 μA internal current source. The value for CSS can be found using BOOT SS V TDC 2A15 ×μ= (2) where TD2 is the desired soft start time, and VBOOT is internally set to 1.1 V . Assuming a desired TD2 time of 1.4 ms, CSS is 19 nF . The closest standard value for CSS is 18 nF. Although CSS also controls the time delay for TD4 (determined by the final VID voltage), the minimum specification for TD4 is 0 ns. This means that as long as the TD2 time requirement is met, TD4 is within the specification. CURRENT-LIMIT LATCH-OFF DELAY TIMES The start-up and current-limit delay times are determined by the capacitor connected to the DELAY pin. The first step is to set CDLY for the TD1, TD3, and TD5 delay times (see Figure 7). The DELAY ramp (IDELAY) is generated using a 15 μA internal current source. The value for CDLY can be approximated using THDELAY DELAYDLY V xTDIC ×= (3) where: TD(x) is the desired delay time for TD1, TD3, and TD5. VDELAY(TH) is the DELAY threshold voltage and is given as 1.7 V . In this example, 2 ms is chosen for all three delay times, which meets Intel specifications. Solving for CDLY results in a value of 17.6 nF . The closest standard value for CDLY is 18 nF . When the ADP3193A surpasses the current limit, the internal current source changes from 15 μA to 3.75 μA. As a result, the latch-off delay time becomes four times longer than the start-up delay time. Note that longer latch-off delay times can be achieved by placing a resistor in parallel with C DLY. INDUCTOR SELECTION The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, using smaller inductors allows the converter to meet a specified peak-to-peak transient deviation with less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but more output capacitance is required to meet the same peak-to- peak transient deviation. In any multiphase converter, a practical value for the peak-to- peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. Lf DVI SW VID R −×= 1 (4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. ()() RIPPLESW OVID Vf DnRVL ×

Rev. 1 | Page 19 of 29 | www.onsemi.com Solving Equation 5 for an output ripple voltage of 10 mV p-p yields () nH762mV10kHz330 350.1mΩ1.0V41. =× −××≥L If the resulting ripple voltage is less than what is designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 320 nH inductor is a good choice for a starting point, and it provides a calculated ripple current of 11.7 A. The inductor should not saturate at the peak current of 27.6 A, and it should be able to handle the sum of the power dissipation caused by the average current of 21.7 A in the winding and core loss. Another important factor in the inductor design is the dc resistance (DCR), which is used for measuring the phase currents. Too large of a DCR causes excessive power losses, whereas too small of a value leads to increased measurement error. A good rule is to have the DCR (R L) be about 1× to 1½× the droop resistance (RO). This example uses an inductor with a DCR of 1.4 mΩ. Designing an Inductor After the inductance and DCR are known, the next step is either to design an inductor or to find a standard inductor that best meets the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. Reasonable tolerances that most manufacturers can meet are 20% inductance and 7% DCR at room temperature. The first decision in designing the inductor is choosing the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (from Micrometals, Inc., for example, or Kool-Mu® from Magnetics®) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type of inductor, such as a potentiometer core; a PQ, U, or E core; or a toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as

  • Magnetic Designer Software from Intusoft
  • Designing Magnetic Components for High Frequency DC- DC Converters, by William T. McLyman, K G Magnetics, Inc., ISBN 1883107008 Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and upon request deliver power inductors optimized for high power applications.
  • Coilcraft, Inc.
  • Coiltronics
  • Sumida Corporation CURRENT SENSE AMPLIFIER Most designs require the regulator output voltage measured at the CPU pins to droop when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO), also referred to as a load line. The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with Resistor RPH(x) (summer) and Resistors RCS and CCS (filters). The impedance gain of the regulator is set by the following equations, where RL is the DCR of the output inductors: L xPH CS O RR RR ×= (6) CSL CS RR LC ×= (7) The user has the flexibility to choose either RCS or RPH(x). However, it is best to select RCS equal to 100 kΩ, and then solve for RPH(x) by rearranging Equation 6. In the following example, RO = 1 mΩ to equal the design load line. () Ωk140Ωk100mΩ0.1 Ωm4.1 =×= xPH CS O L xPH R RR RR Next, use Equation 7 to solve for CCS. nF82.2Ωk100Ωm4.1 nH320 =×=CSC It is best to include two locations for CCS in the layout so that standard values can be used in parallel to better achieve the desired value. For best accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of two 1 nF capacitors in parallel. Recalculating RCS and RPH(x) using this capacitor combination yields 114 kΩ and 160 kΩ. The closest standard 1% value for R PH(x) is 158 kΩ.

compensate for temperature changes of the inductor’s winding. produce the desired temperature tracking. Figure 11. Temperature-Compensation Circuit Values

  1. Select an NTC based on type and value. Because the value

NTC should also have an initial tolerance of better than 5%.

  1. Based on the type of NTC, find its relative resistance value

value of the NTC is always 1 at 25°C.

  1. Find the relative value of RCS required for each of these
  2. Compute the relative values for RCS1, RCS2, and RTH using
  3. Calculate values for RCS1 and RCS2 using Equation 12 and

yields a choice of 35.7 kΩ and 88.7 kΩ. The closest standard 1% resistor value is 1.27 kΩ.

Rev. 1 | Page 21 of 29 | www.onsemi.com COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Use some simple design guidelines to determine the require- ments. These guidelines are based on having both bulk capacitors and ceramic capacitors in the system. First, select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with twelve to eighteen 1206-size pieces being the physical limit. Other capacitors can be placed along the outer edge of the socket as well. To determine the minimum amount of ceramic capacitance required, start with a worst-case load step that occurs immediately after a switching cycle has stopped. The ceramic capacitance then delivers the charge to the load while the load is ramping up until the VR responds with the next switching cycle. Equation 15 provides the designer with a rough approximation for determining the minimum ceramic capacitance. Due to the complexity of the PCB parasitics and bulk capacitors, the actual amount of ceramic capacitance required can vary. ⎡ Δ−⎟⎠ ⎞⎜⎝ R O SWO MINZ S IDnfRC 2 )( (15) The typical ceramic capacitors consist of multiple 10 μF or 22 μF capacitors. For this example, Equation 15 yields 265 μF , so twenty-six 10 μF ceramic capacitors suffice. Next, there is an upper limit imposed on the total amount of bulk capacitance (CX), considering the VID on-the-fly voltage stepping of the output (voltage step, VV, in time, tV, with error of VERR). A lower limit is based on meeting the capacitance for load release at a given maximum load step (ΔIO) and a maximum allowable overshoot. The total amount of load release voltage is ΔVO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum allowable overshoot voltage. ×⎟⎟ Δ Δ+× ×≥ Z VID O rl O O MINX C VI VRn ILC Δ (16) () Z O V VID V VID V O 2MAXX CL nKR V VtV V Rnk LC − −⎟⎟ (17) where ⎟⎟ ⎛−= V ERR V Vk ln . To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and to maintain the output ripple may require the use of a smaller inductor or more phases (in addition to increasing the switching frequency). This example uses twenty-six 10 μF 1206 MLC capacitors Z = 260 μF). The VID on-the-fly step change is 450 mV in 230 μs with a settling error of 2.5 mV . The maximum allowable load release overshoot for this example is 50 mV; therefore, solving for the bulk capacitance yields () mF64.1μF260 V4.1A50 mV50mΩ0.13 A50nH320 = ×⎟⎟ MINXC () () ×××× ×≤ V4.1Ωm0.12.53 mV450nH320 22MAXXC mF 42.7 μF2601nH320mV450 Ωm01253V41μs2301 −⎟⎟ ××××+ ... where k = 5.2. Using eight 560 μF aluminum-poly capacitors with a typical ESR of 6 mΩ each yields CX = 4.48 mF with an RX = 0.75 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using () pH3473 4mΩ1μF260 2 =××≤ ××≤ X 22OZX L QRCL (18) where Q2 is limited to 4/3 to ensure a critically damped system. In this example, LX is approximately 240 pH for the eight aluminum-poly capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors needs to be increased, or lower ESL bulks need to be used if there is excessive undershoot during a load transient. For this multimode control technique, all ceramic designs can be used if the conditions of Equation 15 through Equation 18 are satisfied.

Rev. 1 | Page 22 of 29 | www.onsemi.com POWER MOSFETS For our example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are V GS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3120A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V , logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3193A, currents are balanced between phases; therefore, the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (n SF). With conduction losses being dominant, Equation 19 shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO): () ()SFDS SF R SF O SF Rn In n IDP × ⎛×+⎟⎟ ⎛×−= 11 (19) Knowing the maximum output current being designed for and the maximum allowed power dissipation, the user can find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Therefore, for this example (56 A maximum), RDS(SF) (per MOSFET) is less than 4.7 mΩ. This RDS(SF) is also at a junction temperature of about 120°C. As a result, users need to account for this when making this selection. This example uses two low-side MOSFET s at 4.8 mΩ, each at 120°C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to the input must be small (less than 10% is recom- mended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. In addition, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (45 ns typical for the ADP3120A). The output impedance of the driver is approximately 2 Ω, and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω. Therefore, a total gate capacitance of less than 6000 pF should be adhered to. Because two MOSFETs are in parallel, the input capacitance for each synchronous MOSFET should be limited to 6000 pF . The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET: () ISS MF G MF OCC SWMFS Cn nRn where: nMF is the total number of main MOSFETs. RG is the total gate resistance (2 Ω for the ADP3120A and about 1 Ω for typical high speed switching MOSFET s, making RG = 3 Ω). CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not help the switching loss per MOSFET because the additional gate capacitance slows switching. Use lower gate capacitance devices to reduce switching loss. The conduction loss of the main MOSFET is given by the following: () ()MFDS MF R MF O MFC Rn In n IDP × ⎛×= 1 (21) where RDS(MF) is the on resistance of the MOSFET. Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but such devices usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD40N03L is selected as the main MOSFET (three total, nMF = 3), with CISS = 584 pF (maximum) and RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L is selected as the synchronous MOSFET (three total, nSF = 3), with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ (maximum at TJ = 120°C). The synchronous MOSFET CISS is less than 6000 pF , satisfying this requirement. Solving for the power dissipation per MOSFET at IO = 56 A and IR = 11.7 A yields 1.53 W for each synchronous MOSFET and 1.06 W for each main MOSFET. As a guide, limit the MOSFET power dissipation to 1.5 W . The values calculated in Equation 20 and Equation 21 will comply with this guideline. Finally, consider the power dissipation in the driver for each phase. This is best expressed as QG for the MOSFETs and is given by Equation 22. () CCCCGSFSFGMFMF SW DRV VIQnQnn fP × +×+×××= 2 (22) where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET

Rev. 1 | Page 23 of 29 | www.onsemi.com Also shown is the standby dissipation factor (ICC × VCC) of the driver. For the ADP3120A, the maximum dissipation should be less than 400 mW . In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, there is 191 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3120A data sheet for more details. RAMP RESISTOR SELECTION The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor should be chosen to provide the best combination of thermal balance, stability, and transient response. Equation 23 is used for determining the optimum value. RDSD R R CRA LAR ××× (23) kΩ178pF5Ωm8.453 nH3200.2 =××× ×=RR where: AR is the internal ramp amplifier gain. AD is the current-balancing amplifier gain. RDS is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. The internal ramp voltage magnitude can be calculated as follows: SWRR VIDR R fCR VDAV ×× ×−×= 1 (24) Vm842kHz330pF5Ωk178 V41.170.110.2 =×× ×−×=RV The size of the internal ramp can be increased or decreased. If it is increased, stability and noise rejection improve, but the transient response degrades. Conversely, if the ramp size is decreased, the transient response improves, but noise rejection and stability degrade. In the denominator of Equation 23, the factor of 3 sets a ramp size that produces an optimal balance for good stability, transient response, and thermal balance. COMP PIN RAMP In addition to the internal ramp, there is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: ××× ×−×− OXSW R RT RCfn Dn VV 121 (25) In this example, the overall ramp signal is 1.19 V . However, if the ramp size is smaller than 0.5 V , increase the ramp size to be at least 0.5 V by decreasing the ramp resistor for noise immunity. CURRENT-LIMIT SETPOINT To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3193A is set with a constant current source flowing out of the ILIMIT pin, which sets up a voltage (V LIM) across RLIM with a gain of 82.6 mV/V (ALIM). Therefore, increasing RLIM now increases the current limit. RLIM can be found using the following equation: REF CSALIM ILIMITLIM CL LIM RRI IA In this equation, ILIM is the peak average current limit for the supply output and is equal to the dc current limit plus the output ripple current. In this example, choosing a dc current limit of 88.3 A and having a ripple current of 11.7 A yields an I LIM of 100 A, resulting in an RLIM of 121 kΩ, for which 121 kΩ is chosen as the nearest 1% value. The per-phase initial duty cycle limit and peak current during a load step are determined by RT BIASMAXCOMP MAX V VV DD ×= (27) L VV f DI VIDIN SW MAX PHMAX −×≅ (28) For the ADP3193A, the maximum COMP voltage (VCOMP(MAX)) is 3.4 V , and the COMP pin bias voltage (VBIAS) is 1.1 V . In this example, the maximum duty cycle is 0.23. Because this is small due to the VRT being much larger than 0.5 V, reduce the ramp resistor to get closer to 0.5 V VRT and to obtain a larger duty cycle. Choosing a ramp resistor of 267 kΩ results in a VRT of 0.79 V, a DMAX of 0.34, and a peak current of 34 A. The limit of the peak per-phase current during the secondary current limit is determined by ()MAXDSD BIASCLAMPEDCOMP PHLIM RA VV I × ≅ (29) For the ADP3193A, the current balancing amplifier gain (AD) is 5 and the clamped COMP pin voltage is 2 V . Using an RDS(MAX) of 5.6 mΩ (low-side on resistance at 150°C) results in a per-phase peak current limit of 36 A. This current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur.

Rev. 1 | Page 24 of 29 | www.onsemi.com FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3193A allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (R O). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and minimizes the output decoupling. Because of the multimode feedback structure of the ADP3193A, it is necessary to set the feedback compensation so that the converter output impedance works in parallel with the output decoupling to make the load look entirely resistive. In addition, it is necessary to compensate for several poles and zeros created by the output inductor and the decoupling capacitors (output filter). A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 30 to Equation 34 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for ADP3193A section). First, compute the time constants for all the poles and zeros in the system using Equation 30 to Equation 34. ( ) VIDOX RT VID RTL DSDOE VRCn VDnL V VRRARnR ××× Ωm3.45V41.Ωm1mF48.43 V790.350.1nH3202 V41. V790.Ωm1.4Ωm8.45Ωm13 =××× () () μs47.2Ωm750. Ωm0.5Ωm1 Ωm1 X O O X OXA R RR R LRRCT (31) ( ) ( ) ns0112mF48.4Ωm1Ωm0.5Ωm750.' =×−+=×−+= XOXB CRRRT (32) μs53.3Ωm3.45V41. kHz3302 Ωm8.45nH320V790.2 ×−× ×−× EVID SW DSD RT C RV f RALV T (33) () ns466Ωm1μF026Ωm0.5Ωm1mF48.4 Ωm1μF026mF48.4 =×+−× ××= OZOX OZX D RCRRC RCCT (34) where: R' is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.5 mΩ (assuming a 4-layer, 1 oz motherboard). RDS is the total low-side MOSFET on resistance per phase. AD = 5. VRT = 0.79 V . LX = 347 pH for the eight aluminum-poly capacitors. The compensation values can then be solved using pF128Ωk271.Ωm3.45 μs47.2Ωm13 =× ××=× ××= BE AO A RR TRnC (35) Ωk5.27pF128 μs53.3 === A C A C TR (36) pF882Ωk271. ns1120 === B B B R TC (37) pF9.16Ωk5.27 ns466 === A D FB R TC (38) These equations result in the starting values prior to tuning the design that account for layout and other parasitic effects (see the Tuning Procedure for ADP3193A section). The final values selected after tuning are CA = 220 pF RA = 22.1 kΩ CB = 560 pF CFB = 15 pF

  1. Build a circuit based on the compensation values

computed from the design spreadsheet.

  1. Connect a dc load to the circuit.
  2. Turn on the ADP3193A and verify that it operates properly.
  3. Check for jitter with no load and full load conditions.
  4. Measure the output voltage with no load (VNL) and verify

that it is within the specified tolerance range.

  1. Measure the output voltage with a full load when the

and RCS2 using Equation 41 and Equation 43.

  1. Repeat Step 2 until no adjustment of RCS1 and RCS2 is needed.
  2. Compare the output voltage with no load to that with a full

overall load line slope (ROMEAS).

  1. If the difference between ROMEAS and RO is more than 0.05 mΩ,

use Equation 42 to adjust the RPH values.

  1. Repeat Step 6 and Step 7 until no adjustment of RPH is needed.

for the remainder of the procedure.

  1. Measure the output ripple with no load and with a full load

with scope, making sure both are within specifications.

  1. Remove the dc load from the circuit and connect the
  2. Connect the scope to the output voltage and set it to dc-

coupling mode with the time scale of 100 μs/div.

  1. Set the dynamic load for a transient step of about 40 A at
  2. Measure the output waveform. (Note that use of a dc offset

should look similar to Figure 15. Figure 15. AC Load Line Waveform

  1. Use the horizontal cursors to measure VACDRP and VDCDRP,

overshoot that occurs immediately after this step.

  1. If the difference between VACDRP and VDCDRP is more than a

in the layout for this reason.

  1. Repeat Step 5 and Step 6 until no further adjustment of CCS
  2. Set the dynamic load step to its maximum step size (but do
  3. With the dynamic load set at the maximum step size,

expand the scope time scale to either 2 μs/div or 5 μs/div.

Rev. 1 | Page 28 of 29 | www.onsemi.com Power Circuitry Recommendations The switching power path on the PCB should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power-converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. When a power-dissipating component, such as a power MOSFET, is soldered to a PCB, it is recommended to use vias liberally both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image on the opposite side of the PCB of any pad being used to heat-sink the MOSFETs. This helps achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest pad area possible. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers, extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB and FBRTN pins, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Therefore, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor, and the CSREF signal should be connected to the output voltage at the nearest inductor to the controller.

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.80 SEATING

3.50 REF

0.60 MAX

0.25 MIN

Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.