ADP3190JRUZ-RL

ADP3190 AD | Alldatasheet

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Technical content

6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller ADP3190

FEATURES

Selectable 2-, 3-, or 4-phase operation at up to

1 MHz per phase

±9.5 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers PWM Flex-ModeTM architecture for excellent load transient performance Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes 6-bit digitally programmable 0.8375 V to 1.6 V output Programmable short circuit protection with programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for Next-generation Intel® processors VRM modules Games consoles GENERAL DESCRIPTION The ADP3190/ADP3190A1 are highly efficient, multiphase, synchronous buck switching regulator controllers optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high performance Intel processors. They use an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6 V . The devices use a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3190/ADP3190A also include programmable, no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is always optimally positioned for a system transient. The ADP3190/ADP3190A also provide accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. 1 Protected by U. S. Patent Number 6,683,441; other patents pending. FUNCTIONAL BLOCK DIAGRAM VCC PRECISION REFERENCE SOFT START DELAY UVLO SHUTDOWN AND BIAS OSCILLATOR GND ADP3190 DELAY ILIMIT PWRGD RTRAMPADJ PWM2 PWM3 PWM4 SW1 CSSUM CSCOMP SW2 SW3 SW4 CSREF PWM1 COMP VID DAC DAC +150mV DAC –250mV CSREF EN CURRENT LIMIT CIRCUIT CROWBAR CURRENT LIMIT CMP CMP CURRENT BALANCING CIRCUIT CMP CMP 2-/3-/4-PHASE DRIVER LOGIC ENSET RESET RESET RESET RESET SHUNT REGULATOR (ADP3190 ONLY) 131428 EN 11 FBRTN VID4 VID3 VID2 VID1 VID0 VID5 FB8 05384-001 Figure 1. The ADP3190 is a replacement for the ADP3188. A built-in shunt regulator allows the part to be connected to the 12 V system supply through a series resistor. The devices are specified over the commercial temperature range of 0°C to +85°C and are available in a 28-lead TSSOP and a 28-lead QSOP . Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

1/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS VCC = 5 V , FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1 Table 1. Parameter Symbol Conditions Min Typ Max Units ERROR AMPLIFIER Output Voltage Range VCOMP 0 VCC V Accuracy VFB Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP , VOUT < 1 V −8.0 +8.0 mV Accuracy VFB Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP , VOUT > 1 V −9.5 +9.5 mV Line Regulation ΔVFB VCC = 4.75 V to 5.25 V 0.05 % Input Bias Current IFB 14 15.5 17 μA FBRTN Current IFBRTN 100 140 μA Output Current IO(ERR) FB forced to VOUT – 3% 500 μA Gain Bandwidth Product GBW(ERR) COMP = FB 20 MHz Slew Rate CCOMP = 10 pF 25 V/μs VID INPUTS Input Low Voltage VIL(VID) 0.4 V Input High Voltage VIH(VID) 0.8 V Input Current, Input Voltage Low IIL(VID) VID(X) = 0 V –25 –35 μA Input Current, Input Voltage High IIH(VID) VID(X) = 1.25 V 5 15 μA Pull-up Resistance RVID 35 60 85 kΩ Internal Pull-up Voltage 1.0 1.2 V VID Transition Delay Time 2 VID code change to FB change 400 ns No CPU Detection Turn-off Delay Time2 VID code change to 11111 to PWM going low 400 ns OSCILLATOR Frequency Range2 fOSC 0.25 4 MHz Frequency Variation fPHASE TA = +25°C, RT = 225 kΩ, 4-phase 155 200 245 kHz TA = +25°C, RT = 100 kΩ, 4-phase 400 kHz TA = +25°C, RT = 30 kΩ, 4-phase 600 kHz Output Voltage VRT RT = 100 kΩ to GND 1.8 2.0 2.3 V RAMPADJ Output Voltage VRAMPADJ RAMPADJ – FB –50 +50 mV RAMPADJ Input Current Range IRAMPADJ 0 100 μA CURRENT SENSE AMPLIFIER Offset Voltage VOS(CSA) CSSUM – CSREF –1.5 +1.5 mV Input Bias Current IBIAS(CSSUM) –10 +10 nA Gain Bandwidth Product GBW(CSA) 10 MHz Slew Rate CCSCOMP = 10 pF 10 V/μs Input Common-Mode Range CSSUM and CSREF 0 3 V Positioning Accuracy ΔVFB See Figure 5 –77 –80 –83 mV Output Voltage Range 0.05 VCC V Output Current ICSCOMP 500 μA CURRENT BALANCE CIRCUIT Common-Mode Range VSW(X)CM –600 +200 mV Input Resistance RSW(X) SW(X) = 0 V 12 20 28 kΩ Input Current ISW(X) SW(X) = 0 V 5 11 17 μA Input Current Matching3 ΔISW(X) SW(X) = 0 V –5 +5 %

Rev. 0 | Page 4 of 28 Parameter Symbol Conditions Min Typ Max Units CURRENT LIMIT COMPARATOR Output Voltage Normal Mode VILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ 2.8 3 3.3 V In Shutdown VILIMIT(SD) EN < 0.4 V, IILIMIT = –100 μA 400 mV Output Current, Normal Mode IILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ 12 μA Maximum Output Current2 60 μA Current Limit Threshold Voltage VCL VCSREF – VCSCOMP, RILIMIT = 250 kΩ 105 125 145 mV Current Limit Setting Ratio VCL/IILIMIT 10.4 mV/μA DELAY Normal Mode Voltage VDELAY(NM) RDELAY = 250 kΩ 2.8 3 3.3 V DELAY Overcurrent Threshold VDELAY(OC) RDELAY = 250 kΩ 1.6 1.9 2.2 V Latch-Off Delay Time tDELAY RDELAY = 250 kΩ, CDELAY = 12 nF 1.5 ms SOFT START Output Current, Soft Start Mode IDELAY(SS) During startup, DELAY < 2.8 V 15 20 25 μA Soft Start Delay Time tDELAY(SS) RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111 1 ms ENABLE INPUT Input Low Voltage VIL(EN) 0.4 V Input High Voltage VIH(EN) 0.8 V Input Current IIL(EN) –1 +1 μA POWER GOOD COMPARATOR Undervoltage Threshold VPWRGD(UV) Relative to nominal DAC output –180 –250 –300 mV Overvoltage Threshold VPWRGD(OV) Relative to nominal DAC output 90 150 200 mV Output Low Voltage VOL(PWRGD) IPWRGD(SINK) = 4 mA 225 400 mV Power Good Delay Time During Soft Start RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111 1 ms VID Code Changing 100 250 μs VID Code Static 200 ns Crowbar Trip Point VCROWBAR Relative to nominal DAC output 90 150 200 mV Crowbar Reset Point Relative to FBRTN 450 550 650 mV Crowbar Delay Time tCROWBAR Overvoltage to PWM going low VID Code Changing Blanking time 100 250 μs VID Code Static 400 ns PWM OUTPUTS Output Low Voltage VOL(PWM) IPWM(SINK) = –400 μA 160 500 mV Output High Voltage VOH(PWM) IPWM(SOURCE) = +400 μA 4.0 5 V SUPPLY—ADP3190 VSYSTEM = 12 V, RSHUNT = 240 Ω, see Figure 4 VCC VCC 5 V DC Supply Current 20 30 mA UVLO Threshold Voltage VUVLO VCC rising 6.3 7 8.0 V UVLO Hysteresis 0.9 V SUPPLY—ADP3190A VSYSTEM = 5V, RSHUNT = 10 Ω, see Figure 4 VCC VCC 5 V DC Supply Current 7 12 mA UVLO Threshold Voltage VUVLO VCC rising 3.7 4.0 4.3 V UVLO Hysteresis 0.9 V 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design, not production tested. Specifications subject to change without notice. 3 Relative current matching from each phase to the average of all four phases.

Rev. 0 | Page 5 of 28 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VCC –0.3 V to +6 V VID Pins –0.3 V to +6 V FBRTN –0.3 V to +0.3 V SW1 to SW4 −5 V to +25 V All Other Inputs and Outputs –0.3 V to VCC + 0.3 V Storage Temperature Range –65°C to +150°C Operating Ambient Temperature Range 0°C to +85°C Operating Junction Temperature 125°C Thermal Impedance (θJA) 100°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrosta tic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 3. Pin Function Descriptions “No CPU” mode, shutting off their PWM outputs and pulling the PWRGD output low. 7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. this pin and the output voltage sets the no-load offset point. 9 COMP Error Amplifier Output and Compensation Point. oscillator frequency of the device. currents together to measure the total output current. the load line and the positioning loop response time. 19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. ADP3190/ADP3190A to operate as a 2-, 3-, or 4-phase controller. 28 VCC ADP3190: A 240 Ω resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V. ADP3190A: A 10 Ω resistor should be placed between the 5 V system supply and the VCC pin to ensure 5 V.

Rev. 0 | Page 8 of 28 THEORY OF OPERATION The ADP3190/ADP3190A combine a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 6-bit VRD/VRM 10- and 10.1-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3190/ADP3190A ensures a stable, high performance topology for

Balancing currents and thermals between phases
High speed response at the lowest possible switching frequency and output decoupling
Minimizing thermal switching losses due to lower frequency operation
Tight load line regulation and accuracy
High current output for up to 4-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component selection
Flexibility in operation for tailoring design to low cost or high performance STARTUP SEQUENCE During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3190/ADP3190A operate as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation, and grounding the PWM3 pin and the PWM4 pin programs 2-phase operation. When the ADP3190/ADP3190A are enabled, the controller outputs a voltage on PWM3 and PWM4, which is approxi- mately 675 mV . An internal comparator checks each pin’s voltage vs. a threshold of 300 mV . If the pin is grounded, it is below the threshold, and the phase is disabled. The output resistance of the PWM pins is approximately 5 kΩ during this detection time. Any external pull-down resistance connected to the PWM pins should not be less than 25 kΩ to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 kΩ resistance is removed, and it switches between 0 V and 5 V . If the PWM output is grounded, it remains off. The PWM out- puts are logic-level devices intended for driving external gate drivers, such as the ADP3120A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time for overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ADP3190/ADP3190A is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3190/ADP3190A differential sense compares a high accuracy VID DAC and a precision reference to implement a low offset error amplifier. This maintains a worst-case specification of ±9.5 mV differential sensing error over their full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3190/ADP3190A provide a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detec- tion. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system:
Output inductor DCR sensing without a thermistor for lowest cost
Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements

Rev. 0 | Page 9 of 28 The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF − CSCOMP . This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors, so it can be made extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to equal the droop impedance of the regulator multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response. CURRENT-CONTROL MODE AND THERMAL BALANCE The ADP3190/ADP3190A have individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current-balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. Resistor RSW1 through Resistor RSW4 (see the typical application circuit in Figure 9) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure that placeholders are provided in the layout. To increase the current in any given phase, make RSW for this phase larger (make RSW = 0 for the hottest phase, and do not change during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. VOLTAGE CONTROL MODE A high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termi- nation voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through R B BB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP . SOFT START The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current-limit latch-off time. In UVLO, or when EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged with an internal 20 μA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of the VID DAC and C DLY, with a secondary effect from RDLY. Refer to the Application Information section for detailed information on setting CDLY. If EN is taken low or if VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft start cycle. Figure 7 shows a typical soft start sequence for the ADP3190/ADP3190A.

Table 4. VID Codes for the ADP3190/ADP3190A

Table 4. These limits are based on the VID voltage setting. during the time the output is changing. delay time on PWRGD, the soft start ramp must also be >1 ms. information on setting CDLY. voltage falls below the release threshold of approximately 550 mV . microprocessor from being destroyed. threshold, and the EN pin must be higher than its logic threshold. charge of the output capacitors when the controller is shut off. the output capacitors through the inductors.

1FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. Figure 9. Typical VR101 Applications Schematic (ADP3190 Only; See Figure 18 for ADP3190A Connections)

Rev. 0 | Page 14 of 28

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10.1-compliant CPU application are as follows:

Input voltage (VIN) = 12 V
VID setting voltage (VVID) = 1.300 V
Duty cycle (D) = 0.108
Nominal output voltage at no load (VONL) = 1.281 V
Nominal output voltage at 101 A load (VOFL) = 1.180 V
Static output voltage drop based on a 1.0 mΩ load line (RO) from no load to full load (VD) = VONL − VOFL = 1.281 V − 1.180 V = 101 mV
Maximum output current (IO) = 119 A
Maximum output current step (ΔIO) = 95 A
Number of phases (n) = 4
Switching frequency per phase (fSW) = 330 kHz SETTING THE CLOCK FREQUENCY The ADP3190/ADP3190A use a fixed-frequency control architecture. The frequency is set by an external timing resistor T). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and/or the input and output capacitors. With n = 4 for four phases, a clock frequency of 1.32 MHz sets the switching frequency (f SW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 3 shows that to achieve 1.32 MHz oscillator frequency, the correct value for RT is 130 kΩ. Alternatively, the value for RT can be calculated using Ω −× ×= k 31pF 7 . 4 SW T f nR (1) where 4.7 pF and 31 kΩ are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. SOFT START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES Because the soft start and current-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 μA internal current source. The value of RDLY has a second-order impact on the soft start time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 kΩ, this effect is minor. The value for CDLY can be approximated using VID SS DLY VID DLY V t R VC ×⎟⎟ ×− μ =2A 20 (2) where tSS is the desired soft start time. Assuming an RDLY of 390 kΩ and a desired soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY is chosen, RDLY can be calculated for the current-limit latch-off time using DLY DELAY DLY C tR ×= 96 . 1 (3) If the result for RDLY is less than 200 kΩ, a smaller soft start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200 kΩ. In this example, a delay time of 9 ms results in RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ. INDUCTOR SELECTION The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs; but it allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses but requires larger inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. ( ) L f DVI SW VID R × − ×= 1 (4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. ( )( ) RIPPLESW OVID V f D n R VL × Solving Equation 5 for a 10 mV p-p output ripple voltage yields ( ) nH 224mV 10 kHz 330 0.432 1 mΩ1.0 V 1.3 =× − × ×≥L If the resulting ripple voltage is less than it was designed for, make the inductor smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling.

Rev. 0 | Page 15 of 28 The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 320 nH inductor is a good starting point and gives a calculated ripple current of 11 A. The inductor should not saturate at the peak current of 35.5 A and should be able to handle the sum of the power dissipation caused by the average current of 30 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR can cause excessive power losses, while too small a value can lead to increased measurement error. A good rule is to have the DCR be about 1 to 1½ times the droop resistance (R O). For this design, an inductor with a DCR of 1.4 mΩ is used. DESIGNING AN INDUCTOR Once the inductance and DCR are known, the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. 15% inductance and 8% DCR (at room temperature) are reasonable tolerances most manufacturers can meet. The first decision in designing the inductor is to choose the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (for example, Kool- Mμ® from Magnetics, Inc. or from Micrometals) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type such as a potentiometer core, PQ, U, or E core or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as

Magnetic Designer Software Intusoft (www.intusoft.com)
Designing Magnetic Components for High-Frequency DC- DC Converters, by William T . McLyman, KG Magnetics, Inc., ISBN 1883107008 Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request:
Coilcraft www.coilcraft.com
Coiltronics www.coiltronics.com
Sumida Electric Company www.sumida.com
Vishay Intertechnology www.vishay.com OUTPUT DROOP RESISTANCE The design requires the regulator output voltage measured at the CPU pins to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (R O). The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with R PH(X) (summers), RCS, and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors: L x PH CS O RR RR × = (6) CSL CS R R LC ×= (7) The user has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 kΩ, and then solve for RPH(X) by rearranging Equation 6. () Ωk 140Ωk 100mΩ0 . 1 Ωm 4 . 1 = × = × = x PH CS O L xPH R RR RR Next, use Equation 6 to solve for CCS. nF 8 2 . 2Ωk 100Ωm 4 . 1 nH 320 =×=CSC It is best to have a dual location for CCS in the layout, so that standard values can be used in parallel to get as close as possible to the value desired. For accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of 1.5 nF and 560 pF in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 110 kΩ and 154 kΩ. The closest standard 1% value for R PH(X) is 158 kΩ.

needed for temperature changes of the inductor’s winding. desired temperature tracking. Figure 10. Temperature Compensation Circuit Values

Select an NTC based on type and value. Because there isn’t

a value yet, start with a thermistor with a value close to RCS.

Based on the type of NTC, find its relative resistance value

relative value is always 1 at 25°C.

Find the relative values of RCS required for each of these
Compute the relative values for RCS1, RCS2, and RTH using
Calculate RTH = rTH × RCS, then select the closest value of
Calculate values for RCS1 and RCS2 using Equation 10:

For this example, RCS has been calculated to be 110 kΩ. which yields a choice of 35.7 kΩ or 84.5 kΩ. lower than the nominal voltage corresponding to the VID code. The closest standard 1% resistor value is 1.21 kΩ.

Rev. 0 | Page 17 of 28 COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Also, to determine what is required, use some simple design guidelines that are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capaci- tance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18 of Size 1206 being the physical limit. Additional ceramic capacitors can be placed along the outer edge of the socket as well. Combined ceramic values of 200 μF to 300 μF are recommended, usually made up of multiple 10 μF or 22 μF capacitors. Select the number of ceramic capacitors, and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID on-the-fly voltage stepping of the output (Voltage Step VV in Time tV with error of VERR). A lower limit is based on meeting the capaci- tance for load release for a given maximum load step, ∆IO, and a maximum allowable overshoot. The total amount of load release voltage is given as ΔVO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum allowable overshoot voltage. ×⎟⎟ Δ Δ+ × z VID O rl O O MIN x C VI VR n I LC Δ (12) () ≤MAX xC z O V VID v VID V O 2 CL nKR V VtV V R nK L − −⎟⎟ ⎛ × + × × 11 (13) V ERR V Vn K1 where To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly speci- fication and may require the use of a smaller inductor or more phases (and may need the switching frequency to increase to keep the output ripple the same). This example uses 18, 10 μF 1206 MLC capacitors (CZ = 180 μF). The VID on-the-fly step change is 450 mV in 230 μs with a settling error of 2.5 mV . The maximum allowable load release overshoot for this example is 50 mV , so solving for the bulk capacitance yields () mF 65 . 3μF 180 V 3 . 1A 95 mV 50mΩ0 . 1 4 A 95 nH 320 = ×⎟⎟ ⎛ + × ×≤MIN xC () () ×× × V 3 . 1Ωm 0 . 1 6 . 4 4 mV 450 nH 320 22MAX xC F 180 1nH 320 mV 450 Ω m 1.0 4.6 4 V 1.3 μs 2301 −⎟⎟ × × × ×+ = 48.5 mF where K = 4.6. Using eight 560 μF Al-Poly capacitors with a typical ESR of 5 mΩ each yields CX = 4.48 mF with an RX = 0.63 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (L X) is low enough to limit the high frequency ringing during a load change. This is tested using () pH 360 2 mΩ1μF 180 = × × ≤ × × ≤ x Oz x L Q R C L (14) where Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is approximately 350 pH for the eight A1-Polys capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. For this multimode control technique, all ceramic designs can be used as long as the conditions of Equation 11, Equation 12, and Equation 13 are satisfied.

Rev. 0 | Page 18 of 28 POWER MOSFETS For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are V GS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3120A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V , logic-level threshold MOSFETs (VGS(TH)°< 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3190/ADP3190A, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (n SF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (I R) and average total output current (IO): () ()SF DS SF R SF O SF Rn I n n ID P × ⎛× +⎟⎟ ⎛× − = 11 (15) Knowing the maximum output current being designed for and the maximum allowed power dissipation, it is possible to find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Thus, for this example (119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C, so be certain to account for this temperature when making this selection. This example uses two lower-side MOSFET s at 4.8 mΩ each at 120 °C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3120A). The output impedance of the driver is approximately 2 Ω, and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω, so a total gate capacitance of less than 6000 pF should be adhered to. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the follow- ing expression provides an approximate value for the switching loss per main MOSFET, where n MF is the total number of main MOSFETs: () ISS MF G MF O CC SWMF S Cn nRn where RG is the total gate resistance (2 Ω for the ADP3120A and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω), and CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not really help the switching loss per MOSFET because the additional gate capacitance slows switching. The best way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET: () ()MFDS MF R MF MFC Rn I n nD P × ⎛× = O 1I (17) Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses. For this example, an NTD40N03L was selected as the main MOSFET (eight total; nMF = 8), with a CISS = 584 pF (maximum) and RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L was selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ (maximum at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. These numbers comply with the guideline to limit the power dissipation to 1 W per MOSFET. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation, where QGMF is the total gate charge for each main MOSFET , and QGSF is the total gate charge for each synchronous MOSFET: () CCCCGSFSFGMFMF SW DRV V I Q n Q nn fP × + × + × ××= 2 (18) Also shown is the standby dissipation factor (ICC × VCC) for the driver. For the ADP3120A, the maximum dissipation should be less than 400 mW . In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, 297 mW is found in each driver, which is below the 400 mW dissipation limit. See the ADP3120A data sheet for more details.

Rev. 0 | Page 19 of 28 RAMP RESISTOR SELECTION The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value: kΩ356pF 5Ωm 2.4 5 3 nH 320 0.2 =× × × × × × R R DS D R R R C R A L AR (19) where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor value. The closest standard 1% resistor value is 357 kΩ. The internal ramp voltage magnitude can be calculated by using () V m 390kHz 330 pF 5Ωk 357 V 1.3 0.108 1 0.2 =× × × − ×= × × × − ×= R SW R R VIDR R V f C R V D AV (20) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of 3 in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. COMP PIN RAMP A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: × × × × − ×− OXSW R RT R C f n D n VV 1 21 (21) In this example, the overall ramp signal is 0.49 V . CURRENT-LIMIT SETPOINT To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3190/ADP3190A is set with a 3 V source (V LIM) across RLIM with a gain of 10.4 mV/μA (ALIM). RLIM can be found using OLIM LIMLIM LIM R I VAR × ×= (22) For values of RLIM greater than 500 kΩ, the current limit can be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, choosing a peak current limit of 200 A for ILIM results in RLIM = 156 kΩ, for which 150 kΩ is chosen as the nearest 1% value. The limit of the per-phase current limit described earlier is determined by () 2 R MAX DS D BIAS RMAXCOMP PHLIM I R A V VV I +× − − ≅ (23) For the ADP3190/ADP3190A, the maximum COMP voltage COMP(MAX)) is 3.3 V , the COMP pin bias voltage (VBIAS) is 1.2 V , and the current-balancing amplifier gain (AD) is 5. Using VR of

0.49 V and RDS(MAX) of 3 mΩ (low-side on resistance at 150°C),

calculate a per-phase peak current limit of 100 A. Although this number may seem high, this current level can be reached only with an absolute short at the output, and the current-limit latch- off function shuts down the regulator before overheating can occur. This limit can be adjusted by changing the ramp voltage (VR), but make sure not to set the per-phase limit lower than the average per-phase current (I LIM/n). The per-phase initial duty cycle limit is determined by RT BIASMAXCOMP MAX V VV D D × = (24) In this example, the maximum duty cycle is 0.46. FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3190/ADP3190A allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (R O). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and allows minimization of the output decoupling. With the multimode feedback structure of the ADP3190/ ADP3190A, the feedback compensation must be set to make the converter’s output impedance, working in parallel with the output decoupling, to meet this goal. Several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for.

Rev. 0 | Page 20 of 28 A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 25 to Equation 29 yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Layout and Component Placement section). The first step is to compute the time constants for all of the poles and zeros in the system VID O X RT VID RT L DS D OE V R C n V D n L V V RR A R n R × × × ( ) Ω m 24.2V 1.3 Ω m 1 mF 4.45 4 V 0.490.432 1 nH 320 2 V 1.3 V 0.49 Ω m 1.4Ω m 2.4 5 Ω m 1 4 =× × × Ω m 0.65 Ω m 1 Ω m 1 X O O X OXA R R R R LR R C T (26) ( ) ( ) ns 580 mF 4.45 Ω m 1 Ω m 0.5 Ω m 0.63=×− += × −′+ = XOX B C R R R T (27) μs 4.7Ωm 24.2 V 1.3 kHz 330 2 Ωm 2.4 5nH 320 V 0.492 =× ×− × ×− × E VID SW DS D RT C R V f R AL V T (28) ( ) () ns 333Ω m 1 μF 180 Ω m 0.5 Ω m 1 mF 4.45 Ω m 1 μF 180 mF 4.45 =× + − × × ×= OZOX OZX D R C R R C R C CT (29) where, for the ADP3190/ADP3190A, R' is the PCB resistance from the bulk capacitors to the ceramics and RDS is the total low-side MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.49 V , R' is approximately 0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and LX is 350 pH for the eight Al-Poly capacitors. The compensation values can then be solved using the following: pF 342Ω k 1.21 Ω m 24.2 μs 2.50 Ω m 1 4=× × ×= × ×= A B E A O A C R R T R nC (30) Ωk 13.7pF 342 μs 4.7= = = A C A C TR (31) nF 479Ωk 1.21 ns 580= = = B B B R TC (32) F p 24.3Ωk 13.7 ns 333= = = A D FB R TC (33) These are the starting values, prior to tuning the design, to account for layout and other parasitic effects (see the Layout and Component Placement section). The final values selected after tuning are CA = 470 pF RA = 12.1 kΩ CB = 470 pF C B FB = 22 pF

Rev. 0 | Page 22 of 28 TUNING THE ADP3190/ADP3190A 1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Hook up the dc load to circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. DC Load Line Setting 3. Measure the output voltage at no load (VNL). Verify it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2, using Equation 35 and Equation 36. () ( ) FLHOTNL FLCOLDNL OLD CS2NEW CS2 V V V VRR − −×= (35) 5. Repeat Step 4 until the cold and hot voltage measurements remain the same. 6. Measure the output voltage from no load to full load, using 5 A steps. Compute the load line slope for each change, and then average to get the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mΩ, use the following to adjust the RPH values: () () O OMEAS OLD PHNEW PH R RRR × = (36) 8. Repeat Step 6 and Step 7 to check the load line, and repeat adjustments if necessary. 9. Once dc load line adjustment is complete, do not change R PH, RCS1, RCS2, or RTH for the remainder of the procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. () () C 25 1 °°° THTHOLD CS1NEW CS2OLD CS1THOLD CS1 THOLD CS1 NEW CS1 RR RR RR R RRR (37)

Rev. 0 | Page 25 of 28 LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal per- formance of a switching regulator in a PC system. GENERAL RECOMMENDATIONS

For good results, a PCB with at least four layers is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output power; and wide interconnection traces in the remainder of the power delivery current paths. Note: Each square unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at room temperature.
Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths. Then, the resistance and inductance introduced by these current paths is minimized, and the via current rating is not exceeded.
If critical signal lines, including the output voltage sense lines of the ADP3190/ADP3190A, must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground noisier.
Use an analog ground plane around and under the ADP3190/ADP3190A as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and not tied to any other power circuitry. This prevents power currents from flowing in the ground plane.
Locate the components around the ADP3190/ADP3190A close to the controller with short traces. The most important traces to keep short, and away from other traces, are the FB pin and the CSSUM pin. Connect the output capacitors as close as possible to the load (or connector), for example, a microprocessor core that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic.
Avoid crossing any signal lines over the switching power path loop, as described in the Power Circuitry Recommendations section. POWER CIRCUITRY RECOMMENDATIONS
The switching power path should be routed on the PCB to encompass the shortest possible length in order to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accom- modates the high current demand with minimal voltage loss.
Whenever a power dissipating component, (for example, a power MOSFET), is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. This improves current rating through the vias and also improves thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat- sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area.
The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load.
For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. SIGNAL CIRCUITRY RECOMMENDATIONS
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential-mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller.
The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.

1.20 MAX

6.40 BSC

Figure 19. 28-Lead Thin Shrink Small Outline Package [TSSOP] Figure 20. 28-Lead Thin Shrink Small Outline Package [QSOP]

Rev. 0 | Page 27 of 28 NOTES

Summary

6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller 1/06-Revision 0

Description