ADP3180JRU-REEL7

ADP3180 AD | Alldatasheet

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Information furnished by Analog Devices is be lieved to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or oth- erwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADP3180* 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller *Patent Pending

FEATURES

Selectable 2-, 3-, or 4-Phase Operation at up to

1 MHz per Phase

/H1155014.5 mV Worst-Case Differential Sensing Error over Te mperature Logic-Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between All Output Phases Built-In Power Good/Crowbar Blanking Supports On-the-Fly VID Code Changes 6-Bit Digitally Programmable 0.8375 V to 1.6 V Output Programmable Short Circuit Protection with Programmable Latch-Off Delay

APPLICATIONS

Desktop PC Power Supplies for: Next Generation Intel ® Processors VRM Modules FUNCTIONAL BLOCK DIAGRAM PWM2 FB PWM3 PWM4 SW1 CSSUM CSCOMP SW2 SW3 SW4 CSREF PWM1 ADP3180 VID4 VID3 VID2 VID1 VID5 VID0FBRTN GND EN DELAY ILIMIT PWRGD COMP VCC RT RAMPADJ CROWBAR CURRENT LIMIT 2-, 3-, 4-PHASE DRIVER LOGIC ENSET RESET RESET RESET RESET OSCILLATOR CMP CMP CMP CMP CURRENT BALANCING CIRCUIT DELAY UVLO SHUTDOWN AND BIAS DAC +150mV DAC –250mV CSREF PRECISION REFERENCE SOFT- START VID DAC EN CURRENT LIMIT CIRCUIT 28 13 14 1234 6 57 GENERAL DESCRIPTION The ADP3180 is a highly efﬁ cient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high per- formance Intel processors. It uses an internal 6-bit DAC to read a voltage identiﬁ cation (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and

1.6 V, and uses a multimode PWM architecture to drive the logic

level outputs at a programmable switching frequency that can be optimized for VR size and efﬁ ciency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four comple- mentary buck switching stages. The ADP3180 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3180 also provides accurate and reliable short circuit protection, adjustable current limiting, and a delayed Power Good output that accommodates on-the-ﬂ y output voltage changes requested by the CPU. ADP3180 is speciﬁ ed over the commercial temperature range of 0°C to 85°C and is available in a 28-lead TSSOP package. REV. 0

–2– ADP3180–SPECIFICATIONS1 (VCC = 12 V, FBRTN = GND, TA = 0/H11543C to 85/H11543C, unless otherwise noted.) Parameter Symbol Conditions Min T yp Max Unit ERROR AMPLIFIER Output Voltage Range Accuracy Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate V COMP VFB DVFB IFB IFBRTN IO(ERR) GBW(ERR) Relative to Nominal DAC Output, Referenced to FBRTN, CSSUM = CSCOMP (Figure 3) VCC = 10 V to 14 V FB Forced to V OUT – 3% COMP = FB C COMP = 10 pF 0.5 –14.5 0.05 15.5 500 3.5 +14.5 120 V mV µA µA µA MHz V/µs VID INPUTS Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High Pull-Up Resistance Internal Pull-Up Voltage VID Transition Delay Time No CPU Detection Turn-Off Delay Time VIL(VID) VIH(VID) IIL(VID) IIH(VID) RVID VID(X) = 0 V VID(X) = 1.25 V VID Code Change to FB Change VID Code Change to 11111 to PWM Going Low 0.8 0.825 400 400 –20 1.00 0.4 –30 115 V V µA µA kW V ns ns OSCILLATOR Frequency Range Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range f OSC fPHASE VRT VRAMPADJ IRAMPADJ TA = 25°C, R T = 250 kW, 4-Phase TA = 25°C, R T = 115 kW, 4-Phase TA = 25°C, R T = 75 kW, 4-Phase RT = 100 kW to GND RAMPADJ – FB 0.25 155 1.9 –50 200 400 600 2.0 245 2.1 +50 100 MHz kHz kHz kHz V mV µA CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current V OS(CSA) IBIAS(CSA) GBW(CSA) DVFB ICSCOMP CSSUM – CSREF, See Test Circuit 1 CCSCOMP = 10 pF CSSUM and CSREF See Test Circuit 2 I CSCOMP = ±100µA –50 –77 0.05 –80 500 +50 –83 3.3 mV nA MHz V/µs V mV V µA CURRENT BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching V SW(X)CM RSW(X) ISW(X) DISW(X) SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V –600 +200 mV kW µA CURRENT LIMIT COMPARATOR ILIMIT Output Voltage Normal Mode In Shutdown Output Current, Normal Mode Maximum Output Current Current Limit Threshold Voltage Current Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time V ILIMIT(NM) VILIMIT(SD) IILIMIT(NM) VCL VDELAY(NM) VDELAY(OC) tDELAY EN > 1.7 V, RILIMIT = 250 kW EN < 0.8 V, IILIMIT = –100 µA EN > 1.7 V, RILIMIT = 250 kW EN > 1.7 V V CSREF – VCSCOMP, RILIMIT = 250 kW VCL/IILIMIT RDELAY = 250 kW, CDELAY = 4.7 nF 2.9 105 2.9 1.7 125 10.4 1.8 600 3.1 400 145 3.1 1.9 V mV µA µA mV mV/µA V V µs NOTES 1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2Guaranteed by design, not tested in production. Speciﬁ cations subject to change without notice. REV. 0

–3– Parameter Symbol Conditions Min T yp Max Unit SOFT START Output Current, Soft-Start Mode Soft-Start Delay Time I DELAY(SS) tDELAY(SS) During Startup, DELAY < 2.8 V RDELAY = 250 kW, CDELAY = 4.7 nF VID Code = 011111 15 20 350 25 µA µs ENABLE INPUT Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High V IL(EN) VIH(EN) IIL(EN) IIH(EN) EN = 0 V EN = 1.25 V 0.8 0.4 V V µA µA POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power Good Delay Time VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static V PWRGD(UV) VPWRGD(OV) VOL(PWRGD) VCROWBAR tCROWBAR Relative to Nominal DAC Output Relative to Nominal DAC Output I PWRGD(SINK) = 4 mA Relative to Nominal DAC Output Relative to FBRTN Overvoltage to PWM Going Low –200 +90 100 450 100 –250 +150 +225 250 200 150 550 250 400 –325 +200 +400 200 650 mV mV mV µs ns mV mV µs ns PWM OUTPUTS Output Voltage Low Output Voltage High V OL(PWM) VOH(PWM) IPWM(SINK) = 400 µA IPWM(SOURCE) = 400 µA 4.0 160 5.0 500 mV V SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis V UVLO VCC Rising 6.5 0.7 6.9 0.9 7.3 1.1 mA V V Speciﬁ cations subject to change without notice. REV. 0

–4– PIN CONFIGURATION ADP3180 TOP VIEW (Not to Scale) VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT ABSOLUTE MAXIMUM RATINGS* VID0–VID5, EN, DELAY, ILIMIT, CSCOMP, RT, Junction to Air Thermal Resistance (/H9258 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁ cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise speciﬁ ed, all other voltages are referenced to GND. ORDERING GUIDE Model Temperature Range Package Options Quantity per Reel ADP3180JRU-REEL7 ADP3180JRU-REEL 0°C to 85°C 0°C to 85°C RU-28 (TSSOP-28) RU-28 (TSSOP-28) 1000 2500 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily ac cu mu late on the human body and test equipment and can discharge without detection. Although the ADP3180 features proprietary ESD pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. REV. 0

–5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1–6 VID4–VID0, VID5 Voltage Identiﬁ cation DAC Inputs. These six pins are pulled up to an internal reference, providing a logic one if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V . Leaving VID4 through VID0 open results in the ADP3180 going into a “No CPU” mode, shutting off its PWM outputs. 7 FBRTN Feedback Return. VID DAC and error ampliﬁ er reference for remote sensing of the output voltage. 8F BF eedback Input. Error ampliﬁ er input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point.

9 COMP Error Ampliﬁ er Output and Compensation Point

10 PWRGD Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the proper operating range. 11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs. 12 DELAY Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay time. 13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. 14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. 15 ILIMIT Curr ent Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3180 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high side and low side outputs should go low. 16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense ampliﬁ er and the Power Good and Crowbar functions. This pin should be connected to the common point of the output inductors. 17 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. 19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. 20–23 SW4–SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 24–27 PWM4– PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND will cause that phase to turn off, allowing the ADP3180 to operate as a 2-, 3-, or 4-phase controller. 28 VCC Supply Voltage for the Device. REV. 0

–6– ADP3180–Typical Performance Characteristics MASTER CLOCK FREQUENCY – MHz RT VALUE – k/H9024 SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH 0 50 100 150 200 250 300 TPC 1. Master Clock Frequency vs. RT TEST CIRCUITS CSSUM

18 CSCOMP

28 VCC

1.0V ADP3180 12V VOS = CSCOMP – 1V Test Circuit 1. Current Sense Ampliﬁ er VOS CSSUM 1.0V ADP3180 /H9004V 12V 100nF /H9004VFB = FB/H9004V = 80mV – FB/H9004V = 0mV Test Circuit 2. Positioning Voltage 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 SUPPLY CURRENT – mA MASTER CLOCK FREQUENCY – MHz TA = 25/H11543C 4-PHASE OPERATION TPC 2. Supply Current vs. Master Clock Frequency 250k/H9024 12V 1/H9262F 100nF 100nF VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT 20k/H9024 ADP3180 VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ 1.25V 6-BIT CODE 250k/H9024 1k/H9024 4.7nF Test Circuit 3. Closed-Loop Output Voltage Accuracy REV. 0

–7– VID4 VID3 VID2 VID1 VID0 VID5 V OUT(NOM) X No CPU 0.8375 V 0.850 V 0.8625 V 0.875 V 0.8875 V 0.900 V 0.9125 V 0.925 V 0.9375 V 0.950 V 0.9625 V 0.975 V 0.9875 V 1.000 V 1.0125 V 1.025 V 1.0375 V 1.050 V 1.0625 V 1.075 V 1.0875 V 1.100 V 1.1125 V 1.125 V 1.1375 V 1.150 V 1.1625 V 1.175 V 1.1875 V 1.200 V 1.2125 V VID4 VID3 VID2 VID1 VID0 VID5 V OUT(NOM) 1.225 V 1.2375 V 1.250 V 1.2625 V 1.275 V 1.2875 V 1.300 V 1.3125 V 1.325 V 1.3375 V 1.350 V 1.3625 V 1.375 V 1.3875 V 1.400 V 1.4125 V 1.425 V 1.4375 V 1.450 V 1.4625 V 1.475 V 1.4875 V 1.500 V 1.5125 V 1.525 V 1.5375 V 1.550 V 1.5625 V 1.575 V 1.5875 V 1.600 V X = Don't Care Table I. Output Voltage vs. VID Code THEORY OF OPERATION The ADP3180 combines a multimode, ﬁ xed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10 speciﬁ cations. Multiphase operation is important for produc- ing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter would place high thermal demands on the components in the system such as the inductors and MOSFETs. The multimode control of the ADP3180 ensures a stable, high performance topology for: ∑ Balancing currents and thermals between phases ∑ High speed response at the lowest possible switching frequency and output decoupling ∑ Minimizing thermal switching losses due to lower frequency operation ∑ Tight load line regulation and accuracy ∑ High current output from having up to 4-phase operation ∑ Reduced output ripple due to multiphase cancellation ∑ PC board layout noise immunity ∑ Ease of use and design due to independent component selection ∑ Flexibility in operation for tailoring design to low cost or high performance Number of Phases The number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3180 operates as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase opera- tion, and grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3180 is enabled, the controller outputs a voltage on PWM3 and PWM4 that is approximately 550 mV . An inter- nal comparator checks each pin’s voltage versus a threshold of 400 mV . If the pin is grounded, then it will be below the thresh- old and the phase will be disabled. The output resitance of the PWM pin is approximately 5 kW during this detection time. Any external pull-down resistance connected to the PWM pin should not be less than 25 kW to ensure proper operation. The phase detection is made during the ﬁ rst two clock cycles of the internal oscillator. After this time, if the PWM output was not grounded, the 5 kW resistance is removed and will switch between 0 V and 5 V . If the PWM output was grounded, it will remain off. REV. 0

–8– The PWM outputs become logic-level devices once normal operation starts. The detection is normal and is intended for driv- ing external gate drivers, such as the ADP3418. Since each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at a time for overlapping phases. Master Clock Frequency The clock frequency of the ADP3180 is set with an external resistor connected from the RT pin to ground. The frequency fol- lows the graph in TPC 1. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4. Output Voltage Differential Sensing The ADP3180 combines differential sensing with a high accuracy VID DAC and reference and a low offset error ampliﬁ er to main- tain a worst-case speciﬁ cation of ±10 mV differential sensing error with a VID input of 1.6000 V over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 90 µA to allow accurate remote sensing. The internal error ampliﬁ er compares the output of the DAC to the FB pin to regu- late the output voltage. Output Current Sensing The ADP3180 provides a dedicated current sense ampliﬁ er (CSA) to monitor the total output current for proper voltage positioning versus load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low side MOSFET. This ampliﬁ er can be conﬁ gured several ways, depending on the objectives of the system: ∑ Output inductor ESR sensing without thermistor for lowest cost ∑ Output inductor ESR sensing with thermistor for improved accuracy with tracking of inductor temperature ∑ Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the ampliﬁ er are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the ampliﬁ er, and a ﬁ lter capacitor is placed in parallel with this resistor. The gain of the ampliﬁ er is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF – CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current limit comparator. To provide the best accuracy for the sensing of current, the CSA has been designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors so that it can be made extremely accurate. Active Impedance Control Mode For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output cur- rent at the CSCOMP pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error ampliﬁ er where the output volt- age should be. This differs from previous implementations and allows enhanced feed-forward response. Current Control Mode and Thermal Balance The ADP3180 has individual inputs that are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current bal- ance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply volt- age for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section. External resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase may have better cooling and can support higher currents. Resistors R SW1 through RSW4 (see the typical application circuit in Figure 4) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure placeholders are provided in the layout. To increase the current in any given phase, make R SW for that phase larger (make RSW = 0 for the hottest phase and do not change during balancing). Increasing RSW to only 500 W will make a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the cool- est phase ﬁ rst. Voltage Control Mode A high gain-bandwidth voltage mode error ampliﬁ er is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID 6-bit logic code according to the voltages listed in Table I. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the ampliﬁ er is the COMP pin, which sets the termina- tion voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor R B and is used for sensing and controlling the output voltage at this point. A current source from the FB pin ﬂ owing through RB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage will be negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP. Soft-Start The power-on ramp up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current limit latch-off time as explained in the following section. In UVLO or when REV. 0

capacitor is charged up with an internal 20 µA current source. information on setting CDLY. shows a typical start-up sequence for the ADP3180. Figure 1. Start-Up Waveforms, Circuit of Figure 5.

1.8 V threshold is reached, the controller will return to normal

threshold, a soft-start cycle is initiated. (>1 MW) resistor should be connected from DELAY to VCC. the internal 20 µA current source. Figure 2. Overcurrent Latch-Off Waveforms, the low side MOSFETs through the current balance circuitry. the maximum normal mode COMP voltage. code. This change can be either positive or negative. change and ignores the DAC inputs for a minimum of 400 ns.

–10– six VID inputs are changing. Additionally, the ﬁ rst VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 250 µs to prevent a false PWRGD or CROWBAR event. Each VID change will reset the internal timer. Figure 3 shows VID on-the-ﬂ y performance when the output voltage is stepping up and the output current is switching between mini- mum and maximum values, which is the worst-case situation. Figure 3. VID On-the-Fly Waveforms, Circuit of Figure 5. will go low if the output voltage is outside of this speciﬁ ed range. microprocessor from destruction. charging of the output capacitors when the controller is shut off. the output capacitors through the inductors.

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10 compliant CPU application are as follows: ∑ Input voltage (V IN) = 12 V ∑ VID setting voltage (VVID) = 1.500 V ∑ Duty cycle (D) = 0.125 ∑ Nominal output voltage at no load (VONL) = 1.480 V ∑ Nominal output voltage at 65 A load (VOFL) = 1.3955 V ∑ Static output voltage drop based on a 1.3 mW load line (RO) from no load to full load ∑ (VD) = VONL – VOFL = 1.480 V – 1.3955 V = 84.5 mV ∑ Maximum Output Current (IO) = 65 A ∑ Maximum Output Current Step (DIO) = 60 A ∑ Number of Phases (n) = 3 ∑ Switching frequency per phase (fSW) = 267 kHz REV. 0

–1 1– ENABLE *SEE THEORY OF OPERATION SECTION FOR

DESCRIPTION

R SW RESISTORS POWER GOOD RLIM 200k/H9024 CDLY 39nF RT 249k/H9024 RDLY 390k/H9024 RA 16.9k/H9024 CFB 33pF CA 390pF CCS1 2.2nF RB 1.33k/H9024 CB 1.5nF RPH1 124k/H9024 FROM CPU RR 383k/H9024 CCS2 1.5nF RCS1 35.7k/H9024 RPH3 124k/H9024 RSW1* RSW3* RSW2* RCS2 73.2k/H9024 RPH2 124k/H9024 ADP3180 VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT C19 1/H9262F 10/H9024 C20 33/H9262F IPD06N03L 600nH/1.6m/H9024 BST IN OD VCC DRVH SW PGND DRVL C15 4.7/H9262F C18 4.7nF 2.2/H9024R TH 100k/H9024, 5%Q9 IPD06N03L ADP3418D4 1N4148WS C17 4.7/H9262F IPD12N03L C16 100nF IPD06N03L C12 100nF ADP3418 BST IN OD VCC DRVH SW PGND DRVL C11 4.7/H9262F 1N4148WS C14 4.7nF 2.2/H9024 IPD06N03L 4 5 IPD06N03L IPD06N03L IPD12N03L L3 600nH/1.6m/H9024 4.7/H9262F C13 4.7/H9262F 10/H9262F /H11547 23MLCC AROUND SOCKET V CC(CORE) 0.8375V–1.6V 65A AVG, 74A PK VCC(CORE) RTN 820/H9262F/2.5V /H11547 8 Fujitsu RE Series 8m/H9024 ESR (each) 600nH/1.6m/H9024 C21 C28 C10 4.7nF 2.2/H9024 IPD12N03L 1N4148WS 100nF 4.7/H9262F ADP3418 BST IN OD VCC DRVH SW PGND DRVL 1N4148WS V IN 12V VIN RTN 1.6/H9262H C1 C6 470/H9262F/16V /H11547 6 Nichicon PW Series Figure 4. 65 A Intel Pentium® 4 CPU Supply Circuit, VRD 10 Design

–12– Setting the Clock Frequency The ADP3180 uses a ﬁ xed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. With n = 3 for three phases, a clock frequency of 800 kHz sets the switching frequency of each phase, f SW, to 267 kHz, which represents a practical trade-off between the switching losses and the sizes of the output ﬁ lter components. TPC 1 shows that to achieve an 800 kHz oscillator frequency, the correct value for R T is 249 kW. Alternatively, the value for RT can be calculated using: R nf p F M T SW ××() − 58 3 1 15. . Ω (1) where 5.83 pF and 1.5 MW are internal IC component values. For good initial accuracy and frequency stability, it is recom- mended to use a 1% resistor. Soft-Start and Current Limit Latch-Off Delay Times Because the soft-start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The ﬁ rst step is to set C DLY for the soft-start ramp. This ramp is generated with a 20 µA internal current source. The value of R DLY will have a second order impact on the soft-start time because it sinks part of the current source to ground. However, as long as R DLY is kept greater than 200 kW, this effect is minor. The value for CDLY can be approximated using: CA V R t VDLY VID DLY SS VID =− ×  ×20 2 µ (2) where tSS is the desired soft-start time. Assuming an RDLY of 390 kW and a desired a soft-start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY has been chosen, RDLY can be calculated for the current limit latch-off time using: R t CDLY DELAY DLY = ×19 6. (3) If the result for RDLY is less than 200 kW, a smaller soft-start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. In no case should RDLY be less than 200 kW. In this example, a delay time of 8 ms gives RDLY = 402 kW. The closest standard 5% value is 390 kW. Inductor Selection The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple cur- rent, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows using smaller inductors and, for a speciﬁ ed peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses but requires larger inductors and more output capacitance for the same peak-to- peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator fre- quency, and peak-to-peak ripple current in the inductor. Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage: I VD fLR VID SW = ×−() 1 (4) L VR n D fV VID O SW RIPPLE ×× − × ()() 1 (5) Solving Equation 5 for a 10 mV p-p output ripple voltage yields: L Vm kHz mV nH≥ ×× − () × =15 13 1 03 7 5 267 10 456.. . Ω If the ripple voltage ends up less than that designed for, the inductor can be made smaller until the ripple value is met. This will allow optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 600 nH inductor is a good choice for a starting point and gives a calculated ripple current of 8.2 A. The inductor should not saturate at the peak current of 25.8 A and should be able to handle the sum of the power dissipation caused by the average current of 22.7 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR will cause excessive power losses, while too small a value will lead to increased measurement error. A good rule of thumb is to have the DCR be about 1 to 1½ times the droop resistance (R O). For our example, we are using an inductor with a DCR of 1.6 mW. Designing an Inductor Once the inductance and DCR are known, the next step is to either design an inductor or ﬁ nd a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance speciﬁ ed to control the accuracy of the system. 15% inductance and 8% DCR (at room temperature) are reasonable tolerances that most manufacturers can meet. The ﬁ rst decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-Mµ ® from Magnetics, Inc. or Micrometals) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type, such as a pot core, PQ, U, and E core, or toroid. A good compromise between price and performance is a core with a toroidal shape. There are many useful references for quickly designing a power inductor, such as: Magnetics Design References ∑ Magnetic Designer Software Intusoft (www.intusoft.com) ∑ Designing Magnetic Components for High-Frequency DC-DC Converters, by William T. McLyman, Kg Magnetics, Inc. ISBN 1883107008 REV. 0

–14– 5. Calculate R TH = RTH /H11003 RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k R R TH ACTUAL TH CALCULATED = () (9) 6. Finally, calculate values for RCS1 and RCS2 using Equation 10: RR k r RR k k r CS CS CS CS CS CS 22 1 =× × =× − () +×()() (10) For this example, RCS has been chosen to be 100 kW, so we start with a thermistor value of 100 kW. Looking through available 0603 size thermistors, we ﬁ nd a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these we compute R CS1 = 0.3796, RCS2 = 0.7195 and RTH = 1.0751. Solving for RTH yields 107.51 kW, so we choose 100 kW, making k = 0.9302. Finally, we ﬁ nd RCS1 and RCS2 to be 35.3 kW and 73.9 kW. Choosing the closest 1% resistor values yields a choice of 35.7 kW and 73.2 kW. Output Offset Intel’s speciﬁ cation requires that at no load the nominal output voltage of the regulator be offset to a lower value than the nomi- nal voltage corresponding to the VID code. The offset is set by a constant current source ﬂ owing out of the FB pin (I FB) and ﬂ ow- ing through RB. The value of RB can be found using Equation 11: R VV I R VV A k B VID ONL FB B = − = − =15 14 8 0 15 13 3.. . µ Ω (11) The closest standard 1% resistor value is 1.33 kW. COUT Selection The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. The ﬁ rst thing is to select the total amount of ceramic capaci- tance. This is based on the number and type of capacitor to be used. The best location for ceramics is inside the socket, with 12 to 18 of size 1206 being the physical limit. Others can be placed along the outer edge of the socket as well. Combined ceramic values of 200 µF–300 µF are recommended, usually made up of multiple 10 µF or 22 µF capacitors. Select the number of ceramics and ﬁ nd the total ceramic capacitance (C Z). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when one considers the VID on-the-ﬂ y voltage stepping of the output (voltage step VV in time tV with error of VERR) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step DIO: C LI nR V CXM I N O O VID Z() ≥ × ×× − (12) C L nK R V V t V V nKR L C K V V XM A X O V VID V VID V O Z VERR V () ≤ ×× + ×   −  − =−  where ln (13) To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is larger than CX(MAX), the system will not meet the VID on-the-ﬂ y speci- ﬁ cation and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). For our example, 23 10 µF 1206 MLC capacitors (C Z = 230 µF) were used. The VID on-the-ﬂ y step change is 250 mV in 150 µs with a setting error of 2.5 mV . Solving for the bulk capacitance yields: C nH A mV Fm F C nH mV mV sV m mV nH X MIN X MAX ≥ × ×× −  = ≤ × ×× × + ×× × × 600 60 31 3 1 5 230 5 92 600 250 34 6 1 3 1 5 1 150 1 5 3 4 61 3 250 600 .. . .( . ). .. . Ω Ω Ω µ µ  −  − 1 230 23 9 µF mF K .where Using eight 820 µF A1-Polys with a typical ESR of 8 mW, each yields CX = 6.56 mF with an RX = 1.0 mW. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the initial high fre- quency transient spike. This is tested using: LC R LF m p H XZ O X ≤× = 2230 1 3 389 µ (. ) Ω (14) In this example, LX is 375 pH for the eight A1-Polys capacitors, which satisﬁ es this limitation. If the LX of the chosen bulk capaci- tor bank is too large, the number of capacitors must be increased. One should note for this multimode control technique, all ceramic designs can be used as long as the conditions of Equations 11, 12, and 13 are satisﬁ ed. Power MOSFETs For this example, the N-channel power MOSFETs have been selected for one high side switch and two low side switches per phase. The main selection parameters for the power MOSFETs are V GS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With V GATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current IO determines the RDS(ON) requirement for the low side (synchronous) MOSFETs. With the ADP3180, currents are balanced between phases, thus the current in each low side MOSFET is the output current divided by the total number of MOSFETs (n SF). With conduction losses REV. 0

–15– being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (I R) and average total output cur- rent (IO); PD I n nI n RSF O SF R SF DS SF=−() ×  × ()1 1 (15) Knowing the maximum output current being designed for and the maximum allowed power dissipation, one can ﬁ nd the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50ºC, a safe limit for P SF is 1 W–1.5 W at 120ºC junction temperature. Thus, for our example (65 A maximum), we ﬁ nd RDS(SF) (per MOSFET) < 8.7 mW. This RDS(SF) is also at a junction temperature of about 120ºC, so we need to make sure we account for this when making this selec- tion. For our example, we selected two lower side MOSFETs at 7 mW each at room temperature, which gives 8.4 mW at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the non overlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is about 2 W and the typical MOSFET input gate resis- tances are about 1 W–2 W, so a total gate capacitance of less than 6000 pF should be adhered to. Since there are two MOSFETs in parallel, we should limit the input capacitance for each synchro- nous MOSFET to 3000 pF. The high side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approxi- mate value for the switching loss per main MOSFET, where n MF is the total number of main MOSFETs: Pf VI n R n n CSM F SW CC O MF G MF Here, RG is the total gate resistance (2 W for the ADP3418 and about 1 W for typical high speed switching MOSFETs, making RG = 3 W) and CISS is the input capacitance of the main MOS- FET. It is interesting to note that adding more main MOSFETs MF) does not really help the switching loss per MOSFET since the additional gate capacitance slows down switching. The best thing to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the fol- lowing, where R DS(MF) is the ON resistance of the MOSFET: PD I n nI n RCM F O MF R MF DS MF() () =×  (17) Typically, for main MOSFETs, one wants the highest speed (low CISS) device, but these usually have higher ON resistance. One must select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses. For our example, we have selected an Inﬁ neon IPD12N03L as the main MOSFET (three total; nMF = 3), with a CISS = 1460 pF (max) and RDS(MF) = 14 mW (max at TJ = 120ºC) and an Inﬁ neon IPD06N03L as the synchronous MOSFET (six total; nSF = 6), with CISS = 2370 pF (max) and RDS(SF) = 8.4 mW (max at TJ = 120ºC). The synchronous MOSFET C ISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at I O = 65 A and IR = 8.2 A yields 863 mW for each synchronous MOSFET and 1.44 W for each main MOSFET. These numbers work well considering there is usually more PCB area available for each main MOSFET versus each synchronous MOSFET. One last thing to look at is the power dissipation in the driver for each phase. This is best described in terms of the Q G for the MOSFETs and is given by the following, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET: P f n nQ n Q I VDRV SW MF GMF SF GSF CC CC= × ×× + ×() +  ×2 Also shown is the standby dissipation factor (ICC times the VCC) for the driver. For the ADP3418, the maximum dissipation should be less than 400 mW . For our example, with I CC = 7 mA, QGMF = 22.8 nC, and QGSF = 34.3 nC, we ﬁ nd 260 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3418 data sheet for more details. Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value: R AL AR C R nH mp F k R R DD SR R = × ×× × = × ×× × = 02 600 354 2 5 381. Ω Ω (19) where AR is the internal ramp ampliﬁ er gain, AD is the current balancing ampliﬁ er gain, RDS is the total low side MOSFET ON resistance, and CR is the internal ramp capacitor value. The clos- est standard 1% resistor value is 383 kW. The internal ramp voltage magnitude can be calculated using: V AD V RC f V V kp F kHz V R R VID RR S W R = ×−() × = ×−() × ×× = 02 1 01 2 5 15 383 5 267 05 1.. . . Ω (20) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response will improve, but thermal balance will degrade. Likewise, if the ramp is made smaller, thermal balance will improve at the sacriﬁ ce of transient response and stability. The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. (18) REV. 0

–16– COMP Pin Ramp There is a ramp signal on the COMP pin due to the droop volt- age and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input. V V nD nf C R RT R SW X O − ×− ×() ×× × 1 21 (21) For this example, the overall ramp signal is found to be 0.63 V . Current Limit Set Point To select the current limit set point, we need to ﬁ nd the resistor value for RLIM. The current limit threshold for the ADP3180 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA (ALIM). RLIM can be found using the following: R AV IRLIM LIM LIM LIM O = × × (22) For values of RLIM greater than 500 kW, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the sup- ply. For our example, choosing 120 A for ILIM, we ﬁ nd RLIM to be 200 kW, for which we chose 200 kW as the nearest 1% value. The per phase current limit described earlier has its limit deter- mined by the following: I VV V AR I PHLIM COMP MAX R BIAS D DS MAX × −() () 2 (23) For the ADP3180, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the cur- rent balancing ampliﬁ er gain (AD) is 5. Using VR of 0.63 V and RDS(MAX) of 4.2 mW (low side ON resistance at 150°C), we ﬁ nd a per phase limit of 66 A. This limit can be adjusted by changing the ramp voltage VR. But make sure not to set the per phase limit lower than the average per phase current (I LIM/n). There is also a per phase initial duty cycle limit determined by: DD VV VMAX COMP MAX BIAS RT −() (24) For this example, the maximum duty cycle is found to be 0.42. Feedback Loop Compensation Design Optimized compensation of the ADP3180 allows the best pos- sible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output imped- ance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (R O). With the resistive output impedance, the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output decoupling. With the multimode feedback structure of the ADP3180, one needs to set the feedback compensation to make the converter’s output impedance working in parallel with the output decoupling meet this goal. There are several poles and zeros created by the output inductor and decoupling capacitors (output ﬁ lter) that need to be compensated for. A type-three compensator on the voltage feedback is adequate for proper compensation of the output ﬁ lter. The expressions given in Equations 25–29 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (See the Tuning Procedure for the ADP3180 section). The ﬁ rst step is to compute the time constants for all of the poles and zeros in the system: Rn RAR RV V Ln D V nC R V Rm m mV V nH V mF EO D D S LR T VID RT XO VID E ×× × 31 3 54 2 16 06 3 2 600 1 0 375 0 63 36 5 6 1 3.. .. ΩΩ Ω mmV mΩ Ω× =15 37 9. . (25) TC RR L R RR R mF m m pH m mm m sAX O X O O X . .65 6 13 06 375 13 06 10 47 9 ΩΩ Ω ΩΩ Ω µ (26) T VL AR f VR Vn H m kHz Vm sC RT DD S SW VID E ×− × × = ×− × × =2 06 3 600 54 2 2 267 15 3 7 9 62 . . .. . Ω Ω µ (28) T CCR CR R C R mF F m mF m m F m nsD XZ O XO Z O = ×× ×−() +× = ×× ×−() +× 2 265 6 2 3 0 13 65 6 13 06 2 3 0 13 521 .( . ) .. . . µ µ Ω ΩΩ Ω (29) where, for the ADP3180, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total low side MOSFET ON resistance per phase. For this example, AD is 5, VRT equals 0.63 V, R' is approximately 0.6 mW (assuming a 4-layer motherboard), and LX is 375 pH for the eight Al-Poly capacitors. The compensation values can then be solved using the following: C nR T RR C ms mk pF A OA EB A = ×× = ×× × =31 3 4 7 9 37 9 1 33 371.. Ω ΩΩ µ (30) REV. 0

Figure 6. Typical Transient Response for Design Example

15 A) should be inserted between the converter and the supply

Build circuit based on compensation values computed from
Hook up dc load to circuit, turn on and verify operation.

Also check for jitter at no-load and full-load.

Measure output voltage at no-load (V NL). Verify it is within
Measure output voltage at full-load cold (V FLCOLD). Let

livolts, adjust RCS1 and RCS2 using Equations 35 and 37.

Repeat Step 4 until cold and hot voltage measurements
Measure output voltage from no-load to full-load using 5 A
If ROMEAS is off from RO by more than 0.05 mW, use the fol-
Repeat Steps 6 and 7 to check loadline and repeat adjust-
Once complete with dc loadline adjustment, do not change

RPH, RCS1, RCS2, or RTH for rest of procedure.

–19– LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal perfor- mance of a switching regulator in a PC system. Key layout issues are illustrated in Figure 11. 12V CONNECTOR INPUT POWER PLANE THERMISTOR OUTPUT POWER PLANE CPU SOCKET KEEP-OUT AREA KEEP-OUT AREA SWITCH NODE PLANES KEEP-OUT AREA KEEP-OUT AREA Figure 1 1. Layout Recommendations General Recommendations ∑ For good results, at least a 4-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input, and output power, and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mW at room temperature. ∑ Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. ∑ If critical signal lines (including the output voltage sense lines of the ADP3180) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. ∑ An analog ground plane should be used around and under the ADP3180 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from ﬂ owing in it. ∑ The components around the ADP3180 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. Refer to Figure 11 for more details on layout for the CSSUM node. ∑ The output capacitors should be connected as closely as pos- sible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capaci- tors should also be distributed and generally in proportion to where the load tends to be more dynamic. ∑ Avoid crossing any signal lines over the switching power path loop, described in the Power Circuitry section. Power Circuitry ∑ The switching power path should be routed on the PCB to encompass the shortest possible length in order to minimize radiated switching noise energy (i.e., EMI) and conduc- tion losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power con- verter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs including all interconnecting PCB traces and planes. The use of short and wide interconnec- tion traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high cur- rent demand with minimal voltage loss. ∑ Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal perfor- mance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To fur- ther improve thermal performance, the largest possible pad area should be used. ∑ The output power path should also be routed to encompass a short distance. The output power path is formed by the cur- rent path through the inductor, the output capacitors, and the load. ∑ For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry ∑ The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connects to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus the FB and FBRTN traces should be routed adjacent to each other atop the power ground plane back to the controller. ∑ The feedback traces from the switch nodes should be con- nected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. REV. 0

C03532–0–2/03(0)PRINTED IN U.S.A. –20– ADP3180 OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 4.50 4.40 4.30 28 15 141 9.80 9.70 9.60

6.40 BSC

0.15 0.05 0.30 0.19 0.65 BSC 1.20 MAX 0.20 0.09 0.75 0.60 0.45 8/H11543 0/H11543 COMPLIANT TO JEDEC STANDARDS MO-153AE COPLANARITY 0.10 REV. 0

Summary

6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller REV.0

Description