ADP3166

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADP3166* 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller *Patent pending

FEATURES

Selectable 2-, 3- or 4-Phase Operation at up to

1 MHz per Phase

Differential Sensing Error ±1% over Temperature Logic-Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between All Output Phases Built-in Power Good Blanking Supports On-the-Fly VID Code Changes 5-Bit Digitally Programmable 0.8 V to 1.55 V Output Short-Circuit Protection with Programmable Latch-Off Delay Overvoltage Protection Crowbar Logic Output

APPLICATIONS

Next-Generation AMD Processors VRM Modules FUNCTIONAL BLOCK DIAGRAM VCC PRECISION REFERENCE SOFT START UVLO SHUTDOWN AND BIAS OSCILLATOR GND ADP3166 EN DELAY ILIMIT PWRGD RTRAMPADJ PWM2 FB PWM3 PWM4 SW1 CSSUM CSCOMP SW2 SW3 SW4 CSREF PWM1 VID4 VID3 VID2 VID1 VID0FBRTN COMP VID DAC DAC + 300mV + DAC – 300mV CSREF CSREF 2.1V EN CURRENT LIMIT CIRCUIT CROWBAR CURRENT LIMIT –CMP –CMP –CMP –CMP CURRENT BALANCING CIRCUIT 2-, 3- , 4-PHASE DRIVER LOGIC ENSET RESET RESET RESET RESET CROWBAR 7 1 2 3 4 5 1314

10 DELAY

The ADP3166 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a

12 V main supply into the core supply voltage required by high

performance AMD processors. It uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the pro- cessor, which is used to set the output voltage between 0.8 V and 1.55 V. The ADP3166 also uses a multimode PWM archi tecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switch- ing stages. The ADP3166 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3166 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output volt- age changes requested by the CPU. ADP3166 is specified over the commercial temperature range of 0°C to 85°C and is available in a 28-lead TSSOP package.

REV. 0–2– ADP3166–SPECIFICATIONS1 Parameter Symbol Conditions Min Typ Max Unit ERROR AMPLIFIER Accuracy V FB 0.8 V Output Referenced to FBRTN, CSSUM = CSCOMP,0.792 0.800 0.808 V See Test Circuit 1 1.175 V Output Referenced to FBRTN, CSSUM = CSCOMP,1.163 1.175 1.187 V See Test Circuit 1 1.55 V Output Referenced to FBRTN, CSSUM = CSCOMP,1.535 1.55 1.566 V See Test Circuit 1 Line Regulation ∆VFB VCC = 10 V to 14 V 0.05 % Input Bias Current I FB –13 –15.5 –17 µA FBRTN Current I FBRTN 100 200 µA Output Current I O(ERR) FB forced to VOUT – 3% 500 µA Gain Bandwidth Product GBW (ERR) COMP = FB 20 MHz Slew Rate C COMP = 10 pF 50 V/ µs VID INPUTS Input Low Voltage V IL(VID) 0.8 V Input High Voltage V IH(VID) 2V Input Current I VID VID(X) = 0 V 20 26 µA Pull-Up Resistance R VID 100 120 k Ω Internal Pull-Up Voltage 2.0 2.4 2.65 V VID Transition Delay Time 2 VID code change to FB change 400 ns No CPU Detection Turn-Off VID code change to 11111 to 400 ns Delay Time2 PWM going low OSCILLATOR Frequency Range2 fOSC 0.25 4 MHz Frequency Variation f PHASE TA = 25°C, RT = 250 kΩ, 4-phase 160 200 240 kHz TA = 25°C, RT = 115 kΩ, 4-phase2 400 kHz TA = 25°C, RT = 75 kΩ, 4-phase2 600 kHz Output Voltage V RT RT = 100 kΩ to GND 1.9 2.0 2.1 V Timing Resistor Value 500 k Ω RAMPADJ Voltage V RAMPADJ RAMPADJ – FB –50 +50 mV RAMPADJ Input Current Range I RAMPADJ 05 0 µA CURRENT SENSE AMPLIFIER Offset Voltage V OS(CSA) CSSUM – CSREF, see Test Circuit 2 –3 +3 mV Input Bias Current I BIAS(CSA) 20 100 nA Gain Bandwidth Product GBW CSA 20 MHz Slew Rate C CSCOMP = 10 pF 50 V/ µs Input Common-Mode Range CSSUM and CSREF 0 3 V Positioning Accuracy ∆VFB See Test Circuit 3 –76 –80 –84 mV Output Voltage Range I CSCOMP = ± 100 µA 0.05 3.3 V Output Current I CSCOMP 500 µA CURRENT BALANCE CIRCUIT Common-Mode Range V SW(X)CM –600 +200 mV Input Resistance R SW(X) SW(X) = 0 V 24 30 36 k Ω Input Current I SW(X) SW(X) = 0 V 5 7 9 µA Input Current Matching ∆ISW(X) SW(X) = 0 V –5 +5 % CURRENT LIMIT COMPARATOR Output Voltage Normal Mode V ILIMIT(NM) EN > 2 V 2.9 3 3.1 V In Shutdown V ILIMIT(SD) EN < 0.8 V, IILIMIT = –100 µA 400 mV Output Current, Normal Mode I ILIMIT(NM) EN > 2 V, RILIMIT = 250 kΩ 12 µA Maximum Output Current EN > 2 V 60 µA Current Limit Threshold Voltage V CL VCSREF – VCSCOMP, RILIMIT = 250 kΩ 105 125 145 mV Current Limit Setting Ratio V CL/IILIMIT 10.4 mV/ µA Latch-Off Delay Threshold V SET(DLY) In current limit 1.7 1.8 1.9 V Latch-Off Delay Time t SET(DLY) RDELAY = 250 kΩ, CDELAY = 4.7 nF 600 µs (VCC = 12 V, FBRTN = GND, T A = 0/H11543C to 85/H11543C, unless otherwise noted.)

REV. 0 ADP3166 –3– NOTES 1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2Guaranteed by design, not tested in production. Specifications subject to change without notice. Parameter Symbol Conditions Min Typ Max Unit SOFT START Output Current, Soft Start Mode I DELAY(SS) During start-up, DELAY < 2.8 V 15 20 25 µA Soft Start Delay Time t DELAY(SS) RDELAY = 250 kΩ, CDELAY = 4.7 nF 350 µs VID Code = 01111 ENABLE INPUT Input Low Voltage V IL(EN) 0.8 V Input High Voltage V IH(EN) 2V Input Current –1 +1 µA POWER GOOD COMPARATOR Undervoltage Threshold V PWRGD(UV) Relative to nominal DAC output –200 –300 –400 mV Overvoltage Threshold V PWRGD(OV) Relative to nominal DAC output 200 300 400 mV Output Low Voltage V OL(PWRGD) IPWRGD(SINK) = 4 mA 150 400 mV Off-State Leakage Current V CSREF = VDAC 50 µA Delay Time VID Code Changing 100 250 µs VID Code Static 400 ns CROWBAR COMPARATOR Crowbar Trip Point V CROWBAR 2.0 2.1 2.2 V Crowbar Reset Point 300 400 500 mV Crowbar Response Time t CROWBAR Overvoltage to PWM Low 400 ns Overvoltage to CRWBR High 400 ns Output Voltage Low V OL(CROWBAR) ICROWBAR(SINK) = 100 µA 100 500 mV Output Voltage High V OH(CROWBAR) ICROWBAR(SOURCE) = 100 µA 4.0 5.0 V PWM OUTPUTS Output Voltage Low V OL(PWM) IPWM(SINK) = 400 µA 160 500 mV Output Voltage High V OH(PWM) IPWM(SOURCE) = 400 µA 4.0 5.0 V SUPPLY DC Supply Current I CC 71 0 m A UVLO Threshold Voltage V UVLO VCC rising 6.5 6.9 7.3 V UVLO Hysteresis 0.7 0.9 1.1 V

REV. 0–4– ADP3166 ABSOLUTE MAXIMUM RATINGS * VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP, 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 SUPPLY CURRENT – mA MASTER CLOCK FREQUENCY – MHz TA = 25/H11543C 4-PHASE OPERATION TPC 1. Supply Current vs. Master Clock Frequency ORDERING GUIDE Temperature Package Quantity Model Range Options per Reel ADP3166JRU-REEL7 0 °C to 85°C RU-28 (TSSOP-28) 1000 ADP3166JRU-REEL 0 °C to 85°C RU-28 (TSSOP-28) 2500 *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. MASTER CLOCK FREQUENCY – MHz RT VALUE – kΩ 05 0 100 150 200 250 300 TPC 2. Master Clock Frequency vs. R T CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0 ADP3166 –5– CSSUM CSCOMP VCC CSREF GND 39k/H9024 100nF 1k/H9024 ADP3166 12V VOS = CSCOMP – 1V Test Circuit 2. Positioning Amplifier V OS Test Circuit CSSUM CSCOMP VCC FB COMP CSREF GND 10k/H9024 200k/H9024 200k/H9024 80mV ADP3166 12V /H9004VFB = FB – VVID Test Circuit 3. Positioning Voltage Test Circuit 250k/H9024 12V 1/H9262F 100nF 100nF VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT 20k/H9024 ADP3166 VID4 VID3 VID2 VID1 VID0 CROWBAR FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ 1.25V 5-BIT CODE 250k/H9024 1k/H9024 4.7nF Test Circuit 1. Closed-Loop Output Voltage Accuracy

REV. 0–6– ADP3166 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1–5 VID4–VID0 Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8 V to 1.55 V. Leaving VID4 through VID0 open results in the ADP3166 going into a “No CPU” mode, shutting off its PWM outputs. 6 CROWBAR Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply to ground to protect the CPU from overvoltage if CSREF exceeds 2.1 V. 7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. 8F B Feedback Input. Error amplifier input for remote sensing of the output voltage. A resistor between this pin and the output voltage sets the no-load offset point. 9 COMP Error Amplifier Output and Compensation Point. 10 PWRGD Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the proper operating range. 11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs. 12 DELAY Soft Start Delay and Current Limit Latch-Off Delay Setting Input. A resistor and capacitor connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. 13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscil- lator frequency of the device. 14 RAMPADJ PWM Ramp Current Input. A resistor from the converter input voltage to this pin sets the internal PWM ramp. 15 ILIMIT Current Limit Set Point/Enable Output. A resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3166 EN input is low, or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. 16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifiers and the Power Good and Crowbar functions. This pin should be connected to the com- mon point of the output inductors. 17 CSSUM Current Sense Summing Node. Resistors from each switch node to this pin sum the average inductor cur- rents together to measure the total output current. 18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. 19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. 20–23 SW4–SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be grounded. 24–27 PWM4–PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM 4 outputs to GND will cause that phase to turn off, allowing the ADP3166 to operate as a 2-, 3-, or 4-phase controller. 28 VCC Supply Voltage for the Device. PIN CONFIGURATION RU-28 ADP3166 TOP VIEW (Not to Scale) VID4 VCC VID3 PWM1 VID2 PWM2 VID1 PWM3 VID0 PWM4 CROWBAR SW1 FBRTN SW2 FB SW3 COMP SW4 PWRGD GND EN CSCOMP DELAY CSSUM RT CSREF RAMPADJ ILIMIT

REV. 0 ADP3166 –7– THEORY OF OPERATION The ADP3166 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal 5-bit VID DAC conforms to AMD’s Hammer family power specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single- phase converter would place high thermal demands on the components in the system such as the inductors and MOSFETs. The multimode control of the ADP3166 ensures a stable, high performance topology for

Balancing currents and thermals between phases.
High speed response at the lowest possible switching frequency and output decoupling.
Minimizing thermal switching losses due to lower frequency operation.
Tight load line regulation and accuracy.
High current output from having up to 4-phase operation.
Reduced output ripple utilizing multiphase cancellation.
Immunity to board layout.
Ease of use and design due to independent component selection.
Flexibility in operation for tailoring design to low cost or high performance. Number of Phases The number of operational phases and their phase relationship are determined by internal circuitry that monitors the PWM outputs. Normally, the ADP3166 operates as a 4-phase PWM controller. Grounding the PWM 4 pin programs 3-phase opera- tion, and grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3166 is enabled, the controller outputs a voltage on PWM3 and PWM4 that is approximately 550 mV. An inter- nal comparator checks each pin’s voltage versus a threshold of 400 mV. If the pin is grounded, it will be below the threshold and the phase will be disabled. The output impedance of the PWM pin is approximately 5 k Ω. Any external pull-down resis- tance connected to the PWM pin should not be less than 25 k Ω to ensure proper operation. The phase detection is made during the first two clock cycles of the internal oscillator. After this time, if the PWM output was not grounded, it will switch between 0V and 5 V. If the PWM output was grounded, it will remain off. The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3418. Since each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at a time for overlapping phases. Master Clock Frequency The clock frequency of the ADP3166 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in TPC 1. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4. Table I. VID Code vs. Output Voltage VID4 VID3 VID2 VID1 VID0 V OUT(NOM) (V) 11111N o C P U 11110 0.800 11101 0.825 11100 0.850 11011 0.875 11010 0.900 11001 0.925 11000 0.950 10111 0.975 10110 1.000 10101 1.025 10100 1.050 10011 1.075 10010 1.100 10001 1.125 10000 1.150 01111 1.175 01110 1.200 01101 1.225 01100 1.250 01011 1.275 01010 1.300 01001 1.325 01000 1.350 00111 1.375 00110 1.400 00101 1.425 00100 1.450 00011 1.475 00010 1.500 00001 1.525 00000 1.550 Output Voltage Differential Sensing The ADP3166 combines differential sensing with a high accu- racy VID DAC and reference and a low offset error amplifier to maintain a worst-case specification of ±1% differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the micropro- cessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision refer- ence are referenced to FBRTN, which has a minimal current of 100 µA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. Output Current Sensing The ADP3166 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning versus load current, and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET.

REV. 0–8– ADP3166 This amplifier can be configured several ways depending on the objectives of the system:

Output inductor ESR sensing without thermistor for lowest cost
Output inductor ESR sensing with thermistor for improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF – CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning, and as a differential input for the current limit comparator. To provide the best accuracy for the sensing of current, the CSA has been designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors so that it can be made extremely accurate. Active Impedance Control Mode For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output cur- rent at the CSCOMP pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the sys- tem. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response. Voltage Control Mode A high gain-bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID 5-bit logic code according to the voltages listed in Table I. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage position- ing. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor, R B, and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through R B is used for setting the no-load offset voltage from the VID voltage. The no-load voltage will be positive with respect to the VID DAC. The main loop compensation is incorporated in the feedback network between FB and COMP. Soft Start The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current limit latch-off time, as explained in the following section. In UVLO or when EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged up with an internal 20 µA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of VID DAC and C DLY, with a secondary effect from RDLY. Refer to the Applications section for detailed information on setting CDLY. When the PWRGD threshold is reached, the soft start cycle is stopped and the DELAY pin is pulled up to 3 V. This ensures that the output voltage is at the VID voltage when the PWRGD signals to the system that the output voltage is good. If EN is taken low or if VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft start cycle. Current Limit and Short-Circuit Protection The ADP3166 compares a programmable current limit set point to the voltage on the output of the current sense amplifier at the CSCOMP pin. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current limit threshold of 10.4 mV/µA. If the difference in voltage between CSREF and CSCOMP drops below the current limit threshold, the internal current limit amplifier will control the internal COMP voltage to maintain the average output current at the limit. After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current limit latch-off delay time is therefore set by the RC time constant discharging from 3 V to 1.8 V. The Applications section discusses the selection of R DLY based on the CDLY that has been chosen. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.8 V threshold is reached, the controller will return to normal operation. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if short circuit has caused the output voltage to drop below the PWRGD threshold, then a soft start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3166, or by pulling the EN pin low for a short time. To disable the short-circuit latch-off function, the external resistor to ground should be left open, and a large (greater than 1 MΩ) resistor should be connected from VCC to DELAY. This prevents the DELAY capacitor from discharging so the 1.8 V threshold is never reached. The resistor will have an impact on the soft start time because the current through it will add to the internal 20 µA current source. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This sec- ondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This will limit the voltage drop across the low-side MOSFETs through the current balance circuitry.

REV. 0 ADP3166 –9– Dynamic VID The ADP3166 incorporates the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and sup- plying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID-OTF can occur under either light load or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be either positive or negative. When a VID input changes state, the ADP3166 detects the change and blanks the DAC for a minimum of 400 ns. This time is to prevent a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD blanking function for a minimum of 100 µs to prevent a false PWRGD event. Each VID change will reset the internal timer. Power Good Monitoring The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified previ- ously, based on the VID voltage setting. PWRGD will go low if the output voltage is outside of this specified range. PWRGD is blanked during a VID-OTF event for a period of 100 µs to prevent false signals during the time the output is changing. Output Crowbar As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) and the CROWBAR logic output goes high when the output voltage exceeds the upper power good threshold. This crowbar acti on releases once th e output volt- age has fallen back within specifications if no other faults are present. The release threshold is approximately 400 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short of the high-side MOSFET, this action current limits the input supply or blow its fuse, protect- ing the microprocessor from destruction. The CROWBAR output can be used to signal an external input crowbar or other protection circuit. Output Enable and UVLO The input VCC must be higher than the UVLO threshold and the EN pin must be higher than its logic threshold for the ADP3166 to begin switching. IF UVLO is less than the threshold or the EN pin is a logic low, the ADP3166 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3418 drivers. Because ILIMIT is grounded, this disables the drivers such that both DRVH and DRVL are grounded. This feature is important to prevent dis- charging of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors.

APPLICATION INFORMATION

The design parameters for a typical AMD K8 compliant CPU application are as follows:

Input voltage (VIN) = 12 V
VID setting voltage (V VID) = 1.500 V
Duty cycle (D) = 0.125
Maximum static output voltage error ( ± VSERR) = ±50 mV
Maximum dynamic output voltage error ( ±VDERR) = ±70 mV
Error voltage allowed for controller and ripple ( ± VRERR) = ± 20 mV
Maximum output current (I O) = 56 A
Maximum output current step ( /H9004IO) = 24 A
Static output droop resistance (R O) based on: a) No load output voltage set at upper output voltage limit. VONL = VVID + VSERR – VRERR = 1.530 V b) Full load output voltage set at lower output voltage limit.
VOFL = VVID – VSERR + VRERR = 1.470 V
RO = (VONL – VOFL)/ (IO) = (1.530 V – 1.470 V)/(56A) = 1.1 mΩ
Dynamic output droop resistance (R OD) based on: a) Output current step to no load with output voltage set at upper output dynamic voltage limit. VONLD = VVID + VDERR – VRERR = 1.550 V b) Output voltage prior to load change (at IOUT = /H9004IO).
VOL = VONL – (/H9004IO /H11547 RO)= 1.504 V
ROD = (VONLD – VOL)/ (/H9004IO) = (1.550 V – 1.504 V)/(24A) = 1.9 mΩ
Number of phases (n) = 3
Switching frequency per phase (f SW) = 330 kHz Setting the Clock Frequency The ADP3166 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (R T). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. With n = 3 for three phases, a clock frequency of 990 kHz sets the switching frequency of each phase, f SW, to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 1 shows that to achieve a 990 kHz oscillator frequency, the correct value for R T is 200 kΩ. Alternatively, the value for RT can be calculated using nf . . T SW 58 3 1 15××() ΩpF M– (1) where 5.83 pF and 1.5 M Ω are internal IC component values. For good initial accuracy and frequency stability, it is recom- mended to use a 1% resistor.

REV. 0–10– ADP3166 ENABLE *SEE THEORY OF OPERATION SECTION FOR

DESCRIPTION

R SW RESISTORS POWER GOOD RLIM 200k/H9024 CDLY 39nF RT 200k/H9024 RDLY 390k/H9024 RA 7.32k/H9024 CFB 18pF CA 680pF CCS1 2.2nF RB 2.00k/H9024 CB 680pF RPH1 147k/H9024 FROM CPU RR 383k/H9024 CCS2 1.5nF RCS1 35.7k/H9024 RPH3 147k/H9024 RSW1* RSW3* RSW2* RCS2 73.2k/H9024 RPH2 147k/H9024 ADP3166 VID4 VID3 VID2 VID1 VID0 CROWBAR FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT C19 1/H9262F 10/H9024 C20 33/H9262F IPD06N03L 600nH/1.6m/H9024 BST IN OD VCC DRVH SW PGND DRVL C15 4.7/H9262F C18 4.7nF 2.2/H9024 R TH 100k/H9024, 5%Q9 IPD06N03L ADP3418 1N4148WS C17 4.7/H9262F IPD12N03L C16 100nF IPD06N03L C12 100nF ADP3418 BST IN OD VCC DRVH SW PGND DRVL C11 4.7/H9262F 1N4148WS C14 4.7nF 2.2/H9024 IPD06N03L 4 5 IPD06N03L IPD06N03L IPD12N03L L3 600nH/1.6m/H9024 4.7/H9262F C13 4.7/H9262F 10/H9262F /H11547 5MLCC AROUND SOCKET V CC(CORE) 0.8V–1.55V 56A VCC(CORE) RTN 820/H9262F/2.5V /H11547 8 OSCON SERIES 12m/H9024 ESR (EACH) 600nH/1.6m/H9024 C21 C28 C10 4.7nF 2.2/H9024 IPD12N03L 100nF 4.7/H9262F ADP3418 BST IN OD VCC DRVH SW PGND DRVL 1N4148WS 1N4148WS VIN 12V VIN RTN 1.6/H9262H C1 C6 2200/H9262F/16V /H11547 3 NICHICON PW SERIES Figure 1. 56 AMD K8 CPU Supply Circuit

REV. 0 ADP3166 –11– Soft Start and Current Limit Latch-Off Delay Times Because the soft start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 µA internal current source. The value of RDLY will have a second order impact on the soft- start time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 k Ω, this effect is minor. The value for CDLY can be approximated using C= A – V R t VDLY VID DLY SS VID 20 2µ ×  × (2) where tSS is the desired soft start time. Assuming an RDLY of 390 kΩ and a desired a soft start time of 3 ms, CDLY is 36 nF. The closest standard value for C CS is 39 nF. Once CDLY has been chosen, RDLY can be calculated for the current limit latch off time using R= .t CDLY DLY DLY 19 6 × (3) If the result for RDLY is less than 200 kΩ , then a smaller soft start time should be considered by recalculating the equation for CDLY or a longer latch-off time should be used. In no case should RDLY be less than 200 kΩ. In this example, a delay time of 8 ms makes RDLY = 402 kΩ. The closest standard 5% value is 390 kΩ. Inductor Selection The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduc- tion losses in the MOSFETs but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the induc- tance, oscillator frequency, and peak-to-peak ripple current in the inductor. Equation 5 can be used to determine the mini- mum inductance based on a given output ripple voltage: I= V– D fR VID SW × () L (4) L ≥ ×× × ()() VR – n D fV VID OD SW RIPPLE (5) Solving Equation 5 for a 10 mV p-p output ripple voltage yields L ≥ ×Ω × () 15 19 1 03 7 5 330 10 540.V .m – . kHz mV =n H If the ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. This will allow opti- mal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. A 600 nH inductor is a good choice for a starting point, and it gives a calculated ripple cur- rent of 6.6 A. The inductor should not saturate at the peak current of 22 A, and should be able to handle the sum of the power dissipation caused by the average current of 18.7 A in the winding and the core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR will cause excessive power losses, while too small a value will lead to increased measurement error. A good rule is to have the DCR be about 1 to 1 1/2 times the static droop resistance (R O). For our example, we are using an inductor with a DCR of 1.6 mΩ. Designing an Inductor Once the inductance and DCR are known, the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled. Using 20% for the inductance and 8% for the DCR (at room temperature) are rea- sonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-Mµ ® from Magnetics, Inc. or Micrometals) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choices for a core geometry are closed-loop types, such as pot cores, PQ, U, and E cores, or toroids. A good compromise between price and performance are cores with a toroidal shape. There are many useful references for quickly designing a power inductor, such as

Magnetic Designer Software Intusoft (http://www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-8

Coilcraft (847)639-6400 http://www.coilcraft.com
Coiltronics (561)752-5000 http://www.coiltronics.com
Sumida Electric Company (510) 668-0660 http://www.sumida.com
Vishay Intertechnology (402) 563-6866 http://www.vishay.com Output Droop Resistance The design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to the static output droop resistance (R O). The output current is measured by summing together the voltage across each inductor and then passing the signal through a low- pass filter. This summer-filter is the CS amplifier configured with resistors R PH(X) (summers) and RCS, and CCS (filter). The output resistance of the regulator is set by the following equations, where R L is the DCR of the output inductors: R= R R RO CS PH(X) L× (6) C= L RRCS LC S× (7) One has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 kΩ, and then solve for RPH(X) by rearranging Equation 6. R= R R RPH(X) L O CS× R= .m .m k= . kPH(X) 11 100 145 5Ω Ω ΩΩ× Next, use Equation 6 to solve for CCS: C= nH .m k =. n FCS 600 16 100 37 5ΩΩ× It is best to have a dual location for CCS in the layout so stan- dard values can be used in parallel to get as close to the value desired. For this example, choosing C CS to be a 1.5 nF and 2.2 nF in parallel is a good choice. For best accuracy, CCS should be a 10% capacitor. The closest standard 1% value for R PH(X) is 147 kΩ . Inductor DCR Temperature Correction With the inductor’s DCR being used as the sense element and copper wire being the source of the DCR, one needs to com- pensate for temperature changes of the inductor’s winding. Fortunately, copper has a well known temperature coefficient C) of 0.39%/°C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it will cancel the tem- perature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 (see Figure 2) are needed to linearize the NTC and produce the desired tem- perature tracking. CSSUM 18CSCOMP PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW SIDE MOSFET CSREF 16 ADP3166 CCS RCS1 RTH RCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES TO SWITCH NODES TO VOUT SENSE RPH1 RPH3RPH2

Figure 2. Temperature Compensation Circuit Values

Select an NTC based on type and value. Since we do not
Based on the type of NTC, find its relative resistance value at

the NTC’s relative value is always 1 at 25°C.

Next, find the relative value of RCS required for each of these

REV. 0 ADP3166 –13– 4. Compute the relative values for RCS1, RCS2, and RTH using R= A–B r r –A – Br + B – Ar R= 1– A –R – A r– R –R – R CS CS CC S TH CS CS 12 2 1 21 2 × () ×× () × () S (8) 5. Calculate RTH = rTH /H11003 RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: R R TH ACTUAL TH CALCULATED (9) 6. Finally, calculate values for RCS1 and RCS2 using the following: R= R k R R= R - k + k R CS CS CS CS CS CS 22 1 × () ×()() (10) For this example, RCS has been chosen to be 100 kΩ, so we start with a thermistor value of 100 kΩ. Looking through available 0603 size thermistors, we find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these we compute R CS1 = 0.3796, R CS2 = 0.7195 and R TH = 1.0751. Solving for R TH yields 107.51 k Ω, so we choose 100 k Ω, mak- ing k = 0.9302. F inally, we find RCS1 and RCS2 to be 35.3 kΩ and 73.9 kΩ. Choosing the closest 1% resistor values yields a choice of 35.7 kΩ and 73.2 kΩ. Output Offset AMD’s specification requires that at no load, the nominal output voltage of the regulator be offset to a higher value than the nominal voltage corresponding to the VID code. The offset is set by a con- stant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11: R= V– V I R= .V – . V A =. k B ONL VID FB B 15 3 15 15 20 0µ Ω (11) The closest standard 1% resistor value is 2.00 k Ω. COUT Selection The required output decoupling for the regulator is typically recommended by AMD for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capaci- tance, which is based on the number and type of capacitor to be used. The best location for ceramics is inside the socket. Others can be placed along the outer edge of the socket as well. Combined ceramic values of 30 µF to 100 µF are recommended, usually made up of multiple ceramic capacitors. Select the num- ber of ceramics and find the total ceramic capacitance (C Z). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when one considers the VID on-the-fly voltage stepping of the output (voltage step V V in time tV with error of VERR) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step ∆IO: C LI nR V CX MIN O OD VID Z() –≥ × (12) C L nK R V V +t V V nKR L –1 –C XM A X 2 O V VID V VID V O Z () ≤ (13) where K –In V V ERR V To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (R X) should be less than or equal to the dynamic droop resistance, R OD. If the CX(MIN) is larger than CX(MAX), the system will not meet the VID on-the-fly specification and may require the use of a sm aller inductor or more phases (and may have to increase the switch- ing frequency to keep the output ripple the same). For our example, a combination of MLCC capacitors (CZ = 50 µF) was used. The VID on-the-fly step change is from 1.5 V to 0.8 V (making VV = 700 mV) in 100 µs with a setting error of 3%. Solving for the bulk capacitance yields C nH A mV Fm FX MIN() .. –.≥ × ×× µ  =600 24 31 9 1 5 50 1 63Ω C nH mV .. V + ms . V . . m mV nH ––m F =. m F XM A X () ≤ × ×× × × 600 700 33 5 1 5 1 100 1 5 3 3 5 1 1 700 600 15 0 2 0 4 Ω where K = 3.5. Using eight 820 µF OSCONs with a typical ESR of 12 m Ω each yields CX = 6.56 mF with an RX = 1.5 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the initial high fre- quency transient spike. This is tested using LC R Lm F . m W =p H XZ O D X ≥× × ≥× × 25 0 1 9 361 2 (14)

REV. 0–14– ADP3166 In this example, LX is 375 pH for the eight OSCON capacitors, which basically satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of capacitors must be increased. One should note for this multimode control technique, all- ceramic designs can be used as long as the conditions of Equations 12, 13, and 14 are satisfied. Power MOSFETs For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With V GATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current, I O, determines the R DS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3166, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs ( n SF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (I R) and average total output current (IO): P=– D I n + nI n RSF O SF R SF DS SF1 1 () ×  × () (15) Knowing the maximum output current being designed for and the maximum allowed power dissipation, one can find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50ºC, a safe limit for PSF is 1 W to 1.5 W at 120ºC junction temperature. Thus, for our example (56 A maximum), we find RDS(SF) (per MOSFET) < 10 mΩ. This RDS(SF) is also at a junction temperature of about 120ºC, so we need to make sure we account for this when making this selection. For our example, we selected two lower-side MOSFETs at 7 mΩ each at room temperature, which gives 8.4 mΩ at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and the feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch off the synchronous MOSFETs should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is about 2 Ω and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω, so a total gate capacitance of less than 6000 pF should be adhered to. Since there are two MOSFETs in parallel, we should limit the input capacitance for each synchro- nous MOSFET to 3000 pF. The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switch- ing speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression pro- vides an approximate value for the switching loss per main MOSFET, where n MF is the total number of main MOSFETs: P= 2 f VI n R n n CSM F SW CC O MF G MF Here, RG is the total gate resistance (2 Ω for the ADP3418 and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω) and CISS is the input capacitance of the main MOSFET. It is interesting to note that adding more main MOSFETs (n MF) does not really help the switching loss per MOSFET since the additional gate capacitance slows down switching. The best thing to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the fol- lowing, where RDS(MF) is the on resistance of the MOSFET: P= D I n + nI n RCM F O MF R MF DS MF() () ×  12 (17) Typically, for main MOSFETs, one wants the highest speed (low CISS) device, but these usually have higher on resistance. One must select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switch- ing and conduction losses. For our example, we have selected an Infineon IPD12N03L as the main MOSFET (three total; nMF = 3), with a CISS = 1460 pF (max) and RDS(MF) = 14 mΩ (max at TJ = 120ºC) and an Infineon IPD06N03L as the synchronous MOSFET (six total; n SF = 6), with CISS = 2370 pF (max) and RDS(SF) = 8.4 mΩ (max at TJ = 120ºC). The synchronous MOSFET CISS is less than 3000 pF, satisfy- ing that requirement. Solving for the power dissipation per MOSFET at IO = 56 A and IR = 6.6 A yields 647 mW for each synchronous MOSFET and 1.26 W for each main MOSFET. These numbers work well considering there is usually more PCB area available for each main MOSFET versus each syn- chronous MOSFET. One last thing to look at is the power dissipation in the driver for each phase. This is best described in terms of the Q G for the MOSFETs and is given by the following, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET: P= f n nQ + n Q + IVDRV SW MF GMF SF GSF CC CC2 × ×× ×()  × (18) Also shown is the standby dissipation factor ( ICC /H11003 VCC) for the driver. For the ADP3418, the m aximum dissipation should be less than 400 mW. For our example, with ICC = 7 mA, QGMF = 22.8 nC and QGSF = 34.3 nC, we find 265 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3418 data sheet for more details.

REV. 0 ADP3166 –15– Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value: R= AL AR C R= . 600 nH .m W p F =k R R DD SR R ×× × ×× × 354 2 5 381 Ω (19) where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor value. The closest standard 1% resistor value is 383 k Ω. The internal ramp voltage magnitude can be calculated using V= A– D V RC f V= .– . . V kp F kHz =. V R R VID RR S W R × () × × () × 02 1 01 2 5 15 383 5 330 04 1Ω (20) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response will improve, but thermal balance will degrade. C onversely, if the ramp is made smaller, thermal balance will improve at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. COMP Pin Ramp There is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input. V= V – R+ R – n D nf C R R RT R OO D SW X O OD 1 1() × () ×× × ×  (21) For this example, the overall ramp signal is found to be 0.48 V. Current Limit Set Point To select the current limit set point, we need to find the resistor value for RLIM. The current limit threshold for the ADP3166 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA (ALIM). RLIM can be found using the following: R= AV IRLIM LIM LIM LIM O × (22) For values of RLIM greater than 500 kΩ, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the sup- ply. For our example, choosing 75 A for ILIM, we find RLIM to be 378 kΩ, for which we choose 374 kΩ as the nearest 1% value. The per phase current limit described earlier has its limit deter- mined by the following: I V– V – V AR – I PHLIM COMP(MAX) R BIAS D DS(MAX) R≅ × 2 (23) For the ADP3166, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage ( VBIAS) is 1.2 V, and the current balancing amplifier gain ( AD) is 5. Using VR of 0.48 V, and RDS(MAX) of 4.2 mΩ (low-side on resistance at 150 °C), we find a per phase limit of 74 A. This limit can be adjusted by changing the ramp voltage V R. But make sure not to set the per phase limit lower than the average per phase current (I LIM/n). There is also a per phase initial duty cycle limit determined by: D= D V– V VMAX COMP MAX BIAS RT × () (24) For this example, the maximum duty cycle is found to be 0.55. Feedback Loop Compensation Design Optimized compensation of the ADP3166 allows the best pos- sible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is optimized over the widest possible frequency range, including dc, and equal to the droop resistances (R O and ROD). With the output impedance, the output voltage will respond in proportion with the load current; this ensures the optimal output positioning and allows the minimization of the output decoupling. With the multimode feedback structure of the ADP3166, one needs to set the feedback compensation to make the converter’s output impedance work in parallel with the output decoupling to meet this goal. There are several poles and zeros created by the output inductor and decoupling capacitors (output filter) that need to be compensated for.

REV. 0–16– ADP3166 The first step is to compute the time constants for all of the poles and zeros in the system: R= n R + A R + RV V + R+ R L – n D V nC R R V .V + .m +.m n H –. eO D D D S LR T VID OO D R T XOO D VID e ××× × 31 9 54 2 16 04 8 11 19 6 0 0 10 375 0ΩΩ Ω Ω ..V .m F. m . m. V R= . me 36 5 6 1 1 19 15 36 0 ×× × × ΩΩ Ω (25) T= C R – R+ L R R– R R T= 6.56 mF 1.9 m – 0.6 m + 375 pH 1.5 m 1.9 m – 0.6 m 1.5 m T= 8.70 s aX O D ' X OD OD X a a × () × × () ×ΩΩ Ω ΩΩ Ω µ (26) T=R + R– R C bX OD X b () × ΩΩ Ω() ×µ15 06 19 65 6 13 1m (27) VL – AR VR .V n H – .m kHz .. m =. s c RT DD S SW VID e c × × × × × µ 04 8 600 54 2 2 330 15 3 6 0 50 5 Ω ΩV (28) T= CCR CR – R + C R T= .m F m F . m .m F . m – . m + m F . m =7 n s d XZO D XO Z O D d × () × ×× Ω ×Ω Ω() ×Ω 265 6 5 0 19 65 6 19 06 5 0 19 13 (29) C= T R = ns .k =. p FFB d A 137 73 3 18 7Ω (33) Choosing the closest standard values for these components yields: CA = 680 pF, RA = 7.32 kΩ, CB = 680 pF, and CFB = 18 pF. Figure 3 shows the typical transient response using the compen- sation values. CIN Selection and Input Current di/dt Reduction In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n /H11003 V OUT/VIN and an amplitude one-nth of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by I= D I nD – I= A . –= . A CRMS O CRMS ×× × ×× × 1 1 0 125 56 1 3 125 19 0 5. (34) Note that the capacitor manufacturer’s ripple current ratings are often based on only 2,000 hours of life. This makes it advisable where, for the ADP3166, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total low-side MOSFET on resistance per phase. For this example, AD is 5, VRT equals 0.48 V, R' is approximately 0.6 mΩ (assuming a 4-layer motherboard), and LX is 375 pH for the eight OSCON capacitors. A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. The expressions that follow are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and com- ponent parasitic effects (see the Tuning Procedure section). The compensation values can then be solved using the following: C= nR T RR C= .m . s .m . k =p F A OD a eB A ×× µ 31 9 8 7 0 36 0 2 00 689Ω ΩΩ (30) C= T R = .s .k =p FB b B 13 1 20 0 655µ Ω (31) C= T R = .s .k =p FB b B 13 1 20 0 655µ Ω (32)

and the primary power source.

Build a circuit based on compensation values computed

from the design spreadsheet.

Hook up the dc load to the circuit, turn it on, and verify its

operation. Also check for jitter at no load and full load.

Measure the output voltage at no load (V NL). Verify that
Measure the output voltage at full load cold (VFLCOLD). Let

millivolts, adjust RCS1 and RCS2 using Equations 35 and 37.

Repeat Step 4 until the cold and hot voltage measurements
Measure the output voltage from no load to full load using 5

then average them to get the overall loadline slope (ROMEAS).

If ROMEAS is off by more than 0.05 m Ω from RO, use Equa-
Repeat Steps 6 and 7 to check the loadline and repeat the
Once finished with dc loadline adjustment, do not change

RPH, RCS1, RCS2, or RTH for the rest of the procedure.

Measure the output ripple at no load and at full load with

a scope and make sure that it is within spec.

Remove the dc load from the circuit and hook up the
Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 µs/div.

Set the dynamic load for a transient step of about 24 A at 1
Measure the output waveform (it might be necessary to

vertical scale of 100 mV/div or finer.

The waveform should look something like Figure 3. Use

Figure 3. AC Loadline Waveform

If the V ACDRP and VDCDRP are different by more than a few

since there are limited standard capacitor values available.

Repeat Steps 11 to 13 and repeat adjustments if neces-
Set the dynamic load step to maximum step size (do not

REV. 0 ADP3166 –19– Power Circuitry

The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (i.e., EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise- related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss.
Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, the largest possible pad area should be used.
The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load.
For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connects to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Therefore the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller.
The feedback traces from the switch nodes should be con- nected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the inductor nearest to the controller.

REV. 0 C03589–0–4/03(0) –20– ADP3166 OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 4.50 4.40 4.30 28 15 141 9.80 9.70 9.60

6.40 BSC

0.15 0.05 0.30 0.19 0.65 BSC 1.20 MAX 0.20 0.09 0.75 0.60 0.45 8/H11543 0/H11543 COMPLIANT TO JEDEC STANDARDS MO-153AE COPLANARITY 0.10

Summary

5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller REV.0

Description