ADP3164

ADP3164 ONSEMI | Alldatasheet

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Technical content

a ADP3164 5-Bit Programmable 4-Phase Synchronous Buck Controller FUNCTIONAL BLOCK DIAGRAMFEATURES ADOPT™ Optimal Positioning Technology for Superior Load Transient Response and Fewest Output Capacitors Complies with VRM 9.1 with Lowest System Cost 4-Phase Operation at up to 500 kHz per Phase Quad Logic-Level PWM Outputs for Interface to External High-Power Drivers Active Current Balancing between All Output Phases Accurate Multiple VRM Module Current Sharing 5-Bit Digitally Programmable 1.1 V to 1.85 V Output Total Output Accuracy /H115500.8% Over Temperature Current-Mode Operation Short Circuit Protection Enhanced Power Good Output Detects Open Outputs in Multi-VRM Power Systems Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components

APPLICATIONS

Desktop PC Power Supplies for: Intel Pentium ® 4 Processors VRM Modules DAC + 20% CMP CS– CS+ COMP FB gm PWM3 PWM1SET RESET CROWBAR PGND PWM2 VID DAC VID4 VID3 VID2 VID1 VCC REF GND CT VID0 SHARE POWER GOOD CMP DAC – 20% PWRGD PWM4 3.0V REFERENCE UVLO & BIAS OSCILLATOR 4-PHASE DRIVER LOGIC ADP3164 SOFT ST ART GENERAL DESCRIPTION The ADP3164 is a highly efficient 4-phase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high per- formance Intel processors. The ADP3164 uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.1 V and 1.85 V. The ADP3164 uses a current mode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The four output phases share the dc output current to reduce overall output voltage ripple. An active current bal- ancing function ensures that all phases carry equal portions of the total load current, even under large transient loads, to mini- mize the size of the inductors. The ADP3164 also uses a unique supplemental regulation tech- nique called active voltage positioning (ADOPT) to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifi- cations for high-performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3164 also provides accurate and reliable short circuit protection, adjustable current limiting, and an enhanced Power Good output that can detect open outputs in any phase for single or multi-VRM systems. The ADP3164 is specified over the commercial temperature range of 0°C to 70°C and is available in a 20-lead TSSOP package. Pentium is a registered trademark of Intel Corporation.

REVISION HISTORY

01/08 Rev 1: Conversion to ON Semiconductor ©2010 SCILLC. All rights reserved. Publication Order Number: May 2010 - Rev. 2 ADP3164/D

REV. 0–2– ADP3164–SPECIFICATIONS1 (VCC = 12 V, IREF = 150 A, TA = 0C to 70C, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit FEEDBACK INPUT Accuracy V FB 1.1 V Output 1.091 1 .11 .109 V 1.6 V Output 1.587 1 .61 .613 V 1.85 V Output 1.835 1 .85 1 .865 V Line Regulation VFB VCC = 10 V to 14 V 0 .01 % Input Bias Current I FB 55 0n A Crowbar Trip Point V CROWBAR % of Nominal Output 115 120 125 % Crowbar Reset Point % of Nom inal Output 40 50 60 % Crowbar Response T ime t CROWBAR Overvoltage to PWM Go ing Low 400 ns REFERENCE Output Voltage V REF 2.952 3 .00 3 .048 V Output Current I REF 300 A VID INPUTS Input Low Voltage V IL(VID) 0.8V Input High Voltage V IH(VID) 2.0V Input Current I VID VID(X) = 0 V 70 90 A Pull-Up Resistance R VID 33 43 k Internal Pull-Up Voltage 2 .73 .03 .3V OSCILLATOR Maximum Frequency2 fCT(MAX) 4000 kHz Frequency Variation f CT TA = 25 C, CT = 150 pF 475 575 675 kHz TA = 25 C, CT = 68 pF 850 1000 1250 kHz TA = 25 C, CT = 47 pF 1100 1300 1500 kHz CT Charge Current I CT TA = 25 C, VFB in Regulation 260 300 340 A TA = 25 C, VFB = 0 V 40 65 80 A ERROR AMPLIFIER Output Resistance R O(ERR) 1M Transconductance g m(ERR) 2.02 .22 .45 mmho Output Current I O(ERR) FB = 0 V 575 A Maximum Output Voltage V COMP(MAX) FB Forced to VOUT – 3% 3 .0V Output Disable Threshold V COMP(OFF) 800 875 mV –3 dB Bandwidth BW ERR COMP = Open 500 kHz CURRENT SENSE Threshold Voltage V CS(TH) CS+ = VCC, 143 158 173 mV FB Forced to VOUT – 3% FB 750 mV 80 92 108 mV 0.8 V SHARE

1 V 0 5 mV

Input Bias Current I CS+, ICS– CS+ = CS– = VCC 1 5 A Response Time t CS CS+ – (CS–) 173 mV 50 ns to PWM Going Low CURRENT SHARING Output Source Current 2 mA Output Sink Current 300 400 A Maximum Output Voltage V SHARE(MAX) FB Forced to VOUT – 3% 3 .0V POWER GOOD COMPARATOR Undervoltage Threshold V PWRGD(UV) Percent of Nominal Output 75 80 85 % Overvoltage Threshold V PWRGD(OV) Percent of Nominal Output 115 120 125 % Output Voltage Low V OL(PWRGD) IPWRGD(SINK) = 1 mA 375 525 mV Response Time 250 ns PWM OUTPUTS Output Voltage Low V OL(PWM) IPWM(SINK) = 400 A 100 500 mV Output Voltage High V OH(PWM) IPWM(SOURCE) = 400 A4 .05 .0V Duty Cycle Limit Per Phase2 DC 25 %

REV. 0 –3– ADP3164 Parameter Symbol Conditions Min Typ Max Unit SUPPLY DC Supply Current Normal Mode I CC 3.75 5 .5m A No CPU Mode I CC(NO CPU) VID4 – VID0 = Open 3 .55 .5m A UVLO Mode I CC(UVLO) VCC VUVLO, VCC Rising 350 500 A UVLO Threshold Voltage V UVLO 5.96 .46 .9V UVLO Hysteresis 0.50 .81 .0V NOTES 1All limits at temperature extremes are guaranteed v ia correlation using standard Stat istical Quality Control (SQC) . 2Guaranteed by des ign, not tested in production. Specifications subject to change w ithout notice. ABSOLUTE MAXIMUM RATINGS * C to 70 C C C to +150 C C/W C C C *This is a stress rating only; operation beyond these l imits can cause the dev ice to be permanently damaged . Unless otherw ise specified, all voltages are referenced to PGND. ORDERING GUIDE Model Temperature Range Package Description Package Option ADP3164JRU 0 C to 70 CT h in Shrink Small Outline RU-20 (TSSOP-20) PIN CONFIGURATION RU-20 VID4 VID3 VID2 VID1 VID0 SHARE COMP GND FB CT VCC REF PWM1 PWM2 PWM3 PWM4 PGND CS– CS+ PWRGD ADP3164 TOP VIEW (Not to Scale) WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostat ic d ischarge) sens itive dev ice. Electrostat ic charges as h igh as 4000 V read ily accumulate on the human body and test equ ipment and can d ischarge w ithout detect ion. Although the ADP3164 features propr ietary ESD protect ion c ircuitry, permanent damage may occur on devices sub jected to h igh-energy electrostat ic discharges . Therefore, proper ESD precaut ions are recommended to avo id performance degradat ion or loss of funct ionality.

DAC inputs open results in the ADP3164 going into a “No CPU” mode, shutt ing off its PWM outputs. control level between CS+ and CS– . 7 COMP Error Ampl ifier Output and Compensat ion Point. that can also be used as a return for the FB p in in remote voltage sens ing applications. 9 FB Feedback Input . Error amplifier input for remote sens ing of the output voltage . 10 CT External capac itor CT connection to ground sets the frequency of the dev ice. is not supplying current even if the output voltage is in specification. at this pin with respect to CS–. 13 CS– Current Sense Negat ive Node. Negative input for the current comparator . 14 PGND Power Ground . All internal biasing and logic output signals of the ADP3164 are referenced to th is ground. 15 PWM4 Log ic-Level Output for the Phase 4 Dr iver. 16 PWM3 Log ic-Level Output for the Phase 3 Dr iver. 17 PWM2 Log ic-Level Output for the Phase 2 Dr iver. 18 PWM1 Log ic-Level Output for the Phase 1 Dr iver. 19 REF 3 .0 V Reference Output . 20 VCC Supply Voltage for the ADP3164 . Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit

REV. 0 –5– Typical Performance Characteristics–ADP3164 CT CAP ACIT ANCE – pF 0.1 0 100 50 FREQUENCY – MHz 150 250 200 300 TPC 1. Oscillator Frequency vs. Timing Capacitor (CT) OSCILLA TOR FREQUENCY – kHz 4.5 4.0 0 1000 500 SUPPL Y CURRENT – mA 4.4 1500 2500 2000 3000 4.3 4.2 4.1 TPC 2. Supply Current vs. Oscillator Frequency OUTPUT ACCURACY – % of Nominal –0.5 NUMBER OF P ARTS – % 00 .5 TA = 25C VOUT = 1.6V TPC 3. Output Accuracy Distribution

REV. 0 ADP3164 –6– THEORY OF OPERATION The ADP3164 combines a current-mode, fixed frequency PWM controller with multiphase logic outputs for use in a 4-phase syn- chronous buck power converter. Multiphase operation is important for switching the h igh currents requ ired by h igh performance microprocessors . Handling the h igh current in a single-phase converter would place unreasonable requ irements on the power components such as inductor w ire size and MOSFET ON- resistance and thermal d issipation. The ADP3164’s h igh side current sensing topology ensures that the load currents are bal- anced in each phase, such that no s ingle phase has to carry more than it’s share of the power . An additional benefit of high side current sens ing over output current sens ing is that the average current through the sense res istor is reduced by the duty cycle of the converter allow ing the use of a lower power, lower cost resistor. The outputs of the ADP3164 are log ic drivers only and are not intended to directly drive external power MOSFETs. Instead, the ADP3164 should be pa ired w ith dr ivers such as the ADP3413 . Table I. Output Voltage vs. VID Code VID4 VID3 VID2 VID1 VID0 V OUT(NOM) 11111N o C P U 111101 .100 V 111011 .125 V 111001 .150 V 110111 .175 V 110101 .200 V 110011 .225 V 110001 .250 V 101111 .275 V 101101 .300 V 101011 .325 V 101001 .350 V 100111 .375 V 100101 .400 V 100011 .425 V 100001 .450 V 011111 .475 V 011101 .500 V 011011 .525 V 011001 .550 V 010111 .575 V 010101 .600 V 010011 .625 V 010001 .650 V 001111 .675 V 001101 .700 V 001011 .725 V 001001 .750 V 000111 .775 V 000101 .800 V 000011 .825 V 000001 .850 V The frequency of the ADP3164 is set by an external capac itor connected to the CT p in. The error amplifier and current sense comparator control the duty cycle of the PWM outputs to ma in- tain regulation. The maximum duty cycle per phase is inherently limited to 25%. While one phase is on, all other phases rema in off. In no case can more than one output be h igh at any time. Output Voltage Sensing The output voltage is sensed at the FB p in allowing for remote sensing. To maintain the accuracy of the remote sens ing, the GND pin should also be connected close to the load . A voltage error amplifier (gm) amplifies the difference between the output voltage and a programmable reference voltage . The reference voltage is programmed between 1 .1 V and 1.85 V by an internal 5-bit DAC, which reads the code at the voltage identification (VID) pins. (Refer to Table I for the output voltage versus VID pin code information.) Active Voltage Positioning The ADP3164 uses Analog Dev ices Optimal Positioning Tech- nology (ADOPT), a un ique supplemental regulat ion technique that uses active voltage positioning and provides optimal com- pensation for load transients. When implemented, ADOPT adjusts the output voltage as a funct ion of the load current, so that it is always optimally positioned for a load transient. Standard (passive) voltage positioning has poor dynam ic performance, render ing it ineffective under the str ingent repet itive trans ient cond itions required by high performance processors . ADOPT, however, provides a bandwidth for transient response that is limited only by parasitic output inductance. This yields optimal load tran- sient response with the minimum number of output capac itors. Reference Output A 3.0 V reference is available on the ADP3164 . This reference is normally used to accurately set the voltage pos itioning using a resistor divider to the COMP p in. In addition, the reference can be used for other funct ions such as generat ing a regulated voltage with an external ampl ifier. The reference is bypassed with a 1 nF capacitor to ground. It is not intended to drive larger capacitive loads, and it should not be used to prov ide more than 300 A of output current. Cycle-by-Cycle Operation During normal operation (when the output voltage is regulated), the voltage-error ampl ifier and the current comparator are the main control elements. The free running oscillator ramps between 0 V and 3 V. When the voltage on the CT p in reaches 3 V, the oscillator sets the dr iver logic, which sets PWM1 high. During the ON time of Phase 1, the dr iver IC turns on the Phase 1 h igh side MOSFET . The CS+ and CS– p ins mon itor the current through the sense resistor that feeds all of the high side MOSFETs. When the voltage between the two p ins exceeds the threshold level, the dr iver log ic is reset and the PWM1 output goes low . This signals the dr iver IC to turn off the Phase 1 h igh side MOSFET and turn on the Phase 1 low s ide MOSFET. On the next cycle of the osc illator, the dr iver log ic toggles and sets PWM2 high. The current is then steered through the second phase. This cycle continues for each of the PWM outputs .

REV. 0 ADP3164 –7– On each of the follow ing cycles of the osc illator, the outputs cycle between each of the act ive PWM outputs . In each case, the current comparator resets the PWM output low when the VT1 is reached. The current of each phase is sensed with the same resistor and the same comparator, so the current is inherently balanced. As the load current increases, the output voltage starts to decrease . This causes an increase in the output of the voltage error ampl ifier (gm), which in turn leads to an increase in the current comparator threshold VT1, thus tracking the load current. Active Current Sharing The ADP3164 ensures current balance in all the active phases by sensing the current through a s ingle sense resistor. During one phase’s ON time, the current through the respect ive high side MOSFET and inductor is measured through the sense resistor. When the comparator threshold is reached, the high side MOSFET turns off . On the next cycle the ADP3164 switches to the next phase . The current is measured with the same sense resistor and the same internal comparator, ensur ing accurate matching. This scheme is immune to imbalances in the MOSFET’s RDS(ON) and inductor parasitic resistance. If for some reason one of the phases has a short c ircuit failure, the other phases w ill still be limited to their maximum output current (one over the total number phases t imes the total short circuit current limit). If this is not sufficient to supply the load, the output voltage w ill droop and cause the PWRGD output to signal that the output voltage has fallen out of its spec ified range. If one of the phases has an open c ircuit failure, the ADP3164 will detect the open phase and s ignal the problem v ia the PWRGD pin (see Power Good Mon itoring section). Current Sharing in Multi-VRM Applications The ADP3164 includes a SHARE pin to allow multiple VRMs to accurately share load current . In multiple VRM applications, the SHARE pins should be connected together . This pin is a low impedance buffered output of the COMP p in voltage. The output of the buffer is internally connected to set the threshold of the current sense comparator . The buffer has a 400 A sink current, and a 2 mA sourc ing capab ility. The strong pull-up allows one VRM to control the current threshold set po int for all ADP3164s connected together . The ADP3164’s h igh accu- racy current set threshold ensures good current balance between VRMs. Also, the low impedance of the buffer m inimizes no ise pickup on th is trace wh ich is routed to mult iple VRMs . This circuit operates in additi on to the active current sharing between phases of each VRM descr ibed above. Short Circuit Protection The ADP3164 has mult iple levels of short c ircuit protection to ensure fail-safe operation. The sense resistor and the max imum current sense threshold voltage g iven in the specifications set the peak current limit. When the load current exceeds the current l imit, the excess current discharges the output capac itor. When the output volt- age is below the foldback threshold, V FB(LOW), the maximum deliverable output current is cut by reducing the current sense threshold from the current l imit threshold, VCS(CL), to the fold- back threshold, V CS(FOLD) . Along w ith the result ing current foldback, the oscillator frequency is reduced by a factor of f ive when the output is 0 V. This further reduces the average curre n in short circuit. Power Good Monitoring The power good comparator mon itors the output voltage of th e supply via the FB pin. The PWRGD pin is an open drain outpu whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the specified range of the nom i nal output voltage requested by the VID DAC . PWRGD will go low if the output is outside this range. Short circuits in a VRM power path are relat ively easy to detec t in applications where multiple VRMs are connected to a com- mon power plane . VRM power tra in open fa ilures are not as easily spotted, s ince the other VRMs may be able to supply enough total current to keep the output voltage w ithin the power good voltage spec ification even when one VRM is not functioning. The ADP3164 addresses th is problem by mon itor- ing both the output voltage and the sw itch current to determ ine the state of the PWRGD output . The output voltage port ion of the power good mon itor domi- nates; as long as the output voltage is outs ide the spec ified window, PWRGD w ill rema in low . If the output voltage is within specification, a second circuit checks to make sure that current is being del ivered to the output by each phase . If no current is detected in a phase for three consecut ive cycles, it is assumed that an open c ircuit exists somewhere in the power path, and PWRGD will be pulled low. Output Crowbar The ADP3164 includes a crowbar comparator that senses whe n the output voltage r ises higher than the spec ified trip threshold, VCROWBAR. This comparator overrides the control loop and sets both PWM outputs low . The dr iver ICs turn off the h igh side MOSFETs and turn on the low s ide MOSFETs, thus pull ing the output down as the reversed current bu ilds up in the induc- tors. If the output overvoltage is due to a short of the h igh side MOSFET, this action will current-limit the input supply or blow its fuse, protect ing the m icroprocessor from destruct ion. The crowbar comparator releases when the output drops below the specified reset threshold, and the controller returns to normal operation if the cause of the overvoltage fa ilure does not pers ist Output Disable The ADP3164 includes an output d isable function that turns of the control loop to br ing the output voltage to 0 V . Because an extra pin is not available, the disable feature is accomplished by pulling the COMP pin to ground. When the COMP p in drops below 0.8 V, the oscillator stops and all PWM s ignals are driven low. This function does not place the part in low current shut- down and the reference voltage is still ava ilable. The COMP pin should be pulled down w ith an open drain type of output capable of sinking at least 2 mA .

Figure 2. 80 A Intel VRM 9.1-Compliant CPU Supply Circuit

REV. 0 ADP3164 –9–

APPLICATION INFORMATION

The design parameters for a typ ical VRM 9.1-compliant CPU application are as follows: Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.475 V Nominal output voltage at no load (V ONL) = 1.4605 V Nominal output voltage at 80 A load (V OFL) = 1.3845 V Static output voltage drop based on a 0 .95 m load line (ROUT) from no load to full load (V ) = VONL – VOFL = 1.4605 V – 1.3845 V = 76 mV Maximum Output Current (IO) = 81 A Number of Phases (n) = 4 CT Selection—Choosing the Clock Frequency The ADP3164 uses a f ixed-frequency control arch itecture. The frequency is set by an external t iming capacitor, CT. The clock frequency determines the switching frequency, wh ich relates directly to sw itching losses and the s izes of the inductors and input and output capacitors. A clock frequency of 800 kHz sets the switching frequency of each phase, f SW, to 200 kHz, wh ich represents a practical trade-off between the sw itching losses and the sizes of the output filter components. To achieve an 800 kHz oscillator frequency, the required timing capacitor value is 100 pF. For good frequency stab ility and initial accuracy, it is recom- mended to use a capac itor w ith low temperature coeff icient and t ight tolerance, e.g., an MLC capacitor with NPO dielec- tric and with 5% or less tolerance . Inductance Selection The choice of inductance determines the ripple current in the inductor. Less inductance leads to more r ipple current, which increases the output r ipple voltage and the conduct ion losses in the MOSFETs, but allows us ing smaller-size inductors and, for a specified peak-to-peak trans ient deviation, output capacitors with less total capac itance. Conversely, a h igher inductance means lower ripple current and reduced conduct ion losses, but requires larger-size inductors and more output capac itance for the same peak-to-peak trans ient deviation. In a 4-phase con- verter, a pract ical value for the peak-to-peak inductor r ipple current is under 50% of the dc current in the same inductor. A choice of 50% for th is particular design example yields a total peak-to-peak output r ipple current of 8% of the total dc output current. The following equation shows the relat ionship between the inductance, oscillator frequency, peak-to-peak r ipple current in an inductor and input and output voltages . L VV V Vf I IN OUT OUT IN SW L RIPPLE (– ) (1) For 10 A peak-to-peak r ipple current, wh ich is 50% of the

20 A full-load dc current in an inductor, Equation 1 yields an

inductance of: L VV V V kHz A nH (– . ) .12 1 475 1 475 12 800 4 10 646 A 600 nH inductor can be used, wh ich gives a calculated r ipple current of 10.8 A at no load. The inductor should not saturate at the peak current of 26 A, and should be able to handle the sum of the power d issipation caused by the average current of 20 A in the winding and the core loss . The output r ipple current is smaller than the inductor r ipple current due to the four phases part ially canceling. This can be calculated as follows: I nV V nV VL f I VV V V nH kHz A O OUT IN OUT IN OSC O (– ) . (– . ) .4 1 475 12 4 1 475 12 600 800 62 5 (2 Designing an Inductor Once the inductance is known, the next step is either to design an inductor or f ind a standard inductor that comes as close as possible to meeting the overall des ign goals. The first decision i designing the inductor is to choose the core mater ial. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e .g., Kool-M ® from Magnetics, Inc.) and the gapped soft ferr ite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the induc- tor value is relatively low and the r ipple current is high. Two ma in core types can be used in this appl ication. Open magnetic loop types, such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused mag- netic field in the core. The radiated EMI from the d istributed magnetic field may create problems w ith noise interference in the circuitry surrounding the inductor. Closed-loop types, suc h as pot cores, PQ, U, and E cores, or toro ids, cost more, but have much better EMI/RFI performance . A good compromise between price and performance are cores w ith a toroidal shape. There are many useful references for qu ickly designing a power inductor. Table II gives some examples. Table II. Magnetics Design References Magnetic Designer Software Intusoft (http://www .intusoft.com) Designing Magnetic Components for H igh-Frequency DC-DC Converters McLyman, Kg Magnet ics ISBN 1-883107-00-08 Selecting a Standard Inductor The companies listed in Table III can prov ide design consulta- tion and del iver power inductors opt imized for h igh power applications upon request . Table III. Power Inductor Manufacturers Coilcraft (847)639-6400 http://www.coilcraft.com Coiltronics (561)752-5000 http://www.coiltronics.com Sumida Electric Company (408)982-9660 http://www.sumida.com

REV. 0 ADP3164 –10– RSENSE The value of RSENSE is based on the max imum required output current. The current comparator of the ADP3164 has a m ini- mum current limit threshold of 143 mV . Note that the 143 mV value cannot be used for the max imum specified nominal cur- rent, as headroom is needed for ripple current and tolerances . The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IO, which equals twice the peak inductor current value less half of the peak-to- peak inductor ripple current. From this, the maximum value of RSENSE is calculated as: R V I n I mV AA mSENSE CSCL MIN O L RIPPLE () . . 143 10 8 (3) In this case, 5 m was chosen as the closest standard value . Once RSENSE has been chosen, the output current at the po int where current limit is reached, IOUT(CL), can be calculated us ing the maximum current sense threshold of 173 mV: In V R nI I mV m A A OUT CL CSCL MAX SENSE L RIPPLE OUT CL () ( ) . . 4 173 41 0 8 2 116 8 (4) At output voltages below 750 mV, the current sense threshold is reduced to 108 mV, and the r ipple current is negligible. There- fore, at dead short the output current is reduced to: In V R mV m AOUT SC CS SC SENSE () . 4 108 5 86 4 (5) To safely carry the current under max imum load conditions, the sense resistor must have a power rat ing of at least: PI RR SENSE RMS SENSESENSE 2 (6) where: I I n V V SENSE RMS O OUT IN (7) In this formula, n is the number of phases, and is the con- verter efficiency, in this case assumed to be 85% . Combining Equations 6 and 7 yields: P AV V mWRSENSE 1 475 08 5 1 2 51 2 . . Output Resistance This design requires that the regulator output voltage measured at the CPU drop when the output current increases. The speci- fied voltage drop corresponds to a dc output res istance of: R VV I VV A mOUT ONL OFL O 1 4605 1 3845 80 09 5.. . (8) The required dc output resistance can be achieved by terminating the gm amplifier with a resistor. The value of the total term ina- tion resistance that will yield the correct dc output res istance: R nR ng R m mmho m kT I SENSE m OUT 12 5 5 42 2 0 9 5 74 8. .. . (9) where nI is the division ratio from the output voltage s ignal of the gm ampl ifier to the PWM comparator CMP1, gm is the transconductance of the g m amplifier itself, and n is the number of phases. Output Offset Intel’s VRM 9.1 specification requires that at no load the nominal output voltage of the regulator be offset to a lower value than the nominal voltage corresponding to the VID code to make sure that circuit tolerances never cause the output voltage to exceed the VID value. The offset is introduced by realizing the total termina- tion resistance of the g m amplifier with a divider connected between the REF p in and ground . The res istive divider introduces an offset to the output of the gm amplifier that, when reflected back through the gain of the gm stage, accurately positions the output voltage near its allowed maximum at light load. Furthermore, the output of the gm amplifier sets the current sense threshold voltage. At no load, the current sense threshold is increased by the peak of the ripple current in the inductor and reduced by the delay between sensing when the current threshold has been reached and when the high side MOSFET actually turns off. These two factors are combined with the inherent voltage (VGNL0), at the output of the gm amplifier that commands a current sense threshold of 0 mV: VV IR n VV L nt R n VV Am V V nH ns m V GNL GNL L RIPPLE SENSE I IN OUT D SENSE I GNL 1 10 8 5 12 5 12 1 475 600 4 60 5 12 5 1 074 .. . (10) The divider resistors (RA for the upper and R B for the lower) can now be calculated, assum ing that the internal resistance of the gm amplifier (ROGM) is 1 M: R V VV R gV V R V VV k mmho V V k B REF REF GNL T m ONL VID B . . ( .. ) 3 1 074 74 8 2 2 1 4605 1 475 10 37 (11) Choosing the nearest 1% res istor value gives RB = 10.5k . Finally, RA is calculated: R RR R k M k kA T OGM B 111 74 8 10 5 26 7 (12) Choosing the nearest 1% res istor value gives RA = 26.7k .

REV. 0 ADP3164 –11– COUT Selection The required equivalent series resistance (ESR) and capac itance drive the selection of the type and quant ity of the output capac i- tors. The ESR must be less than or equal to the spec ified output resistance (ROUT), in this case 0.95 m. The capacitance must be large enough that the voltage across the capac itors, which is the sum of the res istive and capacitive voltage deviations, does not deviate beyond the initial resistive step while the inductor current ramps up or down to the value correspond ing to the new load current. One can, for example, use th irteen SP-Type OS-CON capac i- tors from Sanyo, w ith 820 F capacitance, a 4 V voltage rat ing, and 12 m ESR. The ten capacitors have a maximum total ESR of 0.92 m when connected in parallel. As long as the capac itance of the output capac itor bank is above a critical value and the regulat ing loop is compensated w ith Analog Devices’ proprietary compensation technique (ADOPT), the actual capacitance value has no influence on the peak-to- peak deviation of the output voltage to a full step change in the load current. The critical capacitance can be calculated as follows: C I RV L n A mV nH mF OUT CRIT O OUT OUT .. . 0 95 1 475 600 4 85 6 (13) The critical capacitance limit for this circuit is 8.56 mF, while the actual capac itance of the th irteen OS-CON capac itors is 820 F = 10.66 mF. In this case, the capacitance is safely above the critical value. Multilayer ceramic capacitors are also required for high-frequency decoupling of the processor . The exact number of these MLC capacitors is a function of the board layout space and paras itics. Typical designs use twenty to th irty 10 F MLC capacitors located as close to the processor power p ins as is practical. Feedback Loop Compensation Design for ADOPT Optimized compensation of the ADP3164 allows the best pos- sible containment of the peak-to-peak output voltage dev iation. Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load . Therefore, any sudden change of load current w ill initially flow through the output capac itors, and assum ing that the capac itance of the output capac itor is larger than the cr itical value defined by Equation 13, this will produce a peak output voltage dev iation equal to the ESR of the output capacitor times the load current change . The optimal implementation of voltage pos itioning, ADOPT, will create an output impedance of the power converter that is entirely resistive over the widest possible frequency range, includ- ing dc, and equal to the max imum acceptable ESR of the output capacitor array. With the resistive output impedance, the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output capac itor bank. With an ideal current-mode-controlled converter, where the average inductor current would respond w ithout delay to the command s ignal, the res istive output impedance could be achieved by having a single-pole roll-off of the voltage ga in of the voltage-error ampl ifier. The pole frequency must co incide with the ESR zero of the output capac itor bank. The ADP3164 uses constant frequency current-mode control, wh ich is known to have a nonideal, frequency-dependent command s ignal to inductor current transfer funct ion. The frequency dependence manifests in the form of a pa ir of complex conjugate poles at one-half of the sw itching frequency. A purely resistive output impedance could be achieved by canceling the complex conjugate poles with zeros at the same complex frequenc ies and adding a third pole equal to the ESR zero of the output capac itor. Such compensating network would be quite complicated. Fortunately, i practice it is sufficient to cancel the pa ir of complex conjugate poles with a single real zero placed at one-half of the sw itching frequency. Although the end result is not a perfectly res istive output impedance, the rema ining frequency dependence cause s only a small percentage of dev iation from the ideal res istive response. The single-pole and single-zero compensation can easily be implemented by terminating the gm error amplifier with the parallel combination of a resistor (RT) and a series RC network The value of the term inating resistor RT was previously deter- mined; the capacitance and resistance of the ser ies RC network are calculated as follows: C CR R n fR C mF m k kHz k nF OC OUT OUT T OSC T OC 10 7 0 92 74 8 800 7 48 11.. .. . (14 The nearest standard value of COC is 1 nF. The resistance of th zero-setting resistor in series with the compensating capacitor is R n f C kHz nF kZ OSC OC 800 1 15 9. (15 The nearest standard 5% res istor value is 1.5 k. Note that this resistor is only required when COUT approaches CCRIT (within 25% or less) . In th is example, C OUT is approach ing CCRIT, so RZ should be included. Power MOSFETs In this example, eight N-channel power MOSFETs must be used; four as the main (control) switches, and the rema ining four as the synchronous rectifier switches. The main selection parameters for the power MOSFETs are V GS(TH) , QG and R DS(ON) . The minimum gate drive voltage (the supply voltage to the ADP3414) dictates whether standard threshold or log ic-level threshold MOSFETs must be used . Since VGATE <8 V, logic-level thresh- old MOSFETs (VGS(TH) < 2.5 V) are strongly recommended .

REV. 0 ADP3164 –12– The maximum output current IO determines the RDS(ON) require- ment for the power MOSFETs. When the ADP3164 is operating in cont inuous mode, the s implifying assumpt ion can be made that in each phase one of the two MOSFETs is always conducting the average inductor current. For VIN =12 V and VOUT = 1.475 V, the duty ratio of the high-side MOSFET is: D V V V V HSF OUT IN 1 475 12 12 3. . % (16) The duty ratio of the low-side (synchronous rectifier) MOSFET is: DDLSF MAX HSF MAX() () . % 18 7 7 (17) The maximum rms current of the h igh-side MOSFET during normal operation is: I I n D I I AA A A HSF MAX O HSF L RIPPLE O . . . 4 0 123 1 10 8 38 0 70 2 (18) The maximum rms current of the low-s ide MOSFET during normal operation is: II D D AA LSF MAX HFS MAX LSF HSF () () . . . . 70 2 0 877 0 123 18 75 (19) The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the max imum output power is allowed for MOSFET dissipation, the total dissipation in the eight MOSFETs of the 4-phase converter w ill be: PV I PV A W FET TOTAL MIN O FET TOTAL .. . 0 1 1 3845 80 11 08 (20) Allocating half of the total d issipation for the four h igh-side MOSFETs and half for the four low-s ide MOSFETs, and assuming that the resistive and switching losses of the high-side MOSFETs are equal, the requ ired maximum MOSFET resis- tances will be: R P nI R W A m DS ON HSF FET TOTAL HSF MAX DS ON HSF 11 08 447 0 2 14 (21) and: R P nI R W A m DS ON LSF FET TOTAL LSF MAX DS ON LSF . . 11 08 2 4 18 75 39 4 (22) Note that there is a trade-off between converter eff iciency and cost. Larger MOSFETs reduce the conduct ion losses and allow higher eff iciency, but increase the system cost . A Fa irchild FDB7030L (RDS(ON) = 7 m nominal, 10 m worst-case) for the high-side and a Fairchild FDB8030L (RDS(ON) = 3.1 m nominal, 5.6 m worst-case) for the low-s ide are good choices. The high-side MOSFET dissipation is: PR I VI Q f I VQ f Pm A V A nC kHz A V nC kHz W HSF DS ON HSF HSF MAX IN L PK G SW G IN RR SW HSF () ( ) 10 7 02 12 26 35 200 12 150 200 1 95 (23) Where the first term is the conduction loss of the MOSFET, the second term represents the turn-off loss of the MOSFET and the third term represents the turn-on loss due to the stored charge in the body diode of the low-side MOSFET. In the sec- ond term, Q G is the gate charge to be removed from the gate for turn-off and IG is the gate turn-off current . From the data sheet, for the FDB7030L the value of Q G is about 35 nC and the peak gate drive current prov ided by the ADP3414 is about 1 A . In the third term, Q RR, is the charge stored in the body d iode of the low-side MOSFET at the valley of the inductor current. The data sheet of the FDB8030L does not g ive that information, so an estimated value of 150 nC is used. This estimate is based on information found on data sheets of s imilar devices. In both terms, fSW is the actual switching frequency of the MOSFETs, or 200 kHz. IL(PK) is the peak current in the inductor, or 26 A. The worst-case low-s ide MOSFET dissipation is: PR I Pm A W LSF DS ON LSF LSF MAX LSF () ( ) .. . 25 6 18 75 1 97 (24) Note that there are no switching losses in the low-side MOSFET. CIN Selection and Input Current di/dt Reduction In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave w ith a duty ratio equal to V OUT/VIN and an ampl itude of one-half of the maximum output current. To prevent large voltage trans ients, a low ESR input capac itor s ized for the max imum rms current must be used. The maximum rms capacitor current is given by: I I n nD nD I A A C RMS O HSF HSF C RMS –( ) . ( . ) 280 4 4 0 123 4 0 123 10 (25) Note that the capac itor manufacturer’s r ipple current ratings are often based on only 2000 hours of l ife. This makes it advisable to further derate the capac itor, or to choose a capac itor rated at a higher temperature than requ ired. Several capacitors may be placed in parallel to meet s ize or height requirements in the design. In this example, the input capacitor bank is formed by three 270 F, 16 V OS-CON capac itors with a ripple current rating of 4.4 A each.

REV. 0 ADP3164 –13– The ripple voltage across the three paralleled capac itors is: V I n ESR n D nC f Am F kHz mV C RIPPLE OC C HSF CI N S W 0 123 3 270 200 135 (26) Multilayer ceramic input capacitors are also requ ired. These capacitors should be placed between the Input s ide of the cur- rent sense resistor and the sources of the low-s ide synchronous MOSFETs. These capacitors decouple the h igh-frequency lead- ing edge current sp ike that supplies the reverse recovery charge of the low-side MOSFET’s body d iode. The exact number required is a function of the board layout . Typical designs will use two 10 F MLC capacitors. To reduce the input-current di/ dt to below the recommended max imum of 0.1 A/s, an addi- tional small inductor (L > 1 H @ 15 A) should be inserted between the converter and the supply bus . That inductor also acts as a filter between the converter and the primary power source. LAYOUT AND COMPONENT PLACEMENT GUIDELINES The following guidelines are recommended for opt imal perfor- mance of a switching regulator in a PC system. General Recommendations 1. For good results, at least a four-layer PCB is recommended. This should allow the needed versat ility for control c ircuitry interconnections with optimal placement, a s ignal ground plane, power planes for both power ground and the input power (e.g., 12 V), and wide interconnection traces in the rest of the power del ivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a res istance of ~0.53 m at room temperature . 2. Whenever h igh currents must be routed between PCB layers, vias should be used l iberally to create several parallel current paths so that the res istance and inductance intro- duced by these current paths is minimized and the v ia current rating is not exceeded. 3. If critical s ignal l ines ( including the voltage and current sense l ines of the ADP3164) must cross through power circuitry, it is best if a s ignal ground plane can be inter- posed between those s ignal l ines and the traces of the power circuitry. This serves as a sh ield to minimize noise injection into the signals at the expense of mak ing signal ground a bit noisier. 4. The power ground plane should not extend under s ignal components, including the ADP3164 itself. If necessary, follow the preceding guideline to use the s ignal ground plane as a shield between the power ground plane and the signal circuitry. 5. The GND pin of the ADP3164 should be connected f irst to the timing capac itor (on the CT p in), and then into the signal ground plane. In cases where no s ignal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used . 6. The output capacitors of the power converter should be connected to the s ignal ground plane even though power current flows in the ground of these capac itors. For this reason, it is advised to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capac itors. It i also advised to keep the planar interconnection path short (i.e., have input and output capac itors close together) . 7. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors should also be d istributed, and generally in pro- portion to where the load tends to be more dynam ic. 8. Absolutely avoid crossing any signal lines over the switchin power path loop, descr ibed below. Power Circuitry 9. The switching power path should be routed on the PCB t o encompass the smallest poss ible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problem in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the power MOSFETs, and the power Schottky diode, if used (see next), including all intercon- necting PCB traces and planes . The use of short and w ide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommo- dates the high current demand w ith minimal voltage loss. 10. MLC input capacitors should be placed between V IN and Power Ground as close as possible to the sources of the low-side MOSFETs . 11. To dampen ringing, an RC Snubber circuit should be placed from the SW node of each phase to ground. 12. An opt ional power Schottky d iode (3 A–5 A dc rat ing) from each lower MOSFET’s source (anode) to dra in (cath ode) will help to minimize switching power dissipation in the upper MOSFETs. In the absence of an effect ive Schot tky diode, this dissipation occurs through the follow ing sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turn ing on (necessar to prevent cross-conduct ion). The c irculat ing current in the power converter, no longer f inding a path for curre n through the channel of the lower MOSFET, draws cur- rent through the inherent body diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery charac - teristic of the lower MOSFET’s body d iode prevents the drain voltage from be ing pulled high quickly. The upper MOSFET then conducts very large current while it momen- tarily has a high voltage forced across it, which translates into added power d issipation in the upper MOSFET . The Schottky diode minimizes this problem by carry ing a major ity of the circulating current when the lower MOSFET is turned off, and by v irtue of its essent ially nonex istent reverse recovery t ime. The Schottky diode has to be con- nected w ith very short copper traces to the MOSFET t o be effect ive.

1. Whenever a power d issipating component (e.g., a power MOSFET) is soldered to a PCB, the l iberal use of vias, both directly on the mount ing pad and immediately sur- rounding it, is recommended. Two important reasons for this are: improved current rat ing through the vias, and improved thermal performance from v ias extended to the opposite side of the PCB where a plane can more read ily transfer the heat to the a ir. 14. The output power path, though not as cr itical as the switch- ing power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sens ing resistor, the out- put capacitors, and back to the input capacitors. 15. For best EMI conta inment, the power ground plane should extend fully under all the power components except the out- put capacitors. These components are: the input capacitors, the power MOSFETs and Schottky d iodes, the inductors, the current sense res istor, and any snubb ing element that might be added to dampen r inging. Avoid extending the power ground under any other c ircuitry or s ignal l ines, including the voltage and current sense l ines. Signal Circuitry 16. The output voltage is sensed and regulated between the FB pin and the GND pin (which connects to the s ignal ground plane). The output current is sensed (as a voltage) by the CS+ and CS– pins. In order to avo id differential mode noise pickup in the sensed signal, the loop area should be small. Thus the FB trace should be routed atop the s ignal ground plane, and the CS+ and CS– p ins (the CS+ pin should be over the s ignal ground plane as well) . 17. The CS+ and CS– traces should be Kelv in-connected to the current sense res istor, so that the add itional voltage drop due to current flow on the PCB at the current sense resistor connections, does not affect the sensed voltage . Rev. 2 | Page 14 of 15 | www.onsemi.com

(RU-20) 20 11 101 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 0.260 (6.60) 0.252 (6.40) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) OUTLINE DIMENSIONS Dimensions shown in inches and (mm) . Model Temperature Range Package Description Package Option ADP3164JRU-REEL 0°C to 70°C Thin Shrink Small Outline RU-20 (TSSOP-20) ADP3164RU-REEL7 0°C to 70°C Thin Shrink Small Outline RU-20 (TSSOP-20) ADP3164RUZ-R7 1 0°C to 70°C Thin Shrink Small Outline RU-20 (TSSOP-20) 1Z = Pb-Free part ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserve s the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC ass ume any liability arising out of the application or use of any product or circuit, and speci fi cally disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may b e provided in SCILLC data sheets and/or speci fi cations can and do vary in different applications and actual performance may vary over time. All operating parameters, includin g “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical im plant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purcha se or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its of fi cers, employees, subsidiaries, af fi liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out o f, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding th e design or manufacture of the part. SCILLC is an Equal Opportunity/Af fi rmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support : 800-282-9855 Toll Free USA/Canada. Europe, Middle East and Africa Technical Support : Phone: 421 33 790 2910 Japan Customer Focus Cente r Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative PUBLICATION ORDERING INFORMATION