ADP3158JR

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REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADP3158/ADP3178 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 4-Bit Programmable Synchronous Buck Controllers FUNCTIONAL BLOCK DIAGRAM gm CMP DRVH LRDRV2 LRFB2 LRFB1 LRDRV1 COMP DRVL GND CS– CS+ PWM DRIVE VCC CT OSCILLATOR UVLO & BIAS REFERENCE REF VLR1 VLR2 REF VID DAC DAC+20% ADP3158/ADP3178 VID3 VID2 VID1 VID0

FEATURES

Optimally Compensated Active Voltage Positioning with Gain and Offset Adjustment (ADOPT™) for Superior Load Transient Response Complies with VRM Specifications with Lowest System Cost 4-Bit Digitally Programmable 1.3 V to 2.05 V Output N-Channel Synchronous Buck Driver Total Accuracy /H115500.8% Over Temperature Two On-Board Linear Regulator Controllers Designed to Meet System Power Sequencing Requirements High Efficiency Current-Mode Operation Short Circuit Protection for Switching Regulator Overvoltage Protection Crowbar Protects Micro- processors with No Additional External Components

APPLICATIONS

Core Supply Voltage Generation for: Intel Pentium ® III Intel Celeron™ GENERAL DESCRIPTION The ADP3158 and ADP3178 are highly efficient synchronous buck switching regulator controllers optimized for converting a

5 V main supply into the core supply voltage required by high-

performance processors. These devices use an internal 4-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.3 V and 2.05 V. They use a current mode, constant off-time archi- tecture to drive two N-channel MOSFETs at a programmable switching frequency that can be optimized for regulator size and efficiency. The ADP3158 and ADP3178 also use a unique supplemental regulation technique called Analog Devices Optimal Positioning Technology (ADOPT) to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high- performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so it is always optimally positioned for a system transient. They also provide accurate and reliable short circuit protection and adjustable current limiting. The devices include an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 20%. The ADP3158 and ADP3178 contain two linear regulator controllers that are designed to drive external N-channel MOSFETs. The outputs are internally fixed at 2.5 V and 1.8 V in the ADP3158, while the ADP3178 provides adjustable out- puts that are set using an external resistor divider. These linear regulators are used to generate the auxiliary voltages (AGP, GTL, etc.) required in most motherboard designs, and have been designed to provide a high bandwidth load- transient response. The ADP3158 and ADP3178 are specified over the commercial temperature range of 0°C to 70°C and are available in a 16-lead SOIC package. ADOPT is a trademark of Analog Devices, Inc. Pentium is a registered trademark of Intel Corporation. Celeron is a trademark of Intel Corporation.

REV. A–2– ADP3158/ADP3178–SPECIFICATIONS(VCC = 12 V, TA = 0/H11543C to 70/H11543C, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit SWITCHING REGULATOR Output Accuracy V CS– 1.3 V Output Figure 1 1.289 1.3 1.311 V 1.65 V Output Figure 1 1.637 1.65 1.663 V 2.05 V Output Figure 1 2.034 2.05 2.066 V Line Regulation ∆VOUT VCC = 10 V to 14 V 0.06 % Crowbar Trip Point V CROWBAR % of Nominal DAC Voltage 115 120 125 % Crowbar Reset Point % of Nominal DAC Voltage 40 50 60 % Crowbar Response Time t CROWBAR Overvoltage to DRVL Going High 400 ns VID INPUTS Input Low Voltage V IL(VID) 0.6 V Input High Voltage V IH(VID) 2.0 V Input Current I VID VID(X) = 0 V 185 250 µA Pull-Up Resistance R VID 20 30 k Ω Internal Pull-Up Voltage 5.0 5.4 5.7 V OSCILLATOR Off Time T A = 25°C, CT = 200 pF 3.5 4.0 4.5 µs CT Charge Current I CT TA = 25°C, VOUT in Regulation 130 150 170 µA TA = 25°C, VOUT = 0 V 2 53 54 5 µA ERROR AMPLIFIER Output Resistance R O(ERR) 1M Ω Transconductance g m(ERR) 2.05 2.2 2.35 mmho Output Current I O(ERR) CS– Forced to VOUT – 3% 625 µA Maximum Output Voltage V COMP(MAX) CS– Forced to VOUT – 3% 3.0 V Output Disable Threshold V COMP(OFF) 600 750 900 mV –3 dB Bandwidth BW ERR COMP = Open 500 kHz CURRENT SENSE Threshold Voltage V CS(TH) CS– Forced to VOUT – 3% 69 78 87 mV CS– ≤ 0.45 V 35 45 54 mV

0.8 V ≤ COMP ≤ 1 V 1 5 mV

Input Bias Current I CS+, ICS– CS+ = CS– = VOUT 0.5 5 µA Response Time t CS CS+ – (CS–) > 87 mV to DRVH 50 ns Going Low OUTPUT DRIVERS Output Resistance R O(DRV(X)) IL = 50 mA 6 Ω Output Transition Time t R, tF CL = 3000 pF 80 ns LINEAR REGULATORS Feedback Current I FB(X) 0.3 1 µA LR1 Feedback Voltage V LRFB(1) ADP3158, Figure 2, 2.44 2.5 2.56 V VCC = 4.5 V to 12.6 V ADP3178, Figure 2, 0.97 1.0 1.03 V VCC = 4.5 V to 12.6 V LR2 Feedback Voltage V LRFB(2) ADP3158, Figure 2, 1.75 1.8 1.85 V VCC = 4.5 V to 12.6 V ADP3178, Figure 2, 0.97 1.0 1.03 V VCC = 4.5 V to 12.6 V Driver Output Voltage V LRDRV(X) VCC = 4.5 V, VLRFB(X) = 0 V 4.2 V SUPPLY DC Supply Current2 ICC 79 m A UVLO Threshold Voltage V UVLO 6.75 7 7.25 V UVLO Hysteresis 0.8 1 1.2 V NOTES 1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs. Specifications subject to change without notice.

REV. A ADP3158/ADP3178 –3– ABSOLUTE MAXIMUM RATINGS * θJA *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to GND. PIN CONFIGURATION TOP VIEW (Not to Scale) VID0 VID1 VID2 VID3 LRFB1 LRDRV1 CS – CS+ GND DRVH DRVL VCC LRFB2 LRDRV2 COMP CT ADP3158/ ADP3178 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1–4 VID0–VID3 Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a Logic 1 if left open. The DAC output programs the CS– regulation voltage from 1.3 V to 2.05 V. 5, 12 LRFB1, Feedback connections for the linear LRFB2 regulator controllers. 6, 11 LRDRV1, Gate drives for the respective linear LRDRV2 regulator N-channel MOSFETs. 7 CS– Current Sense Negative Node. Negative input for the current comparator. This pin also connects to the internal error ampli- fier that senses the output voltage. 8 CS+ Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to CS–.

9 CT External capacitor connected from CT to

ground sets the Off-time of the device.

10 COMP Error Amplifier Output and Compensation

Point. The voltage at this output programs the output current control level between CS+ and CS–. 13 VCC Supply Voltage for the device. 14 DRVL Low-Side MOSFET Drive. Gate drive for the synchronous rectifier N-channel MOSFET. The voltage at DRVL swings from GND to VCC. 15 DRVH High- Side MOSFET Drive. Gate drive for the buck switch N-channel MOSFET. The voltage at DRVH swings from GND to VCC. 16 GND Ground Reference. GND should have a low impedance path to the source of the synchronous MOSFET. ORDERING GUIDE Temperature LDO Package Package Model Range Voltage Description Option ADP3158JR 0 °C to 70°C 2.5 V, 1.8 V SO = Small Outline Package R-16A (SO-16) ADP3178JR 0 °C to 70°C Adjustable SO = Small Outline Package R-16A (SO-16) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3158/ADP3178 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

REV. A ADP3158/ADP3178 –6– VID0 VID1 VID2 VID3 LRFB1 LRDRV1 CS – CS+ GND DRVH DRVL VCC LRFB2 LRDRV2 COMP CT FROM CPU 100/H9262F C15 1/H9262F 100/H9262F Q2 * C12 1/H9262F Q1 * C3 150pF R B 10.5k/H9024 R A 78.7k/H9024 C OC 2.7nF 3.3V C17 C18 C19 C20 C21 VLR2 1.8V, R12 4m /H9024 1.7/H9262H Q4 * Q3 ** 1000/H9262F 1000/H9262F 22/H9262F 1/H9262H VCC CORE 1.30V TO 2.05V 15A 5V STANDBY 12V MBR052LT1 MBR052LT1 VLR1 2.5V, 2A 1/H9262F 220/H9024 220/H9024 C10 1nF 3.3V ADP3158/ ADP3178 +++++ +++ *SUB45N03-13L **SUB75N03-07 68pF C11 68pF 10k/H9024 R11 10k/H9024 1000/H9262F /H11547 5 24m /H9024 (EACH) Figure 3. 15 A Pentium III Application Circuit

12 V supply has risen above the UVLO value, the switching regula-

tor will begin its start-up sequence.

APPLICATION INFORMATION

Specifications for a Design Example The design parameters for a typical 750 MHz Pentium III appli- cation (shown in Figure 3) are as follows: Input Voltage: (VIN) = 5 V Auxiliary Input: (VCC) = 12 V Output Voltage (VVID) = 1.7 V Maximum Output Current (I O(MAX)) = 15 A Minimum Output Current (I O(MIN)) = 1 A Static tolerance of the supply voltage for the processor core (∆VO) = +40 mV (–80 mV) = 120 mV Transient tolerance (for less than 2 µs) of the supply voltage for the processor core when the load changes between the minimum and maximum values with a di/dt of 20 A/ µs (∆VO(TRANSIENT)) = +80 mV (–130 mV) = 210 mV Input current di/dt when the load changes between the mini- mum and maximum values < 0.1 A/ µs. The above requirements correspond to Intel’s published power supply requirements based on VRM 8.4 guidelines.

REV. A ADP3158/ADP3178 –7– CT Selection for Operating Frequency The ADP3158 and ADP3178 use a constant off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high-side N-channel MOSFET switch turns on, the volt- age across CT is reset to 0 V. During the off-time, CT is charged by a constant current of 150 µA. Once CT reaches 3.0 V, a new on-time cycle is initiated. The value of the off-time is calculated using the continuous-mode operating frequency. Assuming a nominal operating frequency (f NOM) of 200 kHz at an output volt- age of 1.7 V, the corresponding off-time is: t V Vf t V V kHz s OFF OUT IN NOM OFF =   × =−  ×= 1 1 1 17 200 33 . . µ (1) The timing capacitor can be calculated from the equation: C tI V sA V pFT OFF CT TT H = × = µ× µ ≈ .3 3 150 3 150 (2) (3) f t VI R R R V VI R R R R MIN OFF IN O MAX DS ON HSF SENSE L OUT IN O MAX DS ON HSF SENSE L DS ON LSF =× ×+ + ×+ + 1 – () – – ( – ) () ( ) ( ) () () ) The converter only operates at the nominal operating frequency at the above-specified V OUT and at light load. At higher values of VOUT, or under heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at V OUT = 1.7 V is calculated to be 195 kHz (see Equation 3), where: RDS(ON)HSF is the resistance of the high-side MOSFET (estimated value: 14 m Ω ) RDS(ON)LSF is the resistance of the low-side MOSFET (estimated value: 6 m Ω ) RSENSE is the resistance of the sense resistor (estimated value: 4 m Ω ) RL is the resistance of the inductor (estimated value: 3 m Ω ) Inductance Selection The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs, but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, output capacitors with less total capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. The following equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor and input and output voltages. L Vt I OUT OFF L RIPPLE = × (4) For 4 A peak-to-peak ripple current, which corresponds to approximately 25% of the 15 A full-load dc current in an inductor, Equation 4 yields an inductance of L Vs A H= ×µ =µ17 33 4 14.. . A 1.5 µH inductor can be used, which gives a calculated ripple current of 3.8 A at no load. The inductor should not saturate at the peak current of 17 A and should be able to handle the sum of the power dissipation caused by the average current of 15 A in the winding and the core loss. Designing an Inductor Once the inductance is known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequen- cies. Two examples are the powder cores (e.g., Kool-Mµ ® from Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. Two main core types can be used in this application. Open magnetic loop types, such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused mag- netic f ield in the core. The radiated EMI from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor. Closed-loop types, such as pot cores, PQ, U, and E cores, or toroids, cost more, but have much better EMI/RFI performance. A good compromise between price and performance are cores with a toroidal shape.

REV. A ADP3158/ADP3178 –8– There are many useful references for quickly designing a power inductor. Table II gives some examples. Table II. Magnetics Design References Magnetic Designer Software Intusoft (http://www.intusoft.com) Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-08 Selecting a Standard Inductor The companies listed in Table III can provide design consul- tation and deliver power inductors optimized for high power applications upon request. Table III. Power Inductor Manufacturers Coilcraft (847) 639-6400 http://www.coilcraft.com Coiltronics (561) 752-5000 http://www.coiltronics.com Sumida Electric Company (408) 982-9660 http://www.sumida.com COUT Selection—Determining the ESR The required equivalent series resistance (ESR) and capacitance drive the selection of the type and quantity of the output ca paci- tors. The ESR must be small enough to contain the voltage deviation caused by a maximum allowable CPU transient cur- rent within the specified voltage limits, giving consideration also to the output ripple and the regulation tolerance. The capaci- tance must be large enough t hat the voltage across the capacitor, which is the sum of the resistive and capacitive voltage deviations, does not deviate beyond the initial resistive deviation while the inductor current ramps up or down to the value corresponding to the new load current. The maximum allowed ESR also repre- sents the maximum allowed output resistance, R OUT. The cumulative errors in the output voltage regulation cuts into the available regulation window, VWIN. When considering dynamic load regulation this relates directly to the ESR. When consider- ing dc load regulation, this relates directly to the programmed output resistance of the power converter. Some error sources, such as initial voltage accuracy and ripple voltage, can be directly deducted from the available regulation window, while other error sources scale proportionally to the amount of voltage positioning used, which, for an optimal design, should utilize the maximum that the regulation window will allow. The error determination is a closed-loop calculation, but it can be closely approximated. To maintain a conservative design while avoiding an impractical design, various error sources should be considered and summed statistically. The output ripple voltage can be factored into the calculation by summing the output ripple current with the maximum output current to determine an effective maximum dynamic current change. The rem aining errors are summed separately according to the formula: VV V k I II k k kk m V WIN VID VID O OO RCS CSF RT EA =× × + +   ++ ( – ) 1 2 95 (5) where kVID = 0.5% is the initial programmed voltage tolerance from the graph of TPC 6, kRCS = 2% is the tolerance of the current sense resistor, kCSF = 10% is the summed tolerance of the current sense filter components, kRT = 2% is the tolerance of the two termination resistors added at the COMP pin, and kEA = 8% accounts for the IC current loop gain tolerance including the gm tolerance. The remaining window is then divided by the maximum output current plus the ripple to determine the maximum allowed ESR and output resistance: RR V II mV AA mE MAX OUT MAX WIN OO () () .== + = + = Ω95 15 3 8 5 (6) The output filter capacitor bank must have an ESR of less than 5 mΩ . One can, for example, use five ZA series capacitors from Rubycon which would give an ESR of 4.8 m Ω . Without ADOPT voltage positioning, the ESR would need to be less than 3 mΩ , yielding a 50% increase to eight Rubycon output capacitors. COUT —Checking the Capacitance As long as the capacitance of the output capacitor is above a critical value and the regulating loop is compensated with ADOPT, the actual value has no influence on the peak-to-peak deviation of the output voltage to a full step change in the load current. The critical capacitance can be calculated as follows: C I RV L A m Hm F OUT CRIT O EO U T . .. = × × = Ω× ×µ =15 51 7 15 26 (7) The critical capacitance for the five ZA series Rubycon capaci- tors is 2.6 mF while the equivalent capacitance is 5 mF. The capacitance is safely above the critical value.

REV. A ADP3158/ADP3178 –9– RSENSE The value of RSENSE is based on the maximum required output current. The current comparators of the ADP3158 and ADP3178 have a minimum current limit threshold of 69 mV. Note that the 69 mV value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and tolerances. The current comparator threshold sets the peak of the inductor current yielding a maximum output current, I O, which equals twice the peak inductor current value less half of the peak-to-peak induc- tor ripple current. From this the maximum value of R SENSE is calculated as: R V I I mV AA mSENSE CS CL MIN O L RIPPLE = + =Ω() ( ) () . 15 1 9 4 (8) In this case, 4 mΩ was chosen as the closest standard value. Once RSENSE has been chosen, the output current at the point where current limit is reached, I OUT(CL), can be calculated using the maximum current sense threshold of 87 mV: I V R I mV m A A OUT CL CS CL MAX SENSE L RIPPLE () ( ) ( ) – – . = Ω ≈ 2 20 (9) At output voltages below 450 mV, the current sense threshold is reduced to 54 mV, and the ripple current is negligible. There- fore, at dead short the output current is reduced to: I mV m AOUT SC() .= Ω =54 4 13 5 (10) To safely carry the current under maximum load conditions, the sense resistor must have a power rating of at least: PI R A m WR O SENSESENSE =× = × Ω =() ( ) .22 20 4 1 6 (11) Power MOSFETs Two external N-channel power MOSFETs must be selected for use with the ADP3158 and ADP3178, one for the main switch and an identical one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage (V GS(TH)) and the ON-resistance (RDS(ON)). The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (V GS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum value of VCC should be used. The maximum output current IO(MAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3158 and ADP3178 are operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VOUT =

1.65 V, the maximum duty ratio of the high-side FET is:

– () – (. ) % =× µ = 1 195 3 3 36 (12) The maximum duty ratio of the low-side (synchronous rectifier) MOSFET is: DDLSF MAX HSF MAX() () – %==15 4 (13) The maximum rms current of the high-side MOSFET is: ID II I I I AA A A A rms RMSHSF HSF MAX L VALLEY L VALLEY L PEAK L PEAK RMSHSF =× +× + =× +×+ = () () ( ) ( ) () 36 13 1 13 1 16 1 16 1 3 88 (14) The maximum rms current of the low-side MOSFET is: ID II I I I AA A A A rms RMSLSF LSF MAX L VALLEY L VALLEY L PEAK L PEAK RMSLSF =× +× + =× +×+ = () () ( ) ( ) 54 13 1 13 1 16 1 16 1 3 10 8 (15) The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation will be: PV I WD FETs OUT OUT MAX() ( ) ..=× × =01 22 6 (16) Allocating half of the total dissipation for the high-side MOSFET and half for the low-side MOSFET and assuming that switching losses are small relative to the dc conduction losses, the required minimum MOSFET resistances will be: R P I W A mDS ON HSF HSF HSF .≤= = Ω22 11 3 88 15 (17) R P I W A mDS ON LSF LSF LSF .≤= = Ω22 11 3 10 8 10 (18)

10 mΩ worst-case) for the low-side are good choices. removed from the gate for turn-off and I G is the gate current. provided by the ADP3159 is about 1 A. Note that there are no switching losses in the low-side MOSFET. help move the heat away from the package. rent can be tolerated, so three capacitors in parallel are adequate. the converter and the supply bus. ESR of the output capacitor array times the load current change. Figure 4. Transient Response of the Circuit of Figure 3

Figure 5. Efficiency vs. Load Current of the Circuit transconductance of the g m amplifier itself. would determine how the regulation band is centered (i.e., offset). under no load condition. This offset is given by Equation 30. The nearest 1% value of 10.5 k Ω was chosen for RB. The closest standard value for COC is 2.7 nF.

Figure 6. Adding Overcurrent Protection to the provide a well-regulated ± 2.5% accurate output voltage. tion will be based on the actual heatsink used.

REV. A ADP3158/ADP3178 –13– LAYOUT AND COMPONENT PLACEMENT GUIDELINES The following guidelines are recommended for optimal perfor- mance of a switching regulator in a PC system: General Recommendations 1. For best results, a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. 2. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance intro- duced by these current paths is minimized and the via current rating is not exceeded. 3. If critical signal lines (including the voltage and current sense lines of the controller IC) must cross through power circuitry, it is best if a ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injec- tion into the signals at the cost of making signal ground a bit noisier. 4. The GND pin should connect first to a ceramic bypass capacitor (on the VCC pin) and then into the power ground plane. However, the ground plane should not extend under other signal components, including the controller IC itself. 5. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). 6. Absolutely avoid crossing any signal lines over the switching power path loop, described below. Power Circuitry 7. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise-related operational prob- lems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs, and the power Schottky diode, if used, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high- energy ringing, and it accommodates the high current demand with minimal voltage loss. 8. A power Schottky diode (1 ~ 2 A dc rating) placed from the lower MOSFET ’s source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper MOSFET. In the bñôÖÑ x of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower MOSFET, draws current through the inherent body-drain diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery characteristic of the lower MOSFET’s body-drain diode prevents the drain voltage from being pulled high quickly. The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper MOSFET. The Schottky diode minimizes this problem by carrying a majority of the circu- lating current when the lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 9. Whenever a power-dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately sur- rounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance — espe- cially if the vias extend to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 10. The output power path, though not as critical as the switch- ing power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the out- put capacitors, and back to the input capacitors. 11. For best EMI containment, the ground plane should extend fully under all the power components. These are: the input capacitors, the power MOSFETs and Schottky diode, the inductor, the current sense resistor, any snubbing elements that might be added to dampen ringing, and the output capacitors.

REV. A ADP3158/ADP3178 –14– Signal Circuitry 12. The output voltage is sensed and regulated between the GND pin (which connects to the signal ground plane) and the CS– pin. The output current is sensed (as a voltage) and regulated between the CS – pin and the CS+ pin. In order to avoid differential mode noise pickup in those sensed signals, their loop areas should be small. Thus the CS – trace should be routed atop the signal ground plane, and the CS+ and CS – traces should be routed as a closely coupled pair (CS+ should be over the signal ground plane as well). OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead SOIC (R-16A/SO-16) 16 9 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.3937 (10.00) 0.3859 (9.80) 0.050 (1.27) BSC SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8/H11543 0/H11543 0.0196 (0.50) 0.0099 (0.25)/H11547 45/H11543 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19) 13. The CS+ and CS – traces should be Kelvin-connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. It is desir- able to have the controller IC close to the output capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the GND pin is minimized, and voltage regulation is not compromised.

REV. A –15– Location Page Global change from ADP3158 to ADP3158/ADP3178 Change from REV. 0 to REV. A.

–16– C02189–1.5–7/01(A) PRINTED IN U.S.A.