ADP3120JCPZ-RL

ADP3120 AD | Alldatasheet

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Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3120 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

FEATURES

All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel® VRM 10 specification

APPLICATIONS

Multiphase desktop CPU supplies Single-supply synchronous buck converters GENERAL DESCRIPTION The ADP3120 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a non- isolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 45 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3120 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3120 is specified over the commercial temperature range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead LFCSP packages. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM 3OD IN ADP3120 VCC BST DRVH SW DRVL PGND DELAY VCC DELAY CMP CMP CONTROL LOGIC RBST RG CBST1 CBST2 12V TO INDUCTOR 05591-001 Figure 1.

Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

7/05—Revision 0: Initial Version

Rev. 0 | Page 3 of 16 SPECIFICATIONS1 VCC = 12 V , BST = 4 V to 26 V , TA = 0°C to 85°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit PWM INPUT Input Voltage High 2.0 V Input Voltage Low 0.8 V Input Current −1 +1 μA Hysteresis 90 250 mV OD INPUT Input Voltage High 2.0 V Input Voltage Low 0.8 V Input Current −1 +1 μA Hysteresis 90 250 mV Propagation Delay Times2 OD pdhlt See Figure 4 20 35 ns OD pdhlt See Figure 4 40 55 ns HIGH-SIDE DRIVER Output Resistance, Sourcing Current BST − SW = 12 V 2.2 3.5 Ω Output Resistance, Sinking Current BST – SW = 12 V 1.0 2.5 Ω Output Resistance, Unbiased BST – SW = 0 V 10 kΩ Transition Times trDRVH BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 25 40 ns tfDRVH BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 20 30 ns Propagation Delay Times2 tpdhDRVH BST – SW = 12 V, CLOAD = 3 nF, 25°C ≤ TA ≤ 85°C, see Figure 5 32 45 70 ns tpdlDRVH BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 25 35 ns SW Pull-Down Resistance SW to PGND 10 kΩ LOW-SIDE DRIVER Output Resistance, Sourcing Current 2.0 3.2 Ω Output Resistance, Sinking Current 1.0 2.5 Ω Output Resistance, Unbiased VCC = PGND 10 kΩ Transition Times trDRVL CLOAD = 3 nF, Figure 5 20 35 ns t fDRVL CLOAD = 3 nF, Figure 5 16 30 ns Propagation Delay Times2 tpdhDRVL CLOAD = 3 nF, Figure 5 12 35 ns t pdlDRVL CLOAD = 3 nF, Figure 5 30 45 ns Timeout Delay SW = 5 V 110 190 ns SW = PGND 95 150 ns SUPPLY Supply Voltage Range VCC 4.15 13.2 V Supply Current ISYS BST = 12 V, IN = 0 V 2 5 mA UVLO Voltage VCC rising 1.5 3.0 V Hysteresis 350 mV 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.

Rev. 0 | Page 4 of 16 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VCC –0.3 V to +15 V BST –0.3 V to VCC +15 V BST to SW –0.3 V to +15 V SW DC –5 V to +15 V <200 ns –10 V to +25 V DRVH DC SW – 0.3 V to BST + 0.3 V <200 ns SW – 2 V to BST + 0.3 V DRVL DC –0.3 V to VCC + 0.3 V <200 ns –2 V to VCC + 0.3 V IN, OD –0.3 V to 6.5 V θJA, SOIC 2-Layer Board 123°C/W 4-Layer Board 90°C/W θJA, LFCSP1 4-Layer Board 50°C/W Operating Ambient Temperature Range 0°C to 85°C Junction Temperature Range 0°C to 150°C Storage Temperature Range –65°C to +150°C Lead Temperature Range Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 300°C 215°C 260°C 1 For LFCSP , θJA is measured per JEDEC STD with exposed pad soldered to PCB. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to PGND. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. 8-Lead SOIC Pin Configuration

4 VCC

8 DRVH

6 PGND

5 DRVL

Figure 3. 8-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions bootstrapped voltage for the high-side MOSFET as it is switched. low turns on the low-side driver; pulling it high turns on the high-side driver. 3 OD Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. 4 VCC Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor. 5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET. from turning on until the voltage is below ~1 V. 8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 0 | Page 9 of 16 THEORY OF OPERATION The ADP3120 is optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A more detailed description of the ADP3120 and its features follows. See Figure 1. LOW-SIDE DRIVER The low-side driver is designed to drive a ground-referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver’s output is 180° out of phase with the PWM input. When the ADP3120 is disabled, the low-side gate is held low. HIGH-SIDE DRIVER The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST1. CBST2 and RBST are included to reduce the high- side gate drive voltage and to limit the switch node slew rate (called a Boot-Snap circuit—see the

Application Information

section for more details). When the ADP3120 starts up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of C BST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN, forcing the BST pin to VIN + VC(BST), which is enough gate-to-source voltage to hold Q1 on. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The output of the high-side driver is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. OVERLAP PROTECTION CIRCUIT The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn off to the Q2 turn on, and by internally setting the delay from the Q2 turn off to the Q1 turn on. To prevent the overlap of the gate drives during the Q1 turn off and the Q2 turn on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from V IN to 1 V . Once the voltage on the SW pin falls to 1 V , Q2 begins turn on. If the SW pin has not gone high first, the Q2 turn on is delayed by a fixed 150 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 190 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and is flowing through the high-side MOSFET body diode.

Rev. 0 | Page 10 of 16 SUPPLY CAPACITOR SELECTION For the supply input (VCC) of the ADP3120, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 4.7 μF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3120. BOOTSTRAP CIRCUIT The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined using the following equations: GATE GATE BST2BST1 V QC C × = +10 (1) DCC GATE BST2BST1 BST1 V V V C C C −=+ (2) where: QGATE is the total gate charge of the high-side MOSFET at VGATE. VGATE is the desired gate drive voltage (usually in the range of 5 V to 10 V , 7 V being typical). VD is the voltage drop across D1. Rearranging Equation 1 and Equation 2 to solve for CBST1 yields DCC GATE BST1 V V QC −× =10 CBST2 can then be found by rearranging Equation 1:

110 BST

QC − × = For example, an NTD60N02 has a total gate charge of about 12 nC at VGATE = 7 V . Using VCC = 12 V and VD = 1 V , one finds CBST1 = 12 nF and CBST2 = 6.8 nF . Good quality ceramic capacitors should be used. RBST is used to limit slew rate and to minimize the ringing at the switch node. It also provides peak current limiting through D1. An R BST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor needs to handle at least 250 mW due to the peak currents that flow through it. A small-signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by MAXGATEAVG F f Q I×=) ( (3) where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be calculated using BST DCC PEAK F R V VI −=) ( (4) MOSFET SELECTION When interfacing the ADP3120 to external MOSFETs, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short-time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use the boot-snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node. HIGH-SIDE (CONTROL) MOSFETS A high-side, high speed MOSFET is usually selected to minimize switching losses (see the ADP3186 or ADP3188 data sheet for Flex-Mode1 controller details). This typically implies a low gate resistance and low input capacitance/charge device. Y et, a significant source lead inductance can also exist. This depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information. The ADP3120 DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the internal capacitance of the gate. This determines the speed at which the MOSFETs turn on and off. However, because of potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side MOSFETs switch off. This creates a significant drain-source voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition can be referenced in literature from the MOSFET suppliers. 1 Flex-Mode™ is protected by U.S. Patent 6683441.

1. FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3188 THEORY OF OPERATION SECTION.

Figure 16. VRD 10.x-Compliant Power Supply Circuit

Figure 17. 8-Lead Standard Small Outline Package [SOIC_N]

0.60 MAX PIN 1

0.65 TYPSEATING

0.90 MAX

0.85 NOM

0.05 MAX

0.01 NOM

0.20 REF

Figure 18. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

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Rev. 0 | Page 16 of 16 NOTES © 2005 Analog Devices, Inc. All ri ghts reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D05591–0–7/05(0)