ADP3088

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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. a ADP3088

1 MHz, 750 mA Buck Regulator

FEATURES

1 MHz PWM Frequency

Automatic PWM to Power Saving Mode at Light Load Fully Integrated 1 A Power Switch 3% Output Regulation Accuracy over Temperature, Line, and Load 100% Duty Cycle Operation Simple Compensation Output Voltage: 1.25 V to 10.5 V Small Inductor and MLC Capacitors Low Quiescent Current while Pulse Skipping Thermal Shutdown Fully Integrated Soft Start Cycle-by-Cycle Current Limit

APPLICATIONS

PDAs and Palmtop Computers Notebook Computers PCMCIA Cards Bus Products Portable Instruments FUNCTIONAL BLOCK DIAGRAM SW FB COMP GND IN DRV CURRENT SENSE AMP PWM COMPARATOR REF 1.245V ERROR AMP gm SOFT START TIMER+ R S Q RUN/STOP COMPARATORS 1MHz PROTECTION LOGIC (ILIM, OT) IN GND ADP3088 GENERAL DESCRIPTION The ADP3088 is a high frequency, nonsynchronous PWM step- down dc-to-dc regulator with an integrated 1 A power switch in a space-saving MSOP-8 package. It provides high efficiency and excellent dynamic response and is very simple to use. The ADP3088’ s 1 MHz switching frequency allows for small, inexpensive external components, and the current mode control loop is simple to compensate and eases noise filtering. The device operates in PWM current mode under heavy loads and saves energy at lighter loads by switching automatically into power saving mode. Soft start is integrated completely on-chip, as is the cycle-by- cycle current limit. Capable of operating from 2.5 V to 11 V input, the ADP3088 is ideal for many applications, including portable, battery-powered applications where local point-of-use power regulation is required. Supporting output voltages down to 1.25 V, the ADP3088 is ideal for generating low voltage rails, providing the optimal solution in its class for delivering power efficiently, responsively, and simply with a minimal printed circuit board area. The device is specified over the industrial temperature range of –40∞C to +85∞C. SW DRV FB IN GND COMP ADP3088 VOUT 1.8V 3.3/H9262H 10.0k/H9024 22.4k/H9024 20k/H9024 4.7pF 1N5817 IN GND 10/H9262F 0.1/H9262F 220pF VIN 3.3V 10/H9262F Figure 1. Typical Application

REV. C–2– ADP3088–SPECIFICATIONS1 Parameter Symbol Conditions Min Typ Max Unit SUPPLY Input Voltage Range VIN DRV = GND 2.5 11 V Ground Current, Operating I GND

2 VIN = 10 V, IL = 500 mA,

DRV = GND 6 mA DRV = 2 V 2.5 3.6 mA Quiescent Current, Operating I Q No Load 150 250 mA Shutdown ISD VCOMP = 0 V 15 40 mA Thermal Shutdown Threshold T SD 160 ∞C OSCILLATOR Oscillator Frequency f SW 0.75 1 1.25 MHz Minimum Sleep Duty Cycle D PSM IL = 500 mA 14 % Maximum Duty Cycle D MAX 100 % Wake-Up Hysteresis VHYST FB Voltage Drops below V REF 20 30 40 mV OUTPUT SWITCH Switch-On Voltage V IO 3 IL = 500 mA, FB = GND, and 0.25 0.4 V DRV = GND Current Limit Threshold I LIM 1.0 1.2 1.4 A Leakage Current VIN = 12 V 0.5 mA ERROR AMPLIFIER Reference Voltage Accuracy V REF FB = COMP 1.222 1.245 1.265 V Reference Voltage Line FB = COMP, 0.02 %/V Regulation VIN = 3 V to 12 V Feedback Input Bias Current I FB Soft Start Expired –50 +1 +50 nA Sink/Source Current ICOMP 35 60 85 mA Short Circuit Current I COMP, SD VCOMP = 0 V, Activating 20 40 mA Shutdown Transconductance gm, EA FB = COMP 480 mA/V MODULATOR Transconductance gm, MOD VCOMP to IL 1 A/V Control Offset Voltage V PWM, OS 0.90 V Soft Start Time tSS 250 600 ms Shutdown Threshold Voltage V COMP, SD 340 750 mV Slope Compensation mSC Effectively Summed to I SW 0.7 A/ms NOTES 1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2For higher efficiency operation, tie the DRV pin to the output for I L < 250 mA and V IN > 3 V. 3VIN – VSW includes voltage drop across internal current sensor. Specifications subject to change without notice. (VIN = 3.3 V, TA = –40 /H11543C to +85/H11543C, unless otherwise noted.) OBSOLETE

REV. C –3– ADP3088 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3088 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION TOP VIEW (Not to Scale) IN IN GND COMP SW DRV GND FB ADP3088 ABSOLUTE MAXIMUM RATINGS * Voltage on Any Pin with Respect to GND . . . –0.3 V to +12 V (Voltage on Any Pin May Not Exceed V IN) Operating Ambient Temperature Range . . . . –40∞C to +85∞C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1, 2 IN Power Supply Input. Both pins must be connected. 3, 6 GND Ground. Both pins must be connected.

4 COMP Feedback Loop Compensation and

Shutdown Input. An open drain or collector used to pull the pin to ground will shut down the device. 5F B Feedback Voltage Sense Input. This pin senses the voltage via an external resistor divider.

7 DRV This pin provides a separate path for

the drive current to be connected to ground. 8S WS witching Output. ORDERING GUIDE Temperature Package Model Range Option Branding ADP3088ARM-REEL –40∞C to +85∞CM S O P-8 P0A ADP3088ARM-REEL7 –40∞C to +85∞CM S O P-8 P0A OBSOLETE

REV. C–4– ADP3088–Typical Performance Characteristics 0 500100 200 400 300 LOAD CURRENT (mA) EFFICIENCY (%) 100 VOUT = 3.3V VOUT = 1.5V VOUT = 2.5V VIN = 5V, CIN = COUT = 10/H9262F, L = 10/H9262H TA = 25/H11543C TPC 1. Efficiency vs. Load Current and Output Voltage 0 0 500100 200 400 300 LOAD CURRENT (mA) EFFICIENCY (%) 100 VOUT = 5V VOUT = 3.3V VOUT = 2.5V VOUT = 1.5V VIN = 10V, CIN = COUT = 10/H9262F, L = 10/H9262H TA = 25/H11543C TPC 2. Efficiency vs. Load Current and Output Voltage 01 0 24 8 6 INPUT VOLTAGE (V) QUIESCENT CURRENT (mA) 100 VOUT = 1.5V, CIN = COUT = 10/H9262F, DRV = GND IL = 500mA IL = 0mA TA = 25/H11543C TPC 3. Quiescent Current vs. Input Voltage 100.00 –40 85 –15 10 60 35 TEMPERATURE (/H11543C) 120.00 140.00 160.00 180.00STANDBY QUIESCENT CURRENT (/H9262A) 200.00 TPC 4. Standby Quiescent Current vs. Temperature 1.00 –40 85 –15 10 6035 TEMPERATURE (/H11543C) 2.00 3.00 4.00 GROUND CURRENT (mA) 5.00 ILOAD = 500mA VDRV = 2V TPC 5. Ground Current vs. Temperature 1.2418 –40 85 –15 10 60 35 TEMPERATURE (/H11543C) 1.2423 1.2428 1.2433FEEDBACK VOLTAGE (V) 1.2438 TPC 6. Feedback Voltage vs. Temperature OBSOLETE

REV. C –5– ADP3088 1.485 0 500100 200 400 300 OUTPUT CURRENT (mA) 1.495 1.505 OUTPUT VOLTAGE (V) 1.515 VIN = 5V, CIN = COUT = 10/H9262F, L = 10/H9262H TA = 25/H11543C TPC 7. Load Regulation 0.90 –40 85 –15 10 6035 TEMPERATURE (/H11543C) 0.95 1.00 1.05 FREQUENCY (MHz) 1.10 TPC 8. Oscillator Frequency vs. Temperature 1.00 –40 85 –15 10 6035 TEMPERATURE (/H11543C) 1.05 1.10 1.15 CURRENT LIMIT (A) 1.20 TPC 9. Current Limit vs. Temperature 12.00 –40 85 –15 10 60 35 TEMPERATURE (/H11543C) 14.00 16.00 18.00 SHUTDOWN SUPPLY CURRENT (/H9262A) 20.00 10.00 TPC 10. Shutdown Supply Current vs. Temperature 0.220 –40 85 –15 10 60 35 TEMPERATURE (/H11543C) 0.240 0.260 0.280 SWITCH VOLTAGE (V) 0.300 0.200 ILOAD = 500mA TPC 11. Switch-Sense Resistor Voltage vs. Temperature 0.400 OUTPUT CURRENT (A) 0.500 0.600 0.900 SWITCH SATURATION VOLTAGE (V) 1.000 0.300 0.700 0.800 0.100 0.200 VIN = 2.5V VIN = 5V VIN = 12V VIN = 3.3V TA = 25/H11543C TPC 12. Switch Saturation Voltage vs. Load Current and Input Voltage OBSOLETE

REV. C–6– ADP3088 VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 0mA, CIN = COUT = 10/H9262F, L = 10/H9262H TA= 25/H11543C CH 1: INPUT VOLTAGE, 2V/DIV CH 2: OUTPUT VOLTAGE, 500mV/DIV TPC 13. Start-Up Waveform VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 500mA, CIN = COUT = 10/H9262F, L = 10/H9262H TA = 25/H11543C CH 1: INPUT VOLTAGE, 2V/DIV CH 2: OUTPUT VOLTAGE, 500mV/DIV TPC 14. Start-Up Waveform CH 1: INPUT VOLTAGE, 2V/DIV CH 2: OUTPUT VOLTAGE, 500mV/DIV VIN = 2.5V, VOUT = 1.25V, LOAD CURRENT = 250mA, CIN = COUT = 10/H9262F, L = 10/H9262H, TA = 25/H11543C TPC 15. Start-Up Waveform VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 500mA, CIN = COUT = 10/H9262F, L = 10/H9262H TA = 25/H11543C CH 1: INPUT VOLTAGE, 10mv/DIV, AC-COUPLED TPC 16. V OUT Ripple TA = 25/H11543C VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 10mA, CIN = COUT = 10/H9262F, L = 10/H9262H TPC 17. Power-Saving Mode Waveforms* CIN = COUT = 10/H9262F, L = 10/H9262H VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 25mA,TA = 25/H11543C TPC 18. Steady-State Waveforms* *NOTES FOR TPCs 17 AND 18 CH 1: Output Voltage, 20mV/DIV, AC-Coupled CH 2: Switch Node Voltage, 2V/DIV CH 3: Inductor Current, 100mA/DIV OBSOLETE

REV. C –7– ADP3088 VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 100mA, TA = 25/H11543C, CIN = COUT = 10/H9262F, L = 10/H9262H TPC 19. Steady-State Waveforms* TA = 25/H11543C, CIN = 10/H9262F, COUT = 20/H9262F, L = 10/H9262H VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 50mA TO 550mA, CH 1: LOAD CURRENT STEP, 167mA/DIV CH 2: OUTPUT VOLTAGE, 100mV/DIV TPC 20. Load Transient Response VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 550mA TO 50mA, CIN = COUT = 10/H9262F, L = 10/H9262H TA = 25/H11543C CH 1: LOAD CURRENT STEP, 167mA/DIV CH 2: OUTPUT VOLTAGE, 100mV/DIV TPC 21. Load Transient Response *NOTES FOR TPC 19 CH 1: Output Voltage, 20mV/DIV, AC-Coupled CH 2: Switch Node Voltage, 2V/DIV CH 3: Inductor Current, 100mA/DIV VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 50mA TO 550mA TO 50mA, TA = 25/H11543C, CIN = 10/H9262F, COUT = 20/H9262F, L = 10/H9262H CH 1: LOAD CURRENT STEP, 167mA/DIV CH 2: OUTPUT VOLTAGE, 100mV/DIV TPC 22. Load Transient Response VIN = 3V TO 5V, VOUT = 1.5V, LOAD CURRENT = 500mA, TA = 25/H11543C, CIN = 10/H9262F, COUT = 10/H9262F, L = 10/H9262H CH 1: INPUT VOLTAGE, 2V/DIV CH 2: OUTPUT VOLTAGE, 20mV/DIV TPC 23. Line Transient Response OBSOLETE

REV. C–8– ADP3088 THEORY OF OPERATION The ADP3088 is a fixed frequency buck switching regulator in an MSOP-8 package using an external Schottky rectifier. It features an integrated 1 A power switch and switches at 1 MHz. The ADP3088 uses PWM operation and incorporates soft start for controlled start-up sequence and overtemperature switch protection. The ADP3088 draws low current while running in power saving mode and even lower current in shutdown. The system shown in the Functional Block Diagram is config- ured for a 1.8 V output using a 10 mH inductor. At the beginning of a cycle, the 1 MHz oscillator enables an SR latch, enabling the internal 1 A power switch. The current sense amplifier and the protection logic block m onitor the current flowing between the IN and SW pins. The switch is turned off when the current reaches a level determined by the protection logic block or PWM comparator, whichever is lower. The error amplifier measures the output voltage through an external resistor divider tied to the FB pin. This amplifier servos the switch current to regulate the FB pin voltage to 1.245 V. An internal regulator provides power to the control circuitry. The COMP pin can be used to shut down the ADP3088. When pulled low, it turns off the internal regulator, thus biasing down the chip, reducing the input current, and disconnecting the output from the input. Antisaturation circuitry is used to drive the switch to the edge of saturation. This allows the driver to quickly switch at 1 MHz and maintain good efficiency. For improved efficiency, the DRV pin may be connected to the output provided that the input voltage is at least 1 V greater than the output. If the output load increases, the error amplifier will detect a lower voltage on the FB pin via the resistor divider on the output and send a signal to the PWM comparator to increase the on time of the switch. This in effect increases the duty cycle and provides more current to drive the increased load during the transient event until a new operating point is established. Reference The ADP3088 incorporates an internal band gap reference, including curvature correction for an extremely low temperature coefficient. The reference can be disabled by grounding the COMP pin, which also turns off the bias for the rest of the chip. Error Amplifier The error amplifier provides a control voltage to the PWM stage to set the peak inductor current that sets the output current of the regulator. It is a g m amplifier in that its output is a current to the COMP pin. Protection Logic The protection logic block provides current limit and overtemperature protection. The overtemperature protection is enabled when the temperature of the chip exceeds a specified preset temperature; the switch will be disabled until the tempera- ture drops below a specified level, then normal operation will resume. The thermal shutdown only stops switching, but it does not put the chip into power saving mode, nor does it reinitiate soft start. As the chip cools slightly, it will rapidly cycle in and out of thermal shutdown, maintaining the die temperature at 160∞C but allowing the output voltage and current to swing up and down. The current limit protection overrides the PWM comparator; if this occurs, then the switch pulse will be terminated and the soft start mode will be reset. Current Sense Amplifier The voltage on the internal current sense resistor is sensed and passed to the ramp input of the PWM comparator. This current sense signal is also passed to the current limit comparator for peak current limit shutdown. At the current limit, the soft start capacitor is reset and soft start is reinitiated. The current limit is nominally 1.2 A. Slope compensation is added to the ADP3088 to stabilize the loop. A generated ramped signal is summed with the current sense signal to provide slope compensation. Slope compensation is needed to close the inner loop so subharmonic oscillation is avoided. The ramp is reset with each clock cycle so that the ADP3088 is capable of true 100% duty cycle. Run/Stop Comparators This block creates the 1 MHz signal sent to the SR latch that is used for the switching frequency. It also takes the FB voltage and decides when to go into wake-up mode from power saving mode. The decision to induce the power saving mode is based on the duty ratio. During steady-state continuous operation, the duty ratio of a PWM buck regulator is simply a function of the input/output voltage ratio, with second-order effects including the voltage drop of the internal switch and the external diode. Once the load drops to a certain point, discontinuous operation occurs, and the duty ratio begins to modulate to maintain regulation. In the ADP3088, the regulator goes to sleep when the integrated duty ratio measurements drop to less than half of the minimum expected integrated duty ratio. The minimum expected duty ratio occurs at the maximum input voltage and the minimum output voltage in continuous mode operation. PWM Comparator The PWM comparator looks at the signal from the current sense amplifier and the error amplifier to determine the correct switch-on time to regulate the output voltage under a given load. Soft Start Timer The soft start will prevent saturating the inductor, which could cause uncontrolled overshoot of the output voltage and electrical stress to the system at startup. When first powered up, an internal soft start capacitor is discharged and the soft start circuitry provides a gradually decaying offset to the error amplifier to prevent it from saturating and from commanding the maximum switch current to charge the output capacitor. The output voltage approaches the final regulation voltage with a smooth exponential decay. This will reduce electrical stress to the system. Output The output stage contains the bipolar power switch and the circuits necessary to switch it on and off quickly. The pass switch is driven to the edge of saturation, and the result is a fast switching response and low switch resistance. For improved efficiency, the DRV pin may be connected to the output, provided that the input voltage is at least 1 V higher than the output. This will send the current needed to drive the bipolar switch to the output load instead of routing it to ground. For some V IN and ILOAD configurations, the DRV pin must be grounded for reliable operation. OBSOLETE

REV. C –9– ADP3088

APPLICATION INFORMATION

In its standard usage, the output voltage of the ADP3088 is programmed to a desired fixed value by a resistor divider from the output voltage into the feedback node, the FB pin, at which node the control loop ensures regulation at the reference level, V REF. The divider should be designed to satisfy the formula VV R ROUT REF A B =¥ + Ê ËÁ ˆ ¯˜1 (1) where RA is the upper divider resistor (between the output and FB) and RB is the lower one (between FB and ground). RA and RB are recommended to have values in the range of 2 kW~200 kW and are likely to require a 1% tolerance or better to attain acceptable output voltage tolerance. In less conventional applications described separately, the resistor feedback configuration can be modified or tapped with other resistors to affect current flow into the FB node that, in turn, influences the output voltage. Even a switched voltage can be summed into the FB node as long as it is sufficiently integrated and does not intolerably compromise the transient response. This latter application is considered further below, for an application for powering a DSP. Input Voltage, Power Dissipation Considerations, and Power Savings Mode The input voltage range is not typically considered a critical parameter for electrical functionality, but there are several considerations, upon which there is further elaboration below: 1. VIN must never exceed the maximum rated voltage. 2. VIN must be within the specified operating range when normal operation is expected. 3. VIN must be greater than VOUT by at least the specified head- room when dc regulation is expected. 4. VIN, if not sufficiently greater than VOUT, may limit the large signal transient response of a buck converter. 5. VIN, if much greater than VOUT, may give rise to such a low duty ratio that it activates power savings mode even at static higher load conditions or upon dynamic load changes when it is not desired. 6. VIN affects the device power dissipation (a lower value causes higher dissipation), which in turn affects die temperature that must be kept below a maximum rating. The lowest input voltage together with the maximum output voltage and maximum current create the conditions for the maximum power dissipation in the device, which determine the maximum temperature rise that should be checked against the maximum junction temperature rating. The formula for maximum power dissipation in the device is given by P VV V IVDMAX OF I O MAX IN OM A X SW IO MAX= ,@ , (2) where VF is the diode forward voltage drop and VSW is the drop across the internal switch and current sensing resistor that appears between the VIN and SW pins of the ADP3088 during the on state of the switch. Both of these variables can be approximated from a combination of worst-case specifications and typical graphs. Multiply the power dissipation by the thermal resistance from junction to case or ambient, as desired, to determine the internal temperature rise. If the input voltage were so much higher than the output voltage that it required an average duty ratio less than an internally preset threshold, then power savings mode (PSM) —which is characterized by periodic shutdown and wake-up of the device that reduces average quiescent current —would be active for all load conditions rather than only at lighter loads, for which it is intended. PSM operation is characterized by low frequency ripple on the output that appears similar to the behavior of a hysteretic regulator. This is usually not a factor for consider- ation and may be ignored if PSM operation is acceptable for all load conditions. But in case it is relevant, the following recom- mendation is offered: VIN OF PSM MAX VV (3) It is not possible to prevent the duty ratio from tending toward zero in nonsynchronous buck converters below a certain minimum load current level called “borderline current” or “critical current” for the power converter. That corresponds to the in ductor ripple current reaching zero at its bottom peak, sometimes called the “valley current.” If PSM activation strains the lower regulation limit due to the hysteretic ripple, the output voltage can be offset slightly upward by readjusting the nominal voltage setpoint with the resistor divider. Even though a buck converter may have a low dropout voltage that allows the static regulation to be maintained as the input voltage drops near the output voltage, in buck converters, the slew rate limitation of the inductor current can compromise the dynamic regulation in response to the load current step increases. That is because the maximum rate the current can be increased to in the inductor is proportional to the voltage available to impress across it, which is compromised as the input voltage reduces toward the output voltage. This is not a limitation of the device but of buck converters in general. The limitation is considered part of the output filter design, although it could also be considered in terms of a minimum acceptable input voltage for a given output filter that will ensure that the dynamic response is acceptably maintained. Output Filter Components In most applications, it is desirable to use the smallest inductor value that does not introduce practical problems, since this tends to yield the lowest cost inductor. One reason for using an even larger inductor than the minimum tolerable might be to reduce the output ripple voltage further. But cost being equal, this is generally better accomplished with a better quality or propor- tionally larger output capacitor instead, since a larger inductor degrades the large signal transient performance capability. A conservative nominal design target value for the inductor of a typical application circuit is that which creates a peak-to-peak ripple current, DI L, for the nominal input voltage that is approxi- mately a third of the nominal 500 mA rating of the ADP3088. The reason for not basing the ripple current on the maximum load current is concern about the protection. Scaling the ripple currents with lower load currents would yield higher inductor values that might give satisfactory operation. However, in order for overload operation up to the current limit level of the ADP3088 to be satisfactory, it would be necessary to choose an inductor OBSOLETE

REV. C–10– ADP3088 rated up to that higher current, which would likely yield an unsatisfactory inductor size and cost. In any case, having chosen a target level for DIL, the recommended inductor value is given by L DVV fI OF SW L -¥ + () ( )1 D (4) where D is the duty ratio, the suffix indicating continuous inductor current, and is given by D VV VV V OF IN F SW +- (5) VSW and VF are assessed at full load, and fSW is the fixed switching frequency of the ADP3088. The formula suggests the calculation of L using a nominal input voltage; for applications requiring a large range of VIN, the limitations of transient response at VIN(MIN) versus the higher ripple at VIN(MAX) may warrant deeper consideration of how to optimize the design. In applications where load transients are not severe, this conservative design for L is recommended. A more aggressive minimization of L is outlined below, but a few restrictions are noted. As inductance becomes smaller, the ripple current becomes larger. If the ripple becomes particularly large or, as an addi- tional factor, if the load is particularly dynamic, then there is an increasing possibility that the peak inductor current will reach the current limit shutdown threshold, I CL, which is not desirable. This should be avoided by restricting the minimum inductor value to keep the ripple current moderated. An alternative way to prevent excessive dynamic overshoot of the inductor current during a load transient is to reduce the dc gain of the error amplifier by adding resistive feedback; this idea is discussed below. Another important restriction of the minimum inductor value may apply. The design should ensure against possible subharmonic oscillation that can occur in all fixed frequency, current-controlled switching power supplies when switching at high duty ratios. The subharmonic oscillation phenomenon will not be explained here (there are many papers written on the subject) except to say that it is characterized by alternating high and low duty ratios, i.e., every other cycle, which produces additional ripple on the output. To prevent subharmonic oscillation, the follow- ing restriction for the minimum inductor value is recommended: L H V VV VV VOF OF IN MIN >¥ + () ¥ +2 03 5m – . (6) The value used for VIN(MIN) should be only the minimum input voltage for which normal high performance operation must be ensured. Note that the value returned for L may be negative, in which case the restriction does not apply. If the preceding formula yields a lower inductor value than the conservative recommen- dation given previously, as is likely for most applications, then one should consider further limitations to see how low the value can be minimized. For a given inductor selection, the earlier formula is rearranged for convenience and skewed to the worst-case input voltage to determine the maximum inductor ripple current, DI DI VV V VV V VV fLLM A X IN MAX O SW IN MAX F SW OF SW + ¥ ¥ (7) Performance degradation of the inductor, consisting of some loss of inductance or excessive power loss, may be encountered at higher ripple currents, so the ripple current figure, together with the knowledge of the expected dc current, should be checked against the specifications of the inductor. If the ESR of the output capacitor is substantial, as it is likely to be if an MLC capacitor is not used, then the ripple voltage on the output, dominated by the ESR, may be substantial and of concern for regulation specifications. The resistive component of the output voltage ripple is simply the ripple current multi- plied by the ESR, and if it is more than a few millivolts, it will dominate the output capacitance in contributing to the output ripple voltage. The boundary condition of the inductor reaching the borderline current, I O(BL), can be determined by the formula I VV fL VV V VV VOB L OF SW IN O SW IN F SW () = +-2 (8) Below this output current level, the inductor current will be discontinuous, and the duty ratio will be modulated to lower values by factors substantially more than the losses that cause only a small amount of the modulation in the continuous inductor current operation. PSM is initiated automatically by a propri- etary technique consisting of a duty ratio amplifier with an internal time constant. As the load current drops well into the low current region and the duty ratio passes below the threshold of D PSM for a sufficient time, PSM is activated. The correspond- ing level of output current is given by ID VV V VV VV V f O(PSM) PSM IN F SW OF IN O SW SW =¥ +- + ¥ -- L (9) It can be seen in the formula that this current threshold is inversely proportional to inductance, so although it is usually not a relevant concern, it is noted that an aggressively low output inductance should be avoided to keep the PSM threshold current at a desir- ably low level. For the user’ s reference, when current is below the borderline level, the duty ratio is modulated according to the formula DI VV VV V fL VV VDO OF IN F SW SW IN O SW =¥ ¥ +- ¥ --2 (10) where the suffix indicates that the inductor current is discontinuous. For controlling the capacitive component of the output ripple voltage, the following constraint on the minimum output capacitance should be applied: C I fVO L SW R D D8 (11) OBSOLETE

REV. C –11– ADP3088 where /H9004VR is the tolerable ripple voltage. However, this constraint is rarely relevant, since the typical capacitance requirement is driven more by dynamic response requirements than by ripple concerns. In a typical application circuit, a 10 mF capacitor produces a capacitive output voltage ripple component of only about 2 mV. 10 mF is usually sufficient for applications that do not impose particularly high frequency load transients, and imposes additional constraints that are elaborated upon in the next section. Load Characterization Optimization of the compensation, as well as the output filter, requires some knowledge of a fundamental characteristic of the load. Qualitatively, there are two types of loads with which we are concerned: fast slew rate and slow slew rate. These slew rates are assessed with respect to the minimum (absolute) inductor (current) slew rate, as given by dI dt MIN VV V L and VV L L IN MIN SW O MAX OF MAX Ê ËÁ ˆ È Î Í Í =< -- +Ï Ì Ó () (12) where the < sign indicates a selection of whichever bracket term is lower. If the slew rate of the load is fast compared to the minimum inductor slew rate, then the ability of the power converter to contain the output voltage deviation following a load change is limited not only by the response of the control loop, i.e., by its speed to demand zero or maximum duty ratio from the modulator, but by the power stage as well. In such a case, beginning with the recognition that output voltage deviation would be substantial even if the loop response were instantaneous, it can be shown that one can achieve better overall voltage containment by degenerating the dc loop gain. As a technical matter, it should be noted that there will always be some minimum output voltage deviation downward due to a load step even if the inductor slew is as fast as the load slew rate. During a switching cycle, the modula- tor latches its “ decision” to turn off the switch. It cannot rescind that decision, but must instead wait for the next clock cycle to turn on the switch again and begin slewing the inductor current upward. This is only a second-order consideration. Slow slew rate loads may be referred to simply as conventional loads, since these have been the more prevalent type of load. Optimally compensating a conventional load is synonymous with small signal ac considerations; the objective is to maximize the ac gain up to the crossover frequency, ensure sufficient phase margin at the unity gain crossover frequency, and keep the gain rolling off at higher frequencies to avoid gain margin problems. Fast slew rate loads may be referred to as digital loads since, from the perspective of the power converter, they have a digital characteristic when changing between two extremes, and also because such fast slew rates tend to characterize modern digital circuits, which often feature power management interrupts, i.e., interrupt signals used to turn circuitry on and off as needed during normal system operation. Optimally compensating a digital load is more a task of impedance matching and dc gain determina- tion than a task of ac loop optimization. Returning to constraints for choosing the output capacitor for digital loads, another criterion for ensuring sufficient output capacitance applies. C I V dI dt MIN O O O L > È Î Í Í D D 2 (13) where DIO is the maximum high frequency load step. It should be noted that the formula results strictly from the physical limitation of the output filter; the compensation must also be optimized to maximize the response of the control loop to avoid substantial additional output voltage deviation. The formula might also be written to describe a maximum inductance for a given capacitance, but it is generally better practice to choose the inductor first and add capacitance as needed. The impedance of the output capacitor together with a digital load also creates some limiting considerations. Series resistance (ESR) rather than capacitance can be a dominant design consideration with non-MLC capacitors. If the load is essentially digital, then the dynamic deviation of the output voltage cannot be limited to any better than the dynamic load current step times the ESR. In a formula, DDVI ESROO≥ ¥ (14) In such a case, it is often important to choose a capacitor that controls the ESR to a sufficiently small value. MLC capacitors are often chosen to practically eliminate the consideration of ESR entirely. Closing the Loop—Compensation The factors determining the response of the power converter include the feedback input resistor divider, a lead network if applicable, the transconductance of the error amplifier, its frequency response limitation (i.e., as adequately modeled by a capacitance from output to ground), its external termination impedance (i.e., the compensation that may or may not include dc feedback), the modulator transconductance, and the power converter’s termination impedance (i.e., the output capacitor and load resistance). Since the ADP3088 has a current-controlled loop, the particular inductor value does not by first-order consideration affect small signal stability. However, slew rate limitations, as discussed earlier, a large signal limitation consideration, set boundaries that are often relevant for optimizing compensation of the feed- back loop. If the compensation of the current control signal, i.e., the COMP pin, is designed to promote a current response that is faster than the inductor current can slew, then when a step load is applied, the control signal will tend to initially respond in excess (of the actual current change that is occurring) and then allow an overshoot of the current and output voltage since it is delayed in correcting its excess. For conventional loads, the following describes how the fre- quency corners (poles and zeros) are positioned or should be chosen to optimize the loop gain, beginning in the low frequency spectrum: OBSOLETE

ADP3088) is reduced to a negligible second-order effect. Figure 3. +5 V to –3.3 V, General-Purpose of the nominal output voltage. lent to saying that the load regulation appears to be poor. lar importance in many highly dynamic loads.

2.5 V output at 100 mA~400 mA, which constrains the output

that is sepa rately accounted with voltage positioning designs. Figure 4. Application Circuit Using Voltage Posi-

2.5 V system voltage to the FB node that will reduce the out-

lation loop and appears as an integration pole to the PWM signal. Figure 5. Blackfin DSP Application

REV. C –15– ADP3088 OUTLINE DIMENSIONS 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 0.80 0.60 0.40 8/H11543 0/H11543 4.90 BSC PIN 1

0.65 BSC

3.00 BSC SEATING PLANE 0.15 0.00 0.38 0.22

1.10 MAX

3.00 BSC COPLANARITY 0.10 0.23 0.08 COMPLIANT TO JEDEC STANDARDS MO-187AA OBSOLETE

REV. C C02832–0–1/04(C) –16– ADP3088

Revision History

1/04—Data Sheet changed from REV. B to REV. C. 4/03—Data Sheet changed from REV. A to REV. B. 10/02—Data Sheet changed from REV. 0 to REV. A. OBSOLETE