ADP2127

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Ultralow Profile, 500 mA, 6 MHz, Synchronous, Step-Down, DC-to-DC Converters ADP2126/ADP2127 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

FEATURES

1.20 V and 1.26 V fixed output voltage options Clock signal enable Logic signal enable also available on certain models

6 MHz operating frequency

Spread spectrum frequency modulation to reduce EMI 500 mA continuous output current Input voltage: 2.1 V to 5.5 V 0.3 μA (typical) shutdown supply current Pin-selectable power-saving mode Compatible with tiny multilayer inductors Internal synchronous rectifier Internal compensation Internal soft start Output-to-ground short-circuit protection Current-limit protection Undervoltage lockout Thermal shutdown protection 0.330 mm height (maximum), 6-ball BUMPED_CHIP (ADP2126) 0.200 mm height (maximum), 6-pad EWLP (ADP2127)

APPLICATIONS

Digital still/video cameras Digital audio Portable equipment Camera modules Image stabilization systems TYPICAL APPLICATION CIRCUITS B2 A1 VIN GND FB SW EXTCLK MODE CIN 2.2µF COUT 2.2µF INPUT VOLTAGE 2.1V TO 5.5V L 1.0µHADP2126 OUTPUT VOLTAGE 1.20V OR 1.26V OFF ON OFF ON AUTO PWM OR 09658-001*LOGIC HIGH ENABLE IS ONLY AVAILABLE ON CERTAIN MODELS. Figure 1. ADP2126 0.33 mm Maximum Height Solution 09658-002*LOGIC HIGH ENABLE IS ONLY AVAILABLE ON CERTAIN MODELS. Figure 2. ADP2127 0.22 mm Maximum Height Solution improves efficiency and results in fewer external components. a constant frequency with excellent stability and transient response. Light load operation is determined by the state of the MODE pin. life in portable applications.

5.5 V , allowing the use of single Li+/Li polymer cell, three-cell

and external circuit components.

Rev. A | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

5/11—Rev. 0 to Rev. A 5/11—Revision 0: Initial Version

Rev. A | Page 3 of 20 SPECIFICATIONS VIN = 3.6 V , TA = 25°C for typical specifications, and TA = TJ = −40°C to +85°C for minimum and maximum specifications, unless otherwise noted. All specifications at temperature extremes are guaranteed via correlation using the standard statistical quality control (SQC) methods. Typical specifications are not guaranteed. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY Operating Input Voltage Range VIN 2.1 5.5 V PWM Mode Quiescent Current No load, VMODE = VIN 12 mA Auto Mode Quiescent Current No load, VMODE = 0 V, VFB > VOUT, SW = open 300 500 μA Shutdown Current1 VEXTCLK = 0 V, open loop 0.3 1.5 μA UNDERVOLTAGE LOCKOUT Rising VIN Threshold 1.9 2.1 V Falling VIN Threshold 1.5 1.8 V OUTPUT Continuous Output Current2 I LOAD V IN = 2.1 V to 5.5 V 500 mA PWM Mode Output Accuracy3 VOUT V IN = 2.1 V to 5.5 V, no load VOUT − 2% VOUT + 2% V PFM Mode Output Accuracy3, 4 VIN = 2.1 V to 5.5 V VOUT − 3% VOUT + 3% V FB Bias Current VFB = VOUT 4 9 μA FB Pull-Down Resistance RDSCHG V EXTCLK = 0 V, IFB = 10 mA 110 180 Ω SWITCHING CHARACTERISTICS PMOS On Resistance ISW = 500 mA 180 340 mΩ NMOS On Resistance ISW = 500 mA 250 mΩ SW Leakage Current VSW = 0 V, VIN = 5.5 V 10 μA PMOS Switch Current Limit Open loop 770 1000 1291 mA PFM Current Limit VMODE = 0 V, VIN = 3.6 V 170 260 305 mA Oscillator Frequency fSW 4.8 6 6.8 MHz SHORT-CIRCUIT PROTECTION Rising VOUT Threshold 0.55 0.7 V Falling VOUT Threshold 0.4 0.52 V EXTCLK INPUT High Threshold Voltage VEXTCLK(H) V IN = 2.1 V to 5.5 V 1.3 V Low Threshold Voltage VEXTCLK(L) V IN = 2. 1 V to 5.5 V 0.4 V Leakage Current VIN = 5.5 V, VEXTCLK = 2.1 V to 5.5 V 0.01 1 μA Duty Cycle Operating Range DEXTCLK 40 60 % Frequency Operating Range fEXTCLK 6 27 MHz MODE INPUT LOGIC High Threshold Voltage VMODE(H) V IN = 2.1 V to 5.5 V 1.3 V Low Threshold Voltage VMODE(L) V IN = 2.1 V to 5.5 V 0.4 V Leakage Current VEXTCLK = 0 V, VIN = VMODE = 5.5 V 0.005 1 μA THERMAL SHUTDOWN5 PWM mode only Thermal Shutdown Threshold 146 °C Thermal Shutdown Hysteresis 13 °C

1 The maximum operating junction temperature (TJ (MAX)) supersedes the

Considerations section for more information. specified temperature limits. the junction temperature is within specification limits. dissipation exists, attention to thermal board design is required. and environmental conditions. Table 3. Thermal Resistance (4-Layer PCB)

Figure 5. Pin Configuration Table 4. Pin Function Descriptions applied to MODE should never be higher than the voltage applied to VIN. Do not leave this pin floating.

*THE LOGIC HIGH ENABLE FEATURE IS ONLY AVAILABLE ON CERTAIN MODELS. Figure 29. Internal Block Diagram shutdown provide protection for internal circuit components. shut down to draw less than 0.3 μA (typical) from the source.

Rev. A | Page 12 of 20 SPREAD SPECTRUM OSCILLATOR The ADP2126/ADP2127 incorporate spread spectrum functionality to modulate electromagnetic interference (EMI) for EMI sensitive applications. A typical switching converter with a regulated switching frequency has a narrow frequency spectrum centered at the target switching frequency. This results in a high spectral density around the target frequency with peak emission levels that can exceed the regulatory levels for EMI in many portable, cellular, and wireless applications. To maintain acceptable levels of EMI, the ADP2126/ADP2127 employs spread spectrum via a controlled variance of the switching frequency over a wider band of frequencies. Figure 26 shows the variance of the frequency over time. This distribution of the frequency content spreads the spectral density over a wider bandwidth, resulting in lower peak emission levels. MODE SELECTION The ADP2126/ADP2127 have two modes of operation (PWM mode and auto mode), determined by the state of the MODE pin. Pull the MODE pin high to force the converter to operate in PWM mode, regardless of the output current. Otherwise, set MODE low to put the converter into auto mode and allow the converter to automatically transition from PWM mode to the power-saving PFM mode at light load currents. Do not leave this pin floating. Pulse-Width Modulation (PWM) Mode The PWM mode forces the part to maintain a fixed frequency of 6 MHz (maximum) under all load conditions. The ADP2126/ ADP2127 use a proprietary, hybrid voltage-mode control scheme to control the duty cycle under all load current and line voltage variations. This control scheme provides excellent stability, transient response, and output regulation. PWM mode results in lower efficiencies at light load currents. Auto Mode (PFM and PWM Switching) Auto mode is a power-saving feature that enables the converter to switch between PWM and PFM in response to the output load. Auto mode is enabled when the MODE pin is pulled low. In auto mode, the ADP2126/ADP2127 operate in PFM mode for light load currents and switch to PWM mode for medium and heavy load currents. 35BPulse Frequency Modulation (PFM) Mode When the converter is operating under light load conditions, the effective switching frequency and supply current are decreased and varied using PFM to regulate the output voltage. This results in improved efficiencies and lower quiescent currents. In PFM mode, the converter only switches when necessary to keep the output voltage within the PFM limits set by an internal comparator. Switching stops when the upper limit is reached and resumes when the lower limit is reached. When the upper level is reached, the output stage and most control circuitry turn off to reduce the quiescent current. During this stage, the output capacitor supplies the current to the load. As the output capacitor discharges and the output voltage reaches the lower PFM comparator threshold, switching resumes and the process repeats. Mode Transition When the MODE pin is low, the converter switches between PFM and PWM modes automatically to maintain optimal transient response and efficiency. The mode transition point depends on the input voltage. Hysteresis exists in the transition point to prevent instability and decreased efficiencies that could result if the converter were able to oscillate between PFM and PWM for a fixed input voltage and load current. See Figure 10 for the typical PFM and PWM mode boundaries of the ADP2126/ADP2127. A switch from PFM to PWM occurs when the output voltage dips below the nominal value of the output voltage option. Switching to PWM allows the converter to maintain efficiency and supply a larger current to the load. The output voltage in PFM mode is slightly higher to keep the ADP2126/ADP2127 from oscillating between modes, ensuring stable operation. The switch from PWM to PFM occurs when the output current is below the PFM threshold for multiple consecutive switching cycles. Switching to PFM allows the converter to save power by supplying the lighter load current with fewer switching cycles. INTERNAL CONTROL FEATURES Synchronous Rectification In addition to the P-channel MOSFET switch, the ADP2126/ ADP2127 include an N-channel MOSFET switch to build the synchronous rectifier. The synchronous rectifier improves efficiency, especially for small load currents, and reduces cost and board space by eliminating the need for an external rectifier. Soft Start To prevent excessive input inrush current at startup, the ADP2126/ ADP2127 operate with an internal soft start. When EXTCLK begins to oscillate, or when the part recovers from a fault (UVLO, TSD, or SCP), a soft start timer begins. During this time, the peak current limit is gradually increased to its maximum. The output voltage increases in stages to ensure that the converter is able to start up effectively and in proper sequence. After the soft start period expires, the peak PMOS switch current limit remains at 1 A (typical), and the part begins normal operation.

approximately 100 mV of hysteresis to ensure glitch-free startup. certain faults and transient events. nodes to discharge to an off state. yet still allows the converter to recover when the fault is removed. Figure 30. Power-Off Time 133°C (typical), at which point the regulator restarts.

compatible inductors and capacitors. This section describes the selection of external components. sizing is a trade-off between efficiency and transient response. which provides excellent transient response but degrades efficiency. value and lower current rating that can degrade performance. and 0.5 μH. Recommended inductors are shown in Table 5. fSW is the switching frequency. be greater than the peak inductor current (IPK) in the application. calculated IPK to prevent core saturation. voltage ripple caused by the switch currents on the VIN pin. resistance (ESR), and low equivalent series inductance (ESL). rating of 6.3 V or higher are recommended. Table 5. Inductor Selection Table 6. Input/Output Capacitor Selection

Rev. A | Page 15 of 20 OUTPUT CAPACITOR SELECTION The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. For a given loop crossover frequency (the frequency at which the loop gain drops to 0 dB), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. When choosing output capacitors, it is important to account for the loss of capacitance due to output voltage dc bias. This may result in using a capacitor with a higher rated voltage to achieve the desired capacitance value. Additionally, if ceramic output capacitors are used, the capacitor’s rms ripple current rating should always meet or exceed the application requirements. The rms ripple current is calculated from ( ) ) ( ) ( 3 2 MAXINSW OUTMAXINOUT COUTRMS V f L V V V I × × × = (5) At nominal load currents, the converter operates in forced PWM mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor. ΔV OUT = ΔIL × (ESR + 1/(8 × COUT × fSW)) (6) The largest voltage ripple occurs at the highest input voltage. The ADP2126/ADP2127 are designed to operate with one small 2.2 μF capacitor. For a 0.22 mm height solution using the ADP2127, at least 2 × 1.0 μF capacitors will be necessary on the output. X5R or X7R dielectrics that have low ESR, low ESL, and a voltage rating of 4 V or higher are recommended. These low ESR components help the ADP2126/ADP2127 meet tight output voltage ripple specifications. THERMAL CONSIDERATIONS The operating junction temperature (TJ) of the device is dependent on the ambient operating temperature (TA) of the application, the power dissipation of the ADP2126/ADP2127 (PD), and the junction-to-ambient thermal resistance of the package (θJA). The operating junction temperature (TJ) is calculated from TJ = TA + (PD × θJA) (7) where θJA is 105°C/W, as provided in Table 3. The ADP2126/ADP2127 may be damaged when the operating junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits.

• In applications with high PD and poor PCB thermal resistance, the maximum ambient temperature may need to be derated.
• In applications with moderate PD and good PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The power dissipation (PD) of the ADP2126/ADP2127 is only a portion of the power loss of the overall application. For a given application with known operating conditions, the application power loss is calculated by combining the following equations for power loss (P LOSS) and efficiency (η): PLOSS = PIN − POUT (8) 100× = IN OUT P Pη (9) The resulting equation uses the output power and the efficiency to determine the PLOSS. ⎛ −= 1100 ηOUTLOSS P P (10) The power loss calculated using this approach is the combined loss of the ADP2126/ADP2127 device (PD), the inductor (PL), input capacitor (PCIN), and the output capacitor (PCOUT), as shown in the following equation: PLOSS = PD + PL + PCIN + PCOUT (11) The power loss for the inductor, input capacitor, and output capacitor is calculated using PL = IRMS2 × DCR (12) CIN RMS CIN ESRIP ×⎟ 2 (13) PCOUT = (ΔIOUT)2 × ESRCOUT (14) If multilayer chip capacitors with low ESR are used, the power loss in the input and output capacitors is negligible and PD + PL >> PCIN + PCOUT (15) PLOSS ≈ PD + PL (16) The final equation for calculating PD can be used in Equation 7 to ensure that the operating junction temperature is not exceeded. LOUTLLOSSD PP P P P −⎟⎟ η (17)

0.40 REF

0.225 TYP

0.09 TYP

0.05 NOM

Figure 33. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] Figure 34. 6-Pad Embedded Wafer Level Package [EWLP] BUT THE A1 PIN LOCATION IS THE SAME. Figure 35. Tape and Reel Orientation for ADP2126/ADP2127

Rev. A | Page 18 of 20 ORDERING GUIDE Model1 Output Voltage EXTCLK Enable Type Temperature Range Package Description Package Option

2 Branding 3

ADP2126ACDZ-1.20R7 1.20 V Clock and logic −40°C to +85°C 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] CD-6-4 LHY ADP2127ACNZ1.260R7 1.26 V Clock only −40°C to +85°C 6-Pad Embedded Wafer Level [EWLP] CN-6-1 ADP2126-1.2-EVALZ 1.20 V Clock and logic Evaluation Board for ADP2126 ADP2127-1.26-EVALZ 1.26 V Clock only Evaluation Board for ADP2127 1 Z = RoHS Compliant Part. 2 These package options are halide free. 3 The ADP2127 does not have a Pin 1 indicator or a branding code. The bare Cu fiducial on the pad side can be used for device orientation.

Rev. A | Page 19 of 20 NOTES

Rev. A | Page 20 of 20 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09658-0-5/11(A)