ADP2119ACPZ-1.8-R7

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2 A/1.25 A, 1.2 MHz, Synchronous, Step-Down DC-to-DC Regulators ADP2119/ADP2120 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

ADP2119: 2 A ADP2120: 1.25 A 145 mΩ and 70 mΩ integrated MOSFETs Input voltage range from 2.3 V to 5.5 V Output voltage from 0.6 V to V IN ±1.5% output accuracy

1.2 MHz fixed switching frequency

Synchronizable between 1 MHz and 2 MHz Selectable PWM or PFM mode operation Current mode architecture Precision threshold enable input Power-good flag Voltage tracking Integrated soft start Internal compensation Startup with precharged output UVLO, OVP , OCP , and thermal shutdown 10-lead, 3 mm × 3 mm LFCSP_WD package

APPLICATIONS

Communications and networking equipment Industrial and instrumentation Consumer electronics Medical applications TYPICAL APPLICATION CIRCUIT 10EN ADP2119/ADP2120

1 VIN

10kΩ VIN 5V CIN 22µF X5R 6.3V COUT 22µF X5R 6.3V 0.1µF 10Ω RBOT 2.21kΩ VOUT 3.3V L 1.5µH RTOP 10kΩ 08716-001 Figure 1. GENERAL DESCRIPTION The ADP2119/ADP2120 are low quiescent current, synchronous, step-down dc-to-dc regulators in a compact 3 mm × 3 mm LFCSP_WD package. Both devices use a current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. Under light load conditions, they can be configured to operate in a pulse frequency modulation (PFM) mode, which reduces switching frequency to save power. The ADP2119/ADP2120 support input voltages from 2.3 V to 5.5 V . The output voltage can be adjusted from 0.6 V up to the input voltage (V IN) for the adjustable version, whereas the fixed output version is available in preset output voltage options of 3.3 V , minimal external parts and provide a high efficiency solution with their integrated power switches, synchronous rectifiers, and internal compensation. Each IC draws less than 2 μA current from the input source when it is disabled. Other key features include undervoltage lockout (UVLO), integrated soft start to limit inrush current at startup, overvoltage protection (OVP), overcurrent protection (OCP), and thermal shutdown (TSD). 100 0.01 0.1 1 EFFICIENCY (%) OUTPUT CURRENT (A) PFM FPWM VIN = 5V VOUT = 1.8V 08716-002 Figure 2. ADP2119 Efficiency vs. Output Current

Rev. 0 | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

6/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 24 SPECIFICATIONS VIN = VPVIN = 3.3 V , EN = VIN, SYNC/MODE = VIN at TJ = −40°C to +125°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit VIN and PVIN VIN Voltage Range VIN 2.3 5.5 V PVIN Voltage Range VPVIN 2.3 5.5 V Quiescent Current IVIN No switching, SYNC/MODE = GND 150 200 μA Switching, no load, SYNC/MODE = VIN 680 900 μA Shutdown Current ISHDN V IN = VPVIN = 5.5 V, EN = GND 0.3 2 μA VIN Undervoltage Lockout Threshold UVLO VIN rising 2.2 2.3 V VIN falling 2 2.1 V OUTPUT CHARACTERISTICS Load Regulation1 ADP2119, IO = 0 A to 2 A 0.08 %/A Load Regulation2 ADP2120, IO = 0 A to 1.25 A 0.08 %/A Line Regulation1 ADP2119, IO = 1 A 0.05 %/V Line Regulation2 ADP2120, IO = 1 A 0.05 %/V FB FB Bias Current IFB V IN = 2.3 V to 5.5 V 0.01 0.1 μA SW High-Side On Resistance3 VIN = VPVIN = 3.3 V, ISW = 200 mA 145 190 mΩ Low-Side On Resistance3 VIN = VPVIN = 3.3 V, ISW = 200 mA 70 100 mΩ SW Peak Current Limit High-side switch, VIN = VPVIN = 3.3 V (ADP2119) 2.5 3 3.5 A High-side switch, VIN = VPVIN = 3.3 V (ADP2120) 1.6 2 2.4 A SW Maximum Duty Cycle VIN = VPVIN = 5.5 V, full frequency 100 % SW Minimum On Time4 VIN = VPVIN = 5.5 V, full frequency 100 ns TRK TRK Input Voltage Range 0 600 mV TRK-to-FB Offset Voltage TRK = 0 mV to 500 mV −15 +15 mV TRK Input Bias Current 100 nA FREQUENCY Oscillator Frequency fS 1.02 1.2 1.38 MHz SYNC/MODE Synchronization Range 1 2 MHz SYNC Minimum Pulse Width 100 ns SYNC Minimum Off Time 100 ns SYNC Input High Voltage 1.3 V SYNC Input Low Voltage 0.4 V INTEGRATED SOFT START Soft Start Time All switching frequencies 1024 Clock cycles fS = 1.2 MHz 853 μs PGOOD Power-Good Range FB rising threshold 105 110 115 % FB rising hysteresis 2.5 % FB falling threshold 85 90 95 % FB falling hysteresis 2.5 % Power-Good Deglitch Time From FB to PGOOD 16 Clock cycles PGOOD Leakage Current VPGOOD = 5 V 0.1 1 μA PGOOD Output Low Voltage IPGOOD = 1 mA 150 200 mV PGOOD Output Low Resistor IPGOOD = 1 mA 150 200 Ω

Rev. 0 | Page 4 of 24 Parameter Symbol Test Conditions/Comments Min Typ Max Unit EN EN Input Hysteresis VIN = 2.3 V to 5.5 V 100 mV EN Pull-Down Resistor 1 MΩ THERMAL Thermal Shutdown Threshold 150 °C Thermal Shutdown Hysteresis 25 °C 1 Specified by the circuit in . Figure 54 2 Specified by the circuit in . Figure 58 3 Pin-to-pin measurements. 4 Guaranteed by design.

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance board (PCB) with thermal vias.

9 SYNC/MODE2PVIN

8 PGOOD3SW

7 TRK4PGND

6 FB5GND

1. THE EXPOSED PAD SHOULD BE SOLDERED TO

THE IC FOR THERMAL DISSIPATION. Figure 3. Pin Configuration (Top View) Table 4. Pin Function Descriptions small (10 Ω) resistor between this pin and PVIN. 2 PVIN Power Input Pin. Connect this pin to the input power source. Connect a bypass capacitor between this pin and PGND. 3 SW Switch Node Output. Connect this pin to the output inductor. 4 PGND Power Ground. Connect this pin to the power ground plane and to the high current return for the power MOSFET. 5 GND Analog Ground. Connect this pin to the ground plane. tracking function is not used, connect TRK to VIN. 8 PGOOD Power-Good Output (Open Drain). Connect this pin to a resistor to any pull-up voltage < 5.5 V. the switching frequency to the external clock (see the Oscillator and Synchronization section for details). and becomes active at light loads. enable the part automatically, connect the EN pin to VIN. This pin has a 1 MΩ pull-down resistor to GND. EP AD Exposed Pad The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation.

Figure 49. Functional Block Diagram

Rev. 0 | Page 16 of 24 THEORY OF OPERATION The ADP2119/ADP2120 are step-down, dc-to-dc regulators that use a fixed frequency, peak current mode architecture with integrated high-side switch and low-side synchronous rectifier. The high switching frequency and tiny 10-lead, 3 mm × 3 mm LFCSP_WD package provide a small step-down dc-to-dc regulator solution. The integrated high-side switch (P-channel MOSFET) and synchronous rectifier (N-channel MOSFET) yield high efficiency at medium-to-full loads while light load efficiency is improved using the PFM mode. The ADP2119/ADP2120 support input voltages from 2.3 V to 5.5 V and regulate the output voltage down to 0.6 V . The ADP2119/ADP2120 are also available with preset output CONTROL SCHEME The ADP2119/ADP2120 use a fixed frequency, peak current mode PWM control architecture and operate in PWM mode for medium-to-full loads but shift to PFM mode (if enabled) at light loads to maintain high efficiency. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage. When operating in PFM mode at light loads, the switching frequency is adjusted to regulate the output voltage. The ADP2119/ADP2120 operate in PWM mode when the load current is greater than the pulse-skipping threshold current. At load currents below this value, the regulator smoothly transitions to the PFM mode of operation. PWM MODE OPERATION In PWM mode, the ADP2119/ADP2120 operate at a fixed frequency. At the start of each oscillator cycle, the P-channel MOSFET switch is turned on, putting a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current level, turns off the P-channel MOSFET switch, and turns on the N-channel MOSFET synchronous rectifier. This puts a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle or until the inductor current reaches zero, which causes the zero- crossing comparator to turn off the N-channel MOSFET as well. The peak inductor current level is set by V COMP. VCOMP is the output of a transconductance error amplifier that compares the feedback voltage with an internal 0.6 V reference. PFM MODE OPERATION When PFM mode is enabled, the regulator smoothly transitions to the variable frequency PFM mode of operation when the load current decreases below the pulse-skipping threshold current. Switching continues only as necessary to maintain the output voltage within regulation. When the output voltage drops below regulation, the part enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies the load current. Because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. SLOPE COMPENSATION Slope compensation stabilizes the internal current control loop of the ADP2119/ADP2120 when operating close to and beyond the 50% duty cycle to prevent subharmonic oscillations. Slope compensation is implemented by summing an artificial voltage ramp to the current sense signal during the on-time of the P-channel MOSFET switch. This voltage ramp depends on the output voltage. When operating at high output voltages, there is more slope compensation. The slope compensation ramp value determines the minimum inductor that can be used to prevent subharmonic oscillations. ENABLE/SHUTDOWN The EN input pin has a precision analog threshold of 1.2 V (typical) with 100 mV of hysteresis. When the enable voltage exceeds 1.2 V , the regulator turns on, and when it falls below 1.1 V (typical), the regulator turns off. To force the part to automatically start when input power is applied, connect EN to VIN. When the ADP2119/ADP2120 are shut down, the soft start capacitor is discharged. This causes a new soft start cycle to begin when the part is reenabled. An internal pull-down resistor (1 MΩ) prevents an accidental enable if EN is left floating. INTEGRATED SOFT START The ADP2119/ADP2120 include integrated soft start circuitry to limit the output voltage rise time and reduce inrush current at startup. The soft start time is fixed at 1024 clock cycles. If the output voltage is precharged prior to turn-on, the part prevents reverse inductor current (which would discharge the output capacitor) by keeping both MOSFETs turned off until the soft start voltage exceeds the voltage on the FB pin.

Rev. 0 | Page 17 of 24 TRACKING The ADP2119/ADP2120 have a tracking input, TRK, that allows the output voltage to track another voltage (master voltage). The tracking input is especially useful in core and I/O voltage tracking for FPGAs, DSPs, and ASICs. The internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the TRK voltage. The error amplifier regulates the FB voltage to the lowest of the three voltages. To track a master voltage, tie the TRK pin to a resistor divider from the master voltage. If the tracking function is not used, connect the TRK pin to VIN. OSCILLATOR AND SYNCHRONIZATION To synchronize the ADP2119/ADP2120, drive an external clock at the SYNC/MODE pin. The frequency of the external clock can be in the 1 MHz to 2 MHz range. During synchronization, the regulator operates in CCM mode only, and the switching frequency is in phase with the external clock. CURRENT LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2119/ADP2120 have a peak current limit protection circuit to prevent current runaway. When the inductor peak current reaches the current limit value, the high-side MOSFET turns off and the low-side MOSFET turns on until the next cycle starts. The overcurrent counter increments during this time. If the overcurrent counter count exceeds 10, the part enters hiccup mode and both the high-side MOSFET and low-side MOSFET are turned off. The part remains in this mode for 4096 clock cycles and then attempts to restart from soft start. If the current limit fault has cleared, the part resumes normal operation. Otherwise, it reenters hiccup mode again after counting 10 current limit violations. OVERVOLTAGE PROTECTION (OVP) The output voltage is continuously monitored by a comparator through the FB pin, which is at 0.6 V (typical) under normal operation. This comparator is set to activate when the FB voltage exceeds 0.66 V (typical), thus indicating an output overvoltage condition. If the voltage remains above this threshold for 16 clock cycles, the high-side MOSFET turns off and the low-side MOSFET turns on until the current through the low-side MOSFET reaches the limit (−0.6 A for forced continuous conduction mode and 0 A for PFM mode). Thereafter, both the MOSFETs are held in the off state until FB falls below 0.54 V (typical), at this point, the part restarts. The behavior of PGOOD under this condition is described in the Power Good section. UNDERVOLTAGE LOCKOUT (UVLO) Undervoltage lockout circuitry is integrated in the ADP2119/ ADP2120. If the input voltage drops below 2.1 V , the part shuts down and both the power switch and synchronous rectifier turn off. When the voltage rises again above 2.2 V , the soft start period is initiated, and the part is enabled. THERMAL SHUTDOWN If the ADP2119/ADP2120 junction temperatures rise above 150°C, the thermal shutdown circuit turns off the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 25°C hysteresis is included so that if thermal shutdown occurs, the part does not return to operation until the on-chip temperature drops below 125°C. When coming out of thermal shutdown, soft start is initiated. POWER GOOD (PGOOD) PGOOD is an active high, open-drain output and requires a resistor to pull it up to a voltage. A high indicates that the voltage on the FB pin (and therefore the output voltage) is within ±10% of the desired value. A low on this pin indicates that the voltage on the FB pin is not within ±10% of the desired value. There is a 16 cycle waiting period after FB is detected as being out of bounds.

the ADP2119 is shown in Figure 50. Figure 50. Typical Application Circuit calculates the output voltage. load current trade-off between the transient response and efficiency. ΔIL is the inductor current ripple. D is the duty cycle. D = VOUT/VIN. by the selected inductor should not exceed 1.2 A. is greater than the peak current limit of the regulator. determine the output capacitor selection. The ESR and the capacitance determine the output ripple. capacitor, and the control loop. ADP2120. X5R or X7R ceramic capacitors are highly recommended. Table 5. Recommended L and COUT Values for the ADP2119 Table 6. Recommended L and COUT Values for the ADP2120

Figure 54. 1.2 V, 2 A, Step-Down Regulator, Forced Continuous Conduction Mode (ADP2119) Figure 55. 1.8 V, 2 A, Step-Down Regulator, Enable PFM Mode (ADP2119)

Figure 56. 2.5 V, 2 A, Step-Down Regulator, Synchronized to External Clock (ADP2119) Figure 57. 1.5 V, 1.25 A, Step-Down Regulator, Tracking Mode (ADP2120) Figure 58. 1.2 V, 1.25 A, Step-Down Regulator, Forced Continuous Conduction Mode (ADP2120)

0.20 REF

0.05 MAX

0.02 NOM

0.50 BSC

Figure 59. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

Rev. 0 | Page 23 of 24 NOTES

Rev. 0 | Page 24 of 24 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D08716-0-6/10(0)