ADP2105ACPZ-3.3-R7

ADP2105 AD | Alldatasheet

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1 Amp/1.5 Amp/2 Amp Synchronous, Step-Down DC-to-DC Converters ADP2105/ADP2106/ADP2107 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Extremely high 97% efficiency Ultralow quiescent current: 20 μA

1.2 MHz switching frequency

0.1 μA shutdown supply current Maximum load current: ADP2105: 1 A ADP2106: 1.5 A ADP2107: 2 A Input voltage: 2.7 V to 5.5 V Output voltage: 0.8 V to VIN Maximum duty cycle: 100% Smoothly transitions into low dropout (LDO) mode Internal synchronous rectifier Small 16-lead 4 mm × 4 mm LFCSP_VQ package Optimized for small ceramic output capacitors Enable/Shutdown logic input Undervoltage lockout Soft start

APPLICATIONS

PDAs and palmtop computers Telecommunication/Networking equipment Set top boxes Audio/Video consumer electronics GENERAL DESCRIPTION The ADP2105/ADP2106/ADP2107 are low quiescent current, synchronous, step-down dc-to-dc converters in a compact 4 mm × 4 mm LFCSP_VQ package. At medium-to-high load currents, these devices use a current-mode, constant-frequency pulse width modulation (PWM) control scheme for excellent stability and transient response. To ensure the longest battery life in portable applications, the ADP2105/ADP2106/ADP2107 use a pulse frequency modulation (PFM) control scheme under light load conditions that reduces switching frequency to save power. The ADP2105/ADP2106/ADP2107 run from input voltages of 2.7 V to 5.5 V , allowing single Li+/Li− polymer cell, multiple alkaline/NiMH cells, PCMCIA, and other standard power sources. The output voltage of ADP2105/ADP2106/ADP2107-ADJ is adjustable from 0.8 V to the input voltage, while the ADP2105/ ADP2106/ADP2107-xx are available in preset output voltage available in three maximum current levels, 1 A (ADP2105), 1.5 A (ADP2106), and 2 A (ADP2107). The power switch and synchro- nous rectifier are integrated for minimal external part count and high efficiency. During logic-controlled shutdown, the input is disconnected from the output, and it draws less than 0.1 μA from the input source. Other key features include undervoltage lockout to prevent deep-battery discharge and programmable soft start to limit inrush current at startup. TYPICAL PERFORMANCE CHARACTERISTICS 100 0 2000 06079-001 LOAD CURRENT (mA) EFFICIENCY (%) 200 400 600 800 1000 1200 1400 1600 1800 VIN =3 . 3 V VIN =3 . 6 V VIN =5 V VOUT =2 . 5 V Figure 1. Efficiency vs. Load Current for the ADP2107 with VOUT = 2.5 V Figure 2. Circuit Configuration of ADP2107 with VOUT = 2.5 V

Rev. 0 | Page 2 of 32 TABLE OF CONTENTS Recommended PCB Board Layout

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 32 SPECIFICATIONS VIN = 3.6 V @ TA = 25°C, unless otherwise noted.1 Bold values indicate −40°C ≤ TJ ≤ +125°C. Table 1. Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Input Voltage Range 2.7 5.5 V Undervoltage Lockout Threshold VIN rising 2.2 2.4 2.6 V VIN falling 2.0 2.2 2.5 V Undervoltage Lockout Hysteresis2 200 mV OUTPUT CHARACTERISTICS Output Regulation Voltage ADP210x-3.3, load = 10 mA 3.267 3.3 3.333 V ADP210x-1.8, load = 10 mA 1.782 1.8 1.818 V ADP210x-1.5, load = 10 mA 1.485 1.5 1.515 V ADP210x-1.2, load = 10 mA 1.188 1.2 1.212 V Load Regulation ADP2105 0.4 %/A ADP2106 0.5 %/A ADP2107 0.6 %/A Line Regulation3 Measured in servo loop 0.1 0.3 %/V Output Voltage Range ADP210x-ADJ 0.8 VIN V FEEDBACK CHARACTERISTICS ADP210x-1.2 3 6 μA ADP210x-1.5 4 8 μA ADP210x-1.8 5 10 μA OUT_SENSE Bias Current ADP210x-3.3 10 20 μA FB Regulation Voltage ADP210x-ADJ 0.784 0.8 0.816 V FB Bias Current ADP210x-ADJ −0.1 +0.1 μA INPUT CURRENT CHARACTERISTICS IN Operating Current ADP210x-ADJ, VFB = 0.9 V 20 30 μA ADP210x-xx, output voltage 10% above regulation voltage 20 30 μA IN Shutdown Current VEN = 0 V 0.1 15 μA LX (SWITCH NODE) CHARACTERISTICS LX On Resistance4 P-channel switch 100 165 mΩ N-channel synchronous rectifier 90 140 mΩ LX Leakage Current4 VIN = 5.5 V, VLX = 0 V, 5.5 V 0.1 15 μA LX Peak Current Limit4 P-channel switch, ADP2107 2.6 2.9 3.3 A P-channel switch, ADP2106 2.0 2.25 2.6 A P-channel switch, ADP2105 1.3 1.5 1.8 A LX Minimum On-Time4 In PWM mode of operation, VIN = 5.5 V 100 ns ENABLE CHARACTERISTICS EN Input High Voltage VIN = 2.7 V to 5.5 V 2 V EN Input Low Voltage VIN = 2.7 V to 5.5 V 0.4 V EN Input Leakage Current VIN = 5.5 V, VEN = 0 V, 5.5 V −1 −0.1 +1 μA OSCILLATOR FREQUENCY VIN = 2.7 V to 5.5 V 1 1.2 1.4 MHz SOFT START PERIOD CSS = 1 nF 750 1000 1200 μs

Rev. 0 | Page 4 of 32 Parameter Conditions Min Typ Max Unit THERMAL CHARACTERISTICS Thermal Shutdown Threshold 140 °C Thermal Shutdown Hysteresis 40 °C COMPENSATOR TRANSCONDUCTANCE (Gm) 50 μA/V ADP2105 1.875 A/V ADP2106 2.8125 A/V CURRENT SENSE AMPLIFIER GAIN (GCS)2 ADP2107 3.625 A/V 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C. 2 Guaranteed by design. 3 The ADP2015/ADP2106/ADP2107 line regulation was measured in a servo loop on the ATE that adjusts the feedback voltage to achieve a specific comp voltage. 4 All LX (switch node) characteristics are guaranteed only when the LX1 and LX2 pins are tied together. 5 These specifications are guaranteed from −40°C to +85°C.

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance soldered in circuit board for surface mount packages. degradation or loss of functionality.

11 PGND

12 LX2

10 LX1

15 GND

16 OUT_SENSE/FB

13 PWIN1

Figure 3. Pin Configuration Table 4. Pin Function Descriptions it off and reduce the input current to 0.1 μA. error amplifier. Place a series RC network from COMP to AGND to compensate the converter. See the Loop Compensation section. sets a 1 ms soft start period. ADP2106/ADP2107. Also connect AGND to the exposed pad of ADP2105/ADP2106/ADP2107. 8 NC NC No Connect. Not internally connected. Can be connected to other pins or left unconnected. Input Capacitor Selection section. 10, 12 LX1, LX2 LX1, LX2 Switch Outputs. The drain of the P-channel power switch and N-channel synchronous rectifier. connect PGND to the exposed pad of the ADP2105/ADP2106/ADP2107. a resistive voltage divider to set the output voltage. The FB regulation voltage is 0.8 V.

Rev. 0 | Page 13 of 32 SLOPE COMPENSATION Slope compensation stabilizes the internal current control loop of the ADP2105/ADP2106/ADP2107 when operating beyond 50% duty cycle to prevent sub-harmonic oscillations. It is imple- mented by summing a fixed scaled voltage ramp to the current sense signal during the on-time of the P-channel MOSFET switch. The slope compensation ramp value determines the minimum inductor that can be used to prevent sub-harmonic oscillations at a given output voltage. The slope compensation ramp values for ADP2105/ADP2106/ADP2107 follow. For more information, see the Inductor Selection section. For the ADP2105: Slope Compensation Ramp Value = 0.72 A/μs For the ADP2106: Slope Compensation Ramp Value = 1.07 A/μs For the ADP2107: Slope Compensation Ramp Value = 1.38 A/μs Drive EN high to turn on the ADP2105/ADP2106/ADP2107. Drive EN low to turn off the ADP2105/ADP2106/ADP2107, reducing input current below 0.1 μA. To force the ADP2105/ ADP2106/ADP2107 to automatically start when input power is applied, connect EN to IN. When shut down, the ADP2105/ ADP2106/ADP2107 discharge the soft start capacitor, causing a new soft start cycle every time they are re-enabled. Synchronous Rectification In addition to the P-channel MOSFET switch, the ADP2105/ ADP2106/ADP2107 include an integrated N-channel MOSFET synchronous rectifier. The synchronous rectifier improves efficiency, especially at low output voltage, and reduces cost and board space by eliminating the need for an external rectifier. Current Limit The ADP2105/ADP2106/ADP2107 have protection circuitry to limit the direction and amount of current flowing through the power switch and synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output, while the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. Short Circuit Protection The ADP2105/ADP2106/ADP2107 include frequency foldback to prevent output current run-away on a hard short. When the voltage at the feedback pin falls below 0.3 V , indicating the possi- bility of a hard short at the output, the switching frequency is reduced to 1/4 of the internal oscillator frequency. The reduction in the switching frequency gives more time for the inductor to discharge, preventing a runaway of output current. Undervoltage Lockout (UVLO) To protect against deep battery discharge, undervoltage lockout circuitry is integrated on the ADP2105/ADP2106/ADP2107. If the input voltage drops below the 2.2 V UVLO threshold, the ADP2105/ADP2106/ADP2107 shut down, and both the power switch and synchronous rectifier turn off. Once the voltage rises again above the UVLO threshold, the soft start period is initiated, and the part is enabled. Thermal Protection In the event that the ADP2105/ADP2106/ADP2107 junction temperatures rise above 140°C, the thermal shutdown circuit turns off the converter. Extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 40°C hysteresis is included so that when thermal shutdown occurs, the ADP2105/ADP2106/ ADP2107 do not return to operation until the on-chip tempera- ture drops below 100°C. When coming out of thermal shutdown, soft start is initiated. Soft Start The ADP2105/ADP2106/ADP2107 include soft start circuitry to limit the output voltage rise time to reduce inrush current at startup. To set the soft start period, connect the soft start capacitor (CSS) from SS to AGND. When the ADP2105/ADP2106/ ADP2107 are disabled, or if the input voltage is below the under- voltage lockout threshold, CSS is internally discharged. When the ADP2105/ADP2106/ADP2107 are enabled, CSS is charged through an internal 0.8 μA current source, causing the voltage at SS to rise linearly. The output voltage rises linearly with the voltage at SS.

1FB FOR ADP210x-ADJ (ADJUSTABLE VERSION) AND OUT_SENSE FOR ADP210x-xx (FIXED VERSION). Figure 34. Block Diagram of the ADP2105/ADP2106/ADP2107

load for improved load regulation. allows for minimal output voltage ripple even with small inductors. are recommended for their low core losses and low EMI. transient response and efficiency. where fSW is the switching frequency (1.2 MHz). under light load conditions. Table 5. Minimum Inductor Value for Common Output Table 6. Minimum Inductor Value for Common Output Table 7. Minimum Inductor Value for Common Output Table 8. Inductor Recommendations for the ADP2105/

Rev. 0 | Page 18 of 32 INPUT FILTER The IN pin is the power source for the ADP2105/ADP2106/ ADP2107 internal circuitry, including the voltage reference and current sense amplifier that are sensitive to power supply noise. To prevent high frequency switching noise on the PWIN pins from corrupting the internal circuitry of the ADP2105/ADP2106/ ADP2107, a low-pass RC filter should be placed between the IN pin and the PWIN1 pin. The suggested input filter consists of a small 0.1 μF ceramic capacitor placed between IN and AGND and a 10 Ω resistor placed between IN and PWIN1. This forms a 150 kHz low-pass filter between PWIN1 and IN that prevents any high frequency noise on PWIN1 from coupling into the IN pin. SOFT START The ADP2105/ADP2106/ADP2107 include soft start circuitry to limit the output voltage rise time to reduce inrush current at startup. T o set the soft start period, connect a soft start capacitor (CSS) from SS to AGND. The soft start period varies linearly with the size of the soft start capacitor, as shown in the following equation: TSS = CSS × 109 ms To get a soft start period of 1 ms, a 1 nF capacitor must be connected between SS and AGND. LOOP COMPENSATION The ADP2105/ADP2106/ADP2107 utilize a transconductance error amplifier to compensate the external voltage loop. The open loop transfer function at angular frequency, s, is given by OUT REF OUT COMP CSm V V sC s ZG G s H ) () ( where: VREF is the internal reference voltage (0.8 V). VOUT is the nominal output voltage. ZCOMP(s) is the impedance of the compensation network at the angular frequency, s. COUT is the output capacitor. Gm is the transconductance of the error amplifier (50 μA/V nominal). GCS is the effective transconductance of the current loop. GCS = 1.875 A/V for the ADP2105. GCS = 2.8125 A/V for the ADP2106. GCS = 3.625 A/V for the ADP2107. The transconductance error amplifier drives the compensation network that consists of a resistor (RCOMP) and capacitor (CCOMP) connected in series to form a pole and a zero, as shown in the following equation: ⎛ +=⎟⎟ ⎛ + = COMP COMPCOMP COMP COMPCOMP sC C sR sCR s Z 11) ( At the crossover frequency, the gain of the open loop transfer function is unity. This yields the following equation for the compensation network impedance at the crossover frequency: REF OUTOUT CSm CROSS CROSSCOMP V V C G G FF Z ) 2 () ( π where: FCROSS = 80 kHz, the crossover frequency of the loop. COUTVOUT is determined from the Output Capacitor Selection section. To ensure that there is sufficient phase margin at the crossover frequency, place the Compensator Zero at 1/4 of the crossover frequency, as shown in the following equation: 14) π 2 ( =⎟⎠ ⎞⎜⎝ COMPCOMP CROSS C RF Solving the above two simultaneous equations yields the value for the compensation resistor and compensation capacitor, as shown in the following equation: REF OUTOUT CSm CROSS COMP V V C G G FR ) π 2 (8 . 0 COMPCROSS COMP R FC π

Rev. 0 | Page 21 of 32 EFFICIENCY CONSIDERATIONS Efficiency is defined as the ratio of output power to input power. The high efficiency of the ADP2105/ADP2106/ADP2107 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package that reduces thermal constraints. In addition, high efficiency delivers the maximum output power for the given input power, extending battery life in portable applications. There are four major sources of power loss in dc-to-dc converters like the ADP2105/ADP2106/ADP2107.

• Power switch conduction losses
• Inductor losses
• Switching losses
• Transition losses Power Switch Conduction Losses Power switch conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (R DS(ON)) associated with them. The amount of power loss can be approxi- mated by PSW − COND = [RDS(ON) − P × D + RDS(ON) − N × (1 − D)] × IOUT2 where D = VOUT/VIN. The internal resistance of the power switches increases with temperature but decreases with higher input voltage. Figure 19 in the Typical Performance Characteristics section shows the change in RDS(ON) vs. input voltage, while Figure 27 in the Typical Performance Characteristics section shows the change in RDS(ON) vs. temperature for both power devices. Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (DCR) associated with it. Larger sized inductors have smaller DCR, which can improve inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the ADP2105/ADP2106/ADP2107 are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI. The total amount of inductor power loss can be calculated by PL = DCR × IOUT2 + Core Losses Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge ΔQ from the input supply to the gate and then from the gate to ground. The amount of power loss can by calculated by PSW = (CGATE − P + CGATE − N) × VIN2 × fSW where: (CGATE − P + CGATE − N) ~ 600 pF. fSW = 1.2 MHz, the switching frequency. Transition Losses Transition losses occur because the P-channel MOSFET power switch cannot turn on or turn off instantaneously. At the middle of a LX node transition, the power switch is providing all the inductor current, while the source to drain voltage of the power switch is half the input voltage, resulting in power loss. Transition losses increase with load current and input voltage and occur twice for each switching cycle. The amount of power loss can be calculated by SWOUT IN TRAN f t t IVP OFFON × + × × =) (2 where tON and tOFF are the rise time and fall time of the LX node, which are approximately 3 ns. THERMAL CONSIDERATIONS In most applications, the ADP2105/ADP2106/ADP2107 do not dissipate a lot of heat due to their high efficiency. However, in applications with high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125°C. Once the junction temperature exceeds 140°C, the converter goes into thermal shutdown. It recovers only after the junction temperature has decreased below 100°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application solution is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation in it.

TR is the rise in temperature of the package. PD is the power dissipation in the package. ambient temperature of the package. is used with an input voltage of 3.6 V and a load current of 2 A. Also, assume that the maximum ambient temperature is 85°C. Table 3. Thus, the rise in temperature of the package due to which is below the maximum junction temperature of 125°C. Input Voltage = 3.6 V to 4.2 V . Typical Output Current = 600 mA. Maximum Output Current = 1.2 A. Overshoot ≤ 100 mV under all load transient conditions.

1. Choose the dc-to-dc converter that satisfies the maximum
2. See whether the output voltage desired is available as a
3. The first step in external component selection for an

the resistive voltage divider that sets the output voltage.

1. Calculate the minimum inductor value as follows:

maximum load current at the maximum input voltage. criteria is the LPS4012-2.2 μH from Coilcraft.

1. Choose the output capacitor based on the transient

1.2 A, for which the overshoot must be less than 100 mV ,

Rev. 0 | Page 23 of 32 6. Because the ADP2106 is being used in this application, the input capacitors are 10 μF and 4.7 μF X5R Murata capacitors (GRM21BR61A106K and GRM21BR61A475K). 7. The input filter consists of a small 0.1 μF ceramic capacitor placed between IN and AGND and a 10 Ω resistor placed between IN and PWIN1. 8. Choose a soft start capacitor of 2 nF to achieve a soft start time of 2 ms. 9. Finally, the compensation resistor and capacitor can be calculated as REF OUTOUT CSm CROSS COMP V V C G G FR ) π 2 (8 . 0 Ω =⎟⎟ ⎛ × ×= k 215V 8 . 0 V 2 μF 30 V / A 8125 . 2 V / μA 50 kHz 80 ) π 2 (8 .0 pF 39 kΩ215 kHz 80 π π 2 = × × COMPCROSS COMP R F C

Table 10. Recommended External Components for Popular Output Voltage Options at 80 kHz Crossover Frequency with

Table 11. Recommended External Components for Popular Output Voltage Options at 80 kHz Crossover Frequency with

Rev. 0 | Page 26 of 32 CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is essential in obtaining the best performance from the ADP2105/ADP2106/ADP2107. Poor circuit layout degrades the output ripple, as well as the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance. Figure 52 and Figure 53 show the ideal circuit board layout for the ADP2105/ADP2106/ADP2107. Use this layout to achieve the highest performance. Refer to the following guidelines if adjustments to the suggested layout are needed.

• Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry (such as compensation and output voltage divider components) to analog ground; connect the ground reference of power components (such as input and output capacitors) to power ground. In addition, connect both the ground planes to the exposed pad of the ADP2105/ADP2106/ADP2107.
• For each PWIN pin, place an input capacitor as close to the PWIN pin as possible and connect the other end to the closest power ground plane.
• Place the 0.1 μF, 10 Ω low-pass input filter between the IN pin and the PWIN1 pin, as close to the IN pin as possible.
• Ensure that the high current loops are as short and as wide as possible. Make the high current path from CIN through L, COUT, and the PGND plane back to CIN as short as possible. To accomplish this, ensure that the input and output capacitors share a common PGND plane. Also, make the high current path from PGND pin of the ADP2105/ADP2106/ADP2107 through L and COUT back to the PGND plane as short as possible. To do this, ensure that the PGND pin of the ADP2105/ADP2106/ADP2107 is tied to the PGND plane as close as possible to the input and output capacitors.
• Place the feedback resistor divider network as close as possible to the FB pin to prevent noise pickup. Try to minimize the length of trace connecting the top of the feedback resistor divider to the output while keeping away from the high current traces and the switch node (LX) that can lead to noise pickup. To reduce noise pickup, place an analog ground plane on either side of the FB trace. For the low fixed voltage options (1.2 V and 1.5 V), poor routing of the OUT_SENSE trace can lead to noise pickup, adversely affecting load regulation. This can be fixed by placing a 1 nF bypass capacitor close to the OUT_SENSE pin.
• The placement and routing of the compensation components are critical for proper behavior of the ADP2105/ADP2106/ ADP2107. The compensation components should be placed as close to the COMP pin as possible. It is advisable to use 0402-sized compensation components for closer placement, leading to smaller parasitics. Surround the compensation components with analog ground plane to prevent noise pickup. Also, ensure that the metal layer under the compensation components is the analog ground plane.

1 MURATA X5R 0805

Figure 51. Evaluation Board Schematic of the ADP2107-1.8 (Bold Traces Are High Current Paths) CLOSE TO THE FB PIN AS POSSIBLE. DIVIDER TO THE ANALOG GROUND PLANE. Figure 52. Recommended Layout of Top Layer of ADP2105/ADP2106/ADP2107

RESISTIVE VOLTAGE DIVIDER ON THE FB PIN TO THE OUTPUT. CURRENT TRACES AS POSSIBLE TO PREVENT NOISE PICKUP. Figure 53. Recommended Layout of Bottom Layer of ADP2105/ADP2106/ADP2107

F O RA1 AL O A DT R A N S I E N T . Figure 54. Application Circuit—VIN = 5 V, VOUT = 3.3 V, LOAD = 0 A to 2 A

2 TOKO D62LCB OR COILCRAFT LPS4012

F O RA1 AL O A DT R A N S I E N T . Figure 55. Application Circuit—VIN = 3.6 V, VOUT = 1.5 V, LOAD = 0 A to 2 A F O RA1 AL O A DT R A N S I E N T . Figure 56. Application Circuit—VIN = Li-Ion Battery, VOUT = 1.8 V, LOAD = 0 A to 1 A

2 TOKO 1069AS-DB3018HCT OR

Figure 57. Application Circuit—VIN = Li-Ion Battery, VOUT = 1.2 V, LOAD = 0 A to 1 A Figure 58. Application Circuit—VIN = 5 V, VOUT = 2.5 V, LOAD = 0 A to 1.5 A

1.95 BSC

0.80 SEATING

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.65 BSC

0.60 MAX

0.25 MIN

Figure 59. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 32 of 32 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06079-0-7/06(0)