ADP2102 Data Sheet (Rev. C)
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Low Duty Cycle, 600 mA, 3 MHz, Synchronous Step-Down DC-to-DC Converter Data Sheet ADP2102 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Input voltage range: 2.7 V to 5.5 V 600 mA maximum load current 95% efficiency Low duty cycle operation Only 3 tiny external ceramic components
3 MHz typical operating frequency
Fixed output voltage of 1.2 V or 1.375 V Adjustable output voltage up to 3.3 V 0.01 µA shutdown supply current Automatic power save mode Internal synchronous rectifier Internal soft start Internal compensation Enable/shutdown logic input Undervoltage lockout Current limit protection Thermal shutdown Small 8-lead, 3 mm × 3 mm LFCSP
APPLICATIONS
Processor core power from 5 V Digital cameras PDAs and palmtop computers Portable media players, GPS GENERAL DESCRIPTION The ADP2102 is a synchronous step-down dc-to-dc converter that converts a 2.7 V to 5.5 V unregulated input voltage to a lower regulated output voltage with up to 95% efficiency and 1% accuracy. The low duty cycle capability of the ADP2102 is ideal for USB applications or 5 V systems that power up submicron subvolt processor cores. Its 3 MHz typical operating frequency and excel- lent transient response allow the use of small, low cost 1 µH inductors and 2.2 µF ceramic capacitors. At medium-to-high load currents, it uses a current mode, pseudofixed frequency pulse- width modulation to extend battery life. To ensure the longest battery life in portable applications, the ADP2102 has a power save mode (PSM) that reduces the switching frequency under light load conditions to significantly reduce quiescent current. TYPICAL APPLICATION CIRCUIT CIN 2.2µF 1µH L COUT 2.2µF OUTPUT VOLTAGE 1.2V OR 1.375V INPUT VOLTAGE 2.7V TO 5.5V FORCED CCM DCM/ CCM ON OFF 06631-001 ADP2102 LX FB/OUT VIN MODE EN GND Figure 1. The ADP2102 is available in both fixed and adjustable output voltage options with a 600 mA maximum output current. The fixed output voltage options are 1.2 V and 1.375 V. The adjustable output voltage options are available from 1.5 V to 3.3 V. The ADP2102 requires only three external components and consumes 0.01 µA in shutdown mode. The ADP2102 is available in an 8-lead LFCSP and is specified for the −40°C to +85°C temperature range. EFFICIENCY (%) 10 100 1000 LOAD CURRENT (mA) 06631-052 VOUT = 1.375V TA = 25°CVIN = 2.7V VIN = 4.2V VIN = 3V 100 VIN = 3.6V Figure 2. Efficiency vs. Load Current at VOUT = 1.375 V
Rev. C | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
7/2016—Rev. B to Rev. C Changed ADP2102-ADJ to ADP2102 Adjustable Output Voltage Options, ADP2102-FXD to ADP2102 Fixed Output Voltage Options, ADP2102-xx to ADP2102 Fixed Output Changes to Features Section, General Description Section, and 9/2007—Rev. A to Rev. B Changes to Features Section, Applications Section, and General 6/2007—Rev. 0 to Rev. A 6/2007—Revision 0: Initial Version
Rev. C | Page 3 of 24 SPECIFICATIONS VIN = 3.6 V , EN = VIN, MODE = VIN, TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TA ≤ +85°C.1 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Voltage Range2 2.7 5.5 V Undervoltage Lockout Threshold V IN rising 2.2 2.4 2.5 V Undervoltage Lockout Hysteresis 220 mV OUTPUT CHARACTERISTICS Output Voltage Range ADP2102 fixed output voltage options 1.2 1.375 V Output Voltage Range ADP2102 adjustable output voltage options 1.5 3.3 V Output Voltage Initial Accuracy ADP2102 fixed output voltage options, TA= 25°C, ILOAD = 0 mA −1 +1 % ADP2102 fixed output voltage options, −40°C ≤TA ≤ 85°C, ILOAD = 0 mA −2 +2 % Load Regulation VOUT = 1.2 V to 1.375 V, ILOAD = 0 mA to 600 mA 0.5 % Line Regulation VIN = 2.7 V to 5.5 V, ILOAD = 10 mA 0.3 % FEEDBACK CHARACTERISTICS FB Regulation Voltage ADP2102 adjustable output voltage options 784 800 816 mV FB Bias Current ADP2102 adjustable output voltage options 50 nA FB Impedance ADP2102 fixed output voltage options 375 kΩ CURRENT CHARACTERISTICS Operating Current ADP2102 PSM mode, ILOAD = 0 mA 70 99 μA Shutdown Current EN = 0 V 0.01 1 μA Output Current ADP2102, VIN = 2.7 V to 5.5 V 600 mA LX (SWITCH NODE) CHARACTERISTICS LX On Resistance P-channel switch, ILX = 100 mA 325 600 mΩ N-channel synchronous rectifier, ILX = 100 mA 200 400 mΩ LX Leakage Current VIN = 5.5 V, VLX = 0 V, 5.5 V 1 μA LX Minimum Off Time ADP2102 fixed output voltage options, ADP2102 adjustable output voltage options 100 ns LX On Time 1.2 V fixed output voltage 100 131 160 ns
1.375 V fixed output voltage 135 165 195 ns
ADP2102-3, VOUT = 1.5 V 155 177 210 ns ADP2102-3, VOUT = 1.875 V 200 226 275 ns ADP2102-4, VOUT = 3.3 V (VIN = 5 V) 198 238 270 ns Valley Current Limit 1 A ENABLE, MODE CHARACTERISTICS EN, MODE Input High Threshold 1.3 V EN, MODE Input Low Threshold 0.4 V EN, MODE Input Leakage Current V IN = 5.5 V, EN = MODE = 0 V, 5.5 V 1 μA SOFT START PERIOD 250 500 800 μs THERMAL CHARACTERISTICS Thermal Shutdown Threshold 150 °C Thermal Shutdown Hysteresis 15 °C 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 The input voltage (VIN) range over which the rest of the specifications are valid. The device operates as expected until VIN goes below the UVLO threshold.
1 The ADP2102 can be damaged when junction temperature limits are exceeded. otherwise specified, all other voltages are referenced to AGND. Lead Frame Chip Scale Package (LFCSP). Table 3. Thermal Resistance Natural convection, 4-layer board, exposed pad soldered to PCB.
- CONNECT THE EXPOSED PAD TO THE GROUND PLANE.
5 PGND
8 AVIN
7 PVINADP102
Figure 3. Pin Configuration Table 4. Pin Function Descriptions ADP2102 to power save mode/auto mode (PSM), drive MODE low. 0.1 µA. This pin cannot be left floating. electrically common with the analog ground pin. the output LC filter between LX and the output voltage. required on this pin to the nearest PGND plane. RC filter are 10 Ω and 0.1 µF, respectively. This configuration can be used for all loads. For light-to-medium loads up to 300 mA, the AVIN pin and the PVIN pin can be shorted together. PGND plane. Do not short the AVIN and PVIN pins when using only a bypass capacitor. 0 EPAD Exposed Pad. Connect the exposed pad to the ground plane.
60 EFFICIENCY (%)
Figure 4. Efficiency vs. Load Current (VOUT = 1.2 V) Figure 5. Efficiency vs. Load Current (VOUT = 1.5 V) Figure 6. Efficiency vs. Load Current (VOUT = 1.8 V)
1.18 OUTPUT VOLTAGE (V)
Figure 7. Output Voltage Accuracy (VOUT = 1.2 V)
1.48 OUTPUT VOLTAGE (V)
Figure 8. Output Voltage Accuracy (VOUT = 1.5 V)
1.78 OUTPUT VOLTAGE (V)
Figure 9. Output Voltage Accuracy (VOUT = 1.8 V)
Figure 10. Efficiency vs. Load Current (VOUT = 3.3 V)
50 EFFICIENCY (%)
Figure 11. PSM vs. CCM Efficiency (VOUT = 1.8 V) Figure 12. Output Voltage vs. Load Current (VOUT = 1.2 V) Figure 13. Output Voltage vs. Load Current (VOUT = 1.5 V) Figure 14. Output Voltage vs. Load Current (VOUT = 1.8 V) Figure 15. Output Voltage vs. Temperature (VOUT = 1.2 V)
Figure 16. Output Voltage vs. Temperature (VOUT = 1.5 V) Figure 17. Output Voltage vs. Temperature (VOUT = 1.8 V)
3.20 OUTPUT VOLTAGE (V)
Figure 18. Output Voltage Accuracy (VOUT = 3.3 V)
60 QUIESCENT CURRENT (µA)
Figure 19. Quiescent Current vs. Input Voltage Figure 20. Quiescent Current vs. Temperature Figure 21. Feedback Voltage vs. Temperature
Figure 22. Switching Frequency vs. Load Current
1.00 CURRENT LIMIT (A)
Figure 23. Valley Current Limit Figure 24. Switch On Resistance vs. Input Voltage Figure 25. Switch On Resistance vs. Temperature Figure 26. PSM Mode Operation at Very Light Loads (10 mA) Figure 27. PSM Mode Entry—Exit Operation (10 mA to 50 mA to 10 mA)
Rev. C | Page 13 of 24 THEORY OF OPERATION The ADP2102 is a high frequency, synchronous step-down, dc-to-dc converter optimized for battery-powered, portable applications. It is based on constant on-time current-mode control architecture with voltage feed forward to null frequency variation with line voltage, creating a pseudofixed frequency. This type of control allows generation of very low output voltages at a higher switching frequency and offers a very fast load and line transient response with minimal external component count and size. The ADP2102 provides features such as undervoltage lockout, thermal shutdown, and short-circuit protection. The ADP2102 uses valley current-mode control, which helps to prevent minimum on-time limitations at very low output voltages. This allows high frequency operation, resulting in low filter inductor and capacitor values. CONTROL SCHEME The ADP2102 high-side power switch on time is determined by a one-shot timer whose pulse width is directly proportional to the output voltage and inversely proportional to the input or line voltage. Another one-shot timer sets a minimum off time to allow for inductor valley current sensing. The constant on-time, one-shot timer is triggered at the rising edge of EN and, subsequently, when the low-side power switch current is below the valley current limit threshold and the minimum off-time one-shot timer has timed out. While the constant on time is asserted, the high-side power switch is turned on. This causes the inductor current to ramp positively. After the constant on time has completed, the high- side power switch turns off and the low-side power switch turns on. This causes the inductor current to ramp negatively until the sensed current flowing in this switch has reached valley current limit. At this point, the low-side power switch turns off and a new cycle begins with the high-side switch turning on, provided that the minimum off-time one shot has timed out. CONSTANT ON-TIME TIMER The constant on-time timer sets the high-side switch on time. This fast, low jitter, adjustable one shot varies the on time in response to input voltage for a given output voltage. The high- side switch on time is inversely proportional to the input voltage and directly proportional to the output voltage. t ON = K(VOUT/VIN) (1) The duty cycle for a buck converter operating in continuous conduction mode (CCM) is given by D = V OUT/VIN and, by definition, D = tON/(tON + tOFF). Therefore, equating the duty cycle terms of VOUT/VIN and tON/(tON + tOFF) gives tON = VOUT/(VIN × fSW) (2) Equating Equation 1 and Equation 2 gives fSW = 1/K (3) where K is an internally set on-time scale factor constant resulting in a constant switching frequency. As shown in Equation 1, the steady state switching frequency is theoretically independent of both the input and output voltages to a first order. This means the loop switches at a nearly constant frequency until a load step occurs. When a load step occurs, the constant on-time control loop responds by modulating the off time up or down to quickly return to regulation. This momentary frequency variation results in a faster load transient response than a fixed frequency current-mode control loop of similar bandwidth with a similar external filter inductor and capacitor. This is an advantage of a constant on-time control scheme. Resistive voltage losses in the high-side and low-side power switches, package parasitics, inductor DCR, and board parasitic resistance cause the loop to compensate by reducing the off time and, therefore, increase the switching frequency with increasing load current. A minimum off-time constraint is introduced to allow inductor valley current sensing on the synchronous switch. FORCED CONTINUOUS CONDUCTION MODE When the MODE pin is high, the ADP2102 operates in forced continuous conduction mode (CCM). In this mode, irrespective of the load current, the inductor current stays continuous, and CCM is the preferred mode of operation for low noise applications. During this mode, the switching frequency stays close to 3 MHz typical. In this mode, efficiency is lower at light loads, compared to the power save mode, but the output voltage ripple is minimized. POWER SAVE MODE When the MODE pin is low, the ADP2102 operates in power save mode (PSM). In this mode, at light load currents, the device automatically goes into reduced frequency operation where some pulses are skipped to increase efficiency while remaining in regulation. At light loads, a zero-crossing comparator truncates the low-side switch on time when the inductor current becomes negative. In this condition, the device works in discontinuous conduction mode (DCM). The threshold between CCM and DCM is approximately I LOAD (skip) = SWIN OUTOUTIN f V L V V V )( (4) There is a first-order dependency of this threshold on the internally set on-time scale factor indicated in Equation 3. For higher load currents, the inductor current does not cross zero threshold. The device switches to the continuous conduction mode, and the frequency is fixed to the nominal value.
connected to the input of the converter. deep discharge of the battery supply. Figure 46. Internal Block Diagram
Rev. C | Page 16 of 24 APPLICATIONS INFORMATION The external component selection for the ADP2102 applications circuit, as shown in Figure 1, is driven by the load requirement and begins with the selection of Inductor L. Once the inductor is chosen, CIN and COUT can be selected. INDUCTOR SELECTION The high switching frequency of the ADP2102 allows for minimal output voltage ripple, even with small inductors. Inductor sizing is a trade-off between efficiency and transient response. A small inductor leads to a larger inductor current ripple that provides excellent transient response but degrades efficiency. Due to the high switching frequency of the ADP2102, multilayer ceramic inductors can be used for an overall smaller solution size. Shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (EMI). As a guideline, the inductor peak-to-peak current ripple, ΔIL, is typically set to 1/3 of the maximum load current for optimal transient response and efficiency. ΔIL = LfV VVV SWIN OUTINOUT −× )( ≈ 3 )(MAXLOADI (7) LIDEAL = )(3.0 MAXLOADSWIN OUTINOUT IfV VVV ××× where fSW is the switching frequency. Finally, it is important that the inductor be capable of handling the maximum peak inductor current, IPK, determined by the following equation: IPK = ILOAD(MAX) + ΔIL/2 (8) The dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Table 5 shows some typical surface mount inductors that work well in ADP2102 applications. INPUT CAPACITOR SELECTION The input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. The rms input current flowing through the input capacitor is, at maximum, IOUT/2. Select an input capacitor capable of with- standing the rms input current for the maximum load current in the application to be used. Irms = IOUTMAX × IN OUTINOUT V VVV )( −× (9) The input capacitor reduces input voltage ripple caused by the switch currents on the PVIN pin. Place the input capacitor as close as possible to the PVIN pin. In principle, different types of capacitors can be considered, but for battery-powered applications, the best choice is a multilayer ceramic capacitor, due to its small size and equivalent series resistance (ESR). It is recommended that the PVIN pin be bypassed with a 2.2 µF or larger ceramic input capacitor. The size of the input capacitor can be increased without any limit for better input voltage filtering. X5R or X7R dielectrics are recommended, with a voltage rating of 6.3 V or 10 V . Y5U and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. In applications with greater than 300 mA load current, a ceramic bypass capacitor of 0.01 µF is recommended on the AVIN pin for better regulation performance. OUTPUT CAPACITOR SELECTION The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. For a given loop crossover frequency (the frequency at which the loop gain drops to 0 dB), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. The ADP2102 is designed to operate with small ceramic capacitors that have low ESR and equivalent series inductance (ESL) and are thus comfortably able to meet tight output voltage ripple specifications. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V . Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. When choosing output capacitors, it is also important to account for the loss of capacitance due to output voltage dc bias. If ceramic output capacitors are used, the capacitor rms ripple current rating should always meet the application requirements. The rms ripple current is calculated as I rms(COUT) = 1 × MAXINSW OUTMAXINOUT VfL VVV _ )( −× (10) At nominal load currents, the converter operates in forced continuous conduction mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor. ΔV OUT = ΔIL × (ESR + 1/ (8 × COUT × fSW)) (11) The largest voltage ripple occurs at the highest input voltage, VIN. At light load currents, the converter operates in power save mode, and the output voltage ripple is dependent on the output capacitor value. The ADP2102 control loop is stable with a ceramic output capacitor of 2.2 µ F. For better transient performance, a 10 µF ceramic capacitor is recommended at the output. Table 6 lists input and output MLCC capacitors recommended for ADP2102 applications.
degrades the efficiency at very light loads. VFB is the feedback voltage, 0.8 V. R1 is the feedback resistor from VOUT to FB. R2 is the feedback resistor from FB to GND. voltage divider internally, reducing the external circuitry required. voltage as close as possible to the load. ADP2102 adjustable output voltage options, see Table 7. Table 7. Configurations for V Efficiency is defined as the ratio of output power to input power. The high efficiency of the ADP2102 has two distinct advantages. power, extending battery life in portable applications.
- Power switch conduction losses
- Inductor losses
- Switching losses
- Transition losses Power Switch Conduction Losses Power switch conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (R DS(ON)) associated with them. The amount of power loss can be approxi- mated by PSW_COND = (RDS (ON)_P × D + RDS (ON)_N × (1 − D)) × IOUT2 (15) where D = VOUT/VIN. The internal resistance of the power switches increases with temperature but decreases with higher input voltage. Figure 24 in the Typical Performance Characteristics section shows the change in RDS (ON) vs. input voltage, and Figure 25 shows the change in RDS (ON) vs. temperature for both power devices.
Rev. C | Page 20 of 24 Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (DCR) associated with it. Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the ADP2102 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. The total amount of inductor power loss can be calculated by PL = DCR × IOUT2 + Core Losses (16) Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge ΔQ from the input supply to the gate and then from the gate to ground. The amount of power loss can be calculated by PSW = (CGATE_P + CGATE_N) × VIN2 × fSW (17) where: CGATE_P is the gate capacitance of the internal high-side switch. CGATE_N is the gate capacitance of the internal low-side switch. fSW is the switching frequency. Transition Losses Transition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of an LX node transition, the power switch provides all the inductor current. The source to drain voltage of the power switch is half the input voltage, resulting in power loss. Transition losses increase with load current and input voltage and occur twice for each switching cycle. The amount of power loss can be calculated by PTRAN = VIN/2 × IOUT × (tR + tF) × fSW (18) where: tR is the rise time of the LX node. tF is the fall time of the LX node. THERMAL CONSIDERATIONS In most applications, the ADP2102 does not dissipate a lot of heat, due to its high efficiency. However, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junction temperature of 125°C. Once the junction temperature exceeds 150°C, the converter goes into thermal shutdown. It recovers only after the junction temperature has decreased to below 135°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application solution is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, shown in the following equation: T J = TA + TR (19) where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation in it. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is defined as the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = θJA × PD (20) where: TR is the rise in temperature of the package. θJA is the thermal resistance from the junction of the die to the ambient temperature of the package. PD is the power dissipation in the package. DESIGN EXAMPLE The calculations in this section provide only a rough estimate and are no substitute for bench evaluation. Consider an application in which the ADP2102 is used to step down from 3.6 V to 1.8 V with an input voltage range of 2.7 V to 4.2 V. VOUT = 1.8 V at 600 mA Pulsed Load = 300 mA VIN = 2.7 V to 4.2 V (3.6 V typical) fSW = 3 MHz (typical) TA = 85°C Inductor ΔIL = LfV VVV SWIN OUTINOUT −× )( ≈ 3 )(MAXLOADI = 0.6/3 = 200 mA L = )(3.0 )/1( MAXLOADSW INMAXOUTOUT If VVV −× = )6.03.0103( )2.4/8.11(8.1 6 ××× −× = 1.90 µH Choose a 2.2 µH inductor for this application. IPK = ILOAD(MAX) + ΔIL/2 = 0.6 + 0.2/2 = 0.7 A PL = IOUTMAX2 × DCR = (0.6 A)2 × 0.08 Ω (FDK MIPF2520D) = 29 mW
Rev. C | Page 21 of 24 Output Capacitor For transient applications, assume a droop of 0.1 V . Typically, it takes two to three cycles for the output to settle from a load transient because the capacitor alone supplies the load current until the loop responds. Under these conditions, a minimum required output capacitance is calculated as follows: COUT_MIN = 3 × SWDROOP LOAD f V I = 610 3 1 . 0 3 . 0 3 = 3 μF Choose a 4.7 μF capacitor for this application. For an instantaneous step decrease in load current, the output capacitor required to limit the output voltage overshoot (VOS) during a full load to no load transient must be determined. This transient requires the excess energy stored in the output inductor to be absorbed by the output capacitor with a limited overshoot in the output voltage. Assuming an overshoot of 50 mV for a full load transient, COUT = 22 )( OUTOSOUT OUT V V V I L = 22 ) 6 . 0 ( H 2 . 2 = 4.33 μF Choose a 4.7 μF capacitor for this application. Irms = 3 2 1 × MAX INSW OUTMAX INOUT V f L VV V _ )( = 3 2 1 × 2 . 4 10 3 10 2 . 2 ) 8 . 1 2 . 4 ( 8 . 1 66 = 45 mA rms PCOUT = Irms2 × ESR = (0.045)2 × 0.005 = 10.12 μW Input Capacitor Assume an input ripple of 27 mV based on 1% of VIN_MIN. For ceramic capacitors, the typical ESR is from 5 mΩ to 15 mΩ. CIN = SWOUTIN fESR I V 4 )/ ( 1 = 610 3 4 ) 005 . 0 6 . 0 / 027 . 0 ( = 2.2 μF Irms = IOUT/2 = 0.3 A rms PCIN = Irms2 × ESR = (0.3)2 × 0.005 = 450 μW Losses PSW_COND = (RDS (ON)_P × D + RDS (ON)_N × (1 − D)) × IOUT2 = PTRAN = (VIN/2) × IOUT × (tR + tF) × fSW = PSW = (CGATE_P + CGATE_N) × VIN2 × fSW = (200 pF) × PL = DCR × IOUT2 = 0.08 × (0.6)2 = 28.8 mW PLOSS = PSW_COND + PTRAN + PSW + PL = 82 mW + 32.4 mW + 7.8 mW + 28.8 mW = 151 mW TJMAX = TA + θJA PLOSS = 85°C + 54°C/W × 151 mW = 93.15°C PLOSS is well below the junction temperature maximum of 125°C.
Rev. C | Page 24 of 24 OUTLINE DIMENSIONS TOP VIEW 0.30 0.25 0.20 BOTTOM VIEW PIN 1 INDEX AREA SEATING PLANE 0.80 0.75 0.70 1.55 1.45 1.35 1.84 1.74 1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
3.10 3.00 SQ 2.90 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.COPLANARITY 0.08 0.50 0.40 0.30 COMPLIANT TOJEDEC STANDARDS MO-229-WEED 12-07-2010-A PIN 1 INDICATOR (R 0.15) Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP]
Description
ADP2102YCPZ-1.2-R7 600 −40°C to +85°C 1.2 V 8-Lead LFCSP CP-8-13 L5V ADP2102YCPZ-1.37R7 600 −40°C to +85°C 1.375 V 8-Lead LFCSP CP-8-13 L5X ADP2102YCPZ-3-R7 600 −40°C to +85°C 1.5 V to 1.875 V 8-Lead LFCSP CP-8-13 L6M ADP2102YCPZ-4-R7 600 −40°C to +85°C 2.5 V to 3.3 V 8-Lead LFCSP CP-8-13 L6N ADP2102-1.2-EVALZ Fixed Output 1.2 V Evaluation Board ADP2102-3-EVALZ Adjustable Output 1.5 V to1.875 V Evaluation Board ADP2102-4-EVALZ Adjustable Output 2.5 V to 3.3 V Evaluation Board 1 Z = RoHS Compliant Part. 3 Operating junction temperature range: −40°C to +125°C. ©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06631-0-7/16(C)