ADP1074ACCZ-RL

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Isolated, Synchronous Forward Controller with Active Clamp and iCoupler Data Sheet ADP1074 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2017–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Current mode controller for active clamp forward topology Integrated 5 kV (wide body SOIC package) or 3.0 kV (LGA package) rated dielectric isolation voltage with Analog Devices, Inc., patented iCoupler technology Wide voltage supply range Primary VIN: up to 60 V Secondary VDD2: up to 36 V Integrated 1 A primary side MOSFET driver for power switch and active clamp reset switch Integrated 1 A secondary side MOSFET drivers for synchronous rectification Integrated error amplifier and <1% accurate reference voltage Programmable slope compensation Programmable frequency range: 50 kHz to 600 kHz typical Frequency synchronization Programmable maximum duty cycle limit Programmable soft start Smooth soft start from precharged load Programmable dead time Power saving light load mode using MODE pin Protection features such as short circuit, output overvoltage, and overtemperature protection Cycle-by-cycle input overcurrent protection Precision enable UVLO with hysteresis PGOOD pin for system flagging Tracking function from secondary side Remote (secondary side) shutdown/reset function Safety and regulatory approvals (pending) UL recognition

5000 V rms for 1 minute per UL 1577 (for wide body

SOIC package)

3000 V rms for 1 minute per UL 1577 (for LGA package)

CSA component acceptance notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V IORM = 849 V peak (for wide body SOIC package) VIORM = 560 V peak (for LGA package) CQC certification per GB4943.1-2011 Available in 24-lead SOIC_W package and 24-terminal LGA package AEC-Q100 Qualified for Automotive Applications

APPLICATIONS

Isolated dc-to-dc power conversion Intermediate bus voltage generation Telecom, industrial Base station and antenna RF power Small cell PoE powered device Enterprise switches/routers Core/edge/metro/optical routing Power modules SIMPLIFIED BLOCK DIAGRAM ACTIVE CLAMP FORWARD BIAS WDG 12VDC/8AINPUT SYNCHRONOUS RECTIFIER OPTIONAL START-UP CIRCUITRY ADP1074 15627-001 Figure 1.

Rev. D | Page 2 of 32 TABLE OF CONTENTS DIN V VDE V 0884-10 (VDE V 0884-10) Insulation DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

REVISION HISTORY

6/2020—Rev. C to Rev. D 4/2020—Rev. B to Rev. C 8/2018—Rev. A to Rev. B Changes to Input/Output Current-Limit Protection Section .... 19 8/2018—Rev. 0 to Rev. A Added DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Section, Table 5, and Figure 2; Renumbered Added DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Changes to Input/Output Current Limit Protection Section .. 19 10/2017—Revision 0: Initial Version

synchronous forward converter at heavy loads. synchronization, and slope compensation. programmable light load mode setting. iCouplers using a proprietary transmission scheme. and power saving light load mode (LLM). Table 1. Related Products representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. 2 Some packages are available in 500 unit reels through designated sales channels. These versions feature the #TRMPBF suffix. 3 Contact the factory for devices specified with wider operating temperature ranges. The temperature grade is identified by a label on the shipping container.

Rev. D | Page 4 of 32 SPECIFICATIONS VIN = 24 V, VDD2 = 12 V, TJ = −40°C to +125°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY (PRIMARY) Supply Voltage VIN 4.7 μF capacitor from VIN to PGND1, 1 μF capacitor from VREG1 to PGND1 4.7 24 60 V Quiescent Supply Current I VIN VIN > VIN UVLO, NGATE and PGATE unloaded At 100 kHz 5.3 mA At 300 kHz 5.8 mA At 600 kHz 6.8 mA VIN > VIN UVLO, NGATE and PGATE loaded with 2.2 nF and 410 pF, respectively At 100 kHz 7.5 mA At 300 kHz 12 mA At 600 kHz 19.5 mA VIN Shutdown Current EN pin voltage (VEN) < 1.2 V, VREG1 = 0 V, VIN = 60 V 55 μA (VIN + VREG1) Start-Up Current I VIN_STARTUP VEN < 1.2 V, VREG1 = 12 V, VIN = 12 V 160 μA VIN UVLO VIN rising 4.7 V VIN falling 4.0 V UVLO Hysteresis 0.19 V Time from EN High to PGATE Output Switching V EN > 1.2 V, 1 μF capacitor on VREG1 1 ms Time from EN Low to SR1/SR2 Output Stops Switching V EN < 1.0 V, 1 μF capacitor on VREG1 1 μs SUPPLY (SECONDARY) Supply Voltage VDD2 4.7 μF capacitor from VDD2 to PGND2, 1 μF capacitor from VREG2 to PGND2 4.5 12 36 V Quiescent Supply Current I DD2 SR1 and SR2 unloaded At 100 kHz 6.5 mA At 300 kHz 6.7 mA At 600 kHz 7 mA I DD2 SR1 and SR2 loaded with 2.2 nF At 100 kHz 8.3 mA At 300 kHz 12 mA At 600 kHz 18 mA VDD2 UVLO Threshold VDD2 rising 3.55 V VDD2 falling 3.0 V UVLO Hysteresis 0.145 V Secondary UVLO Hiccup Time 200 ms OSCILLATOR Switching Frequency (fS) RT resistance (RRT) = 480 kΩ (±1%) 50 − 10% 50 50 + 10% kHz RRT = 240 kΩ (±1%) 100 − 10% 100 100 + 10% kHz RRT = 120 kΩ (±1%) 200 − 10% 200 200 + 10% kHz RRT = 80 kΩ (±1%) 300 − 10% 300 300 + 10% kHz RRT = 60 kΩ (±1%) 400 − 10% 400 400 + 10% kHz RRT = 40 kΩ (±1%) 600 − 10% 600 600 + 10% kHz VREG1 PIN VREG1 Voltage Clamp VREG1 current (IVREG1) = 3 mA, VEN < 1.2 V 13.5 14.3 15.2 V VREG1 Clamp Series Resistance VREG1 forced current of 5 mA and 15 mA 16 Ω

Rev. D | Page 5 of 32 Parameter Symbol Test Conditions/Comments Min Typ Max Unit GATE DRIVERS (PRIMARY) NGATE and PGATE High Voltage I VREG1 = 20 mA, VIN > 9 V 7.8 8 8.2 V Gate Short-Circuit Peak Current1 8 V on VREG1 1.0 A Rise Time 10% to 90% NGATE CNGATE = 2.2 nF 18 ns PGATE CPGATE = 410 pF 8 ns Fall Time 90% to 10% NGATE CNGATE = 2.2 nF 16 ns PGATE CPGATE = 410 pF 7 ns Source Resistance RON_SOURCE Source 100 mA NGATE 4 Ω PGATE 6.5 Ω Sink Resistance RON_SINK Sink 100 mA NGATE 3 Ω PGATE 3.5 Ω NGATE Maximum Duty Cycle D MAX Divider bottom resistor (R BOT) = 0 Ω 45 50 55 % Divider top resistor (RTOP) = RBOT, 1% resistors 75 % NGATE Minimum On Time Includes propagation delay and CS comparator blanking time 170 ns SRx DRIVERS (SECONDARY) SR1 and SR2 High Voltage IVREG2 = 15 mA, VDD2 > 5.5 V 4.9 5 5.1 V Gate Short-Circuit Peak Current1 5 V on VREG2 1.0 A SRx Time CSRx = 2.2 nF Rise 10% to 90% 14 ns Fall 90% to 10% 11 ns Minimum On Includes blanking time 230 ns SRx Resistance Source RON_SR_SOURCE Source 100 mA 3.5 Ω Sink RON_SR_SINK Sink 100 mA 2 Ω DELAYS Gate Delay (SR1 Rising to NGATE Rising) 35 ns Delay Between NGATE Falling Edge and SR1 Falling Edge iCoupler delay 21 ns SR DEAD TIME (PGATE RISING TO SR2 FALLING) Resistor (±5%) at NGATE Dead time resistor (RDT) = 10 kΩ 154 ns RDT = 22 kΩ 109 ns RDT = 47 kΩ 72 ns RDT is open 42 ns SR1 and SR2 Dead Time Dead time between SR1 and SR2 25 ns CURRENT-LIMIT SENSE (PRIMARY) CS Limit Threshold VCS_LIM Over current sense limit threshold 120 mV CS Leading Edge Blanking Time 150 ns Current Source di/dt for Slope Compensation Switching period (t S) = 1/fS 20 μA per tS

Rev. D | Page 6 of 32 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Overcurrent Protection (OCP) Comparator Delay 40 ns Time in OCP Before Entering Hiccup Mode 1.5 ms OCP Hiccup Time See Input/Output Current-Limit Protection section 40 ms FB PIN AND ERROR AMPLIFIER Temperature Coefficient 76 ppm/°C FB Input Bias Current −100 +1 +100 nA Transconductance gm 230 250 270 μA/V Output Current Clamp Minimum −57 μA Maximum 43 μA COMP Clamp Voltage Minimum 20 μA sinking current from COMP pin 0.7 V Maximum 20 μA sourcing current to COMP pin 2.52 V Open-Loop Gain 80 dB Output Shunt Resistance 5 GΩ Gain Bandwidth Product 1 MHz PRECISION ENABLE THRESHOLD EN Threshold VEN EN rising 1.14 1.2 1.26 V EN Hysteresis VEN < 1.2 V 4 μA VEN > 1.2 V 1 μA EN Hysteresis Current 3 μA MODE PIN Light Load Mode Current Source Connect a resistor from MODE to AGND2 6 6.5 7 μA Hysteresis 24 40 60 mV TEMPERATURE Thermal Shutdown 155 °C Hysteresis −15 °C SOFT START SS1 AND SS2 PINS Primary Side SS1 Current Source During soft start only 9.1 μA Secondary Side SS2 Current Source During soft start only, post handover 20 μA SS2 Discharging Current During a fault condition or soft stop 30 μA SYNC PIN Synchronization Range 100 600 kHz Input Pulse Width 100 ns Number of Cycles Before Synchronization

7 Cycles

Low 0.4 V High 3 V Leakage Current 1 μA iCOUPLER DELAY COMP Signal Delay Through iCoupler 600 ns

Rev. D | Page 7 of 32 Parameter Symbol Test Conditions/Comments Min Typ Max Unit FB, OVP, AND PGOOD THRESHOLDS Overvoltage (OV) threshold for PGOOD to toggle for FB and OVP pin 1.3 1.36 1.42 V FB Pin OV Hysteresis 36 mV OVP Pin Hysteresis 36 mV FB Pin UV Threshold Undervoltage (UV) threshold for PGOOD to toggle 1.04 1.11 1.16 V FB Pin UV Hysteresis 36 mV OVP Comparator Delay (Includes iCoupler Delay) 320 ns Time from Fault Condition to PGOOD Toggling OVP pin fault to PGOOD toggling 90 ns FB pin OV/UV to PGOOD toggling 5 μs OVP Pin Leakage Current 1 μA PGOOD Pin Leakage Current 1 μA OVP Hiccup Time in OVP before entering OVP hiccup mode 200 μs Hiccup time triggered by OVP event 200 ms 1 Short-circuit duration less than 1 μs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit WIDE BODY SOIC iCoupler Rated Dielectric Insulation Voltage 1 minute duration 5 kV Minimum External Air Gap (Clearance) Measured from input terminals to output terminals, shortest distance through air 7.6 mm Minimum External Air Gap (Creepage) Measured from input terminals to output terminals, shortest distance path along body 7.6 mm Minimum Internal Gap (Internal Clearance) Insulation distance through insulation 0.030 mm Tracking Resistance (Comparative Tracking Index) CTI >400 V Isolation Group Material Group II (DIN VDE 0110, 1/89, Table 1) LAND GRID ARRAY (LGA) iCoupler Rated Dielectric Insulation Voltage 1 minute duration 2.5 kV Minimum External Air Gap (Clearance) Measured from input terminals to output terminals, shortest distance through air 4 mm Minimum External Air Gap (Creepage) Measured from input terminals to output terminals, shortest distance path along body 4 mm Minimum Internal Gap (Internal Clearance) Insulation distance through insulation 0.030 mm Tracking Resistance (Comparative Tracking Index) CTI >400 V Isolation Group Material Group I (D IN VDE 0110, 1/89, Table 1)

isolation waveforms and insulation levels. Table 4. Regulatory Information for Wide Body SOIC Package

849 V peak,

8000 V peak

238 V rms (325 V peak)

1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec. 2 In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥1592 V peak for 1 sec (partial discharge detection limit = 5 pC). Note that the asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. Table 5. Regulatory Information for LGA Package

4242 V peak

1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec. 2 In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥1059 V peak for 1 sec (partial discharge detection limit = 5 pC). Note that the asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.

circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 6. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics for Wide Body SOIC Package Figure 2. Thermal Derative Curve, Dependence of Safety Limiting Values with Ambient Temperature per DINV VDE V 0884-10

circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 7. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics for LGA Package Figure 3. Thermal Derative Curve, Dependence of Safety Limiting Values with Ambient Temperature per DINV VDE V 0884-10

operational section of this specification is not implied. extended periods may affect product reliability. PCB thermal design is required. Table 9. Thermal Resistance

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

Table 10. Maximum Continuous Working Voltage, Wide

1 Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details. Table 11. Maximum Continuous Working Voltage, LGA1 barrier. See the Insulation Lifetime section for more details.

Rev. D | Page 13 of 32 Pin No. Mnemonic Description 16 COMP Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. This pin is referenced to AGND2. 17 FB Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the nominal voltage, when the power supply is in regulation, is 1.2 V. Reference this pin to AGND2. 18 OVP Output Overvoltage Protection (OVP). The OVP threshold is set at 1.36 V. Connect a resistive divider from OVP to the output and AGND2. 19 VDD2 Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power supply for a self driven configuration. Connect a 4.7 μF capacitor from VDD2 to AGND2. The size of this capacitor can be reduced if the input voltage to VDD2 is guaranteed stable. 20 VREG2 5 V Regulated Low Dropout (LDO) Output for Internal Bias and Powering of the Drivers of the Synchronous Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 μF capacitor from VREG2 to AGND2. 21 AGND2 Analog Ground on the Secondary Side. Star connect AGND2 to PGND2. Use AGND2 for differential sensing of the output voltage between the FB pin and AGND2. 22 PGND2 Power Ground on the Secondary Side. Star connect PGND2 to AGND2. 23 SR2 MOSFET Driver Output 2 for the Synchronous Rectif ier MOSFET. This PWM controls the freewheeling switch. 24 SR1 MOSFET Driver Output 1 for the Synchronous Rect ifier MOSFET. This PWM is in phase with NGATE.

Rev. D | Page 16 of 32 THEORY OF OPERATION The ADP1074 is a current mode, fixed frequency, active clamp, synchronous forward controller designed for isolated dc to dc power supplies. Analog Devices proprietary iCouplers are integrated in the ADP1074 to eliminate the bulky signal trans- formers and optocouplers that transmit signals over the isolation boundary. Integrating the iCouplers reduces system design complexity, cost, and component count and improves overall system reliability. With the integrated isolators and MOSFET drivers on both the primary and the secondary side, the ADP1074 offers a compact system level design and yields a higher efficiency than a nonsynchronous forward converter at heavy loads. Traditionally in a forward or flyback converter, a discrete opto- coupler is used in the feedback path to transmit the signal from the secondary to the primary side, and an external transformer is used for transmitting the PWM signal from the primary to the secondary side for synchronous rectification. However, the current transfer ratio (CTR) of the optocouplers degrades over time and over temperature and so the optocoupler must be replaced every five to ten years, depending on the manufacturing quality and optocoupler grade that determines the initial CTR. The ADP1074 eliminates the use of optocouplers and signal transformers, thus reducing system cost, PCB area, and complexity while improving system reliability, without the issue of CTR degradation of the optocouplers. The ADP1074 controller offers a complete solution for an isolated dc to dc power supply by integrating the 5 kV isolators and the primary and secondary control circuitries in one package. The PWM controls are performed on the primary side by sensing the input peak current cycle by cycle with a sense resistor at the source of the main switching MOSFET. The output of the converter is sensed by the secondary circuitry, which sends the feedback and PWM signals to the primary side via the 5 kV integrated isolators for a complete control loop solution. The primary circuitry in the ADP1074 includes an 8 V LDO, input current sensing, bias circuit, and MOSFET drivers including an active clamp reset driver, slope compensation, external frequency synchronization, PWM generator, and a programmable maximum duty cycle setting. The primary side also has pins for differential sensing of the current sense signal. The secondary circuitry includes the feedback compensation, a

5 V LDO regulator, an internal reference, two MOSFET drivers for

synchronous rectification, and a dedicated pin for overvoltage protection. Additionally, the secondary side features differential output voltage sensing and power good pins, and a program- mable light load mode setting. The integrated iCouplers carry out the communications between the primary and secondary sides by transmitting the feedback signal and the PWMs over the isolation barrier. The feedback signal and timing of synchronous rectifier PWMs are transmitted between the primary and the secondary sides, or between the secondary and primary sides, through the iCouplers using a proprietary transmission scheme. The ADP1074 also offers features such as input current protection, UVLO, precision enable with adjustable hysteresis, OTP, LLM, and tracking.

MOSFET drivers at the NGATE and PGATE pins. 5 V, the LDO regulator operates in dropout mode. with an auxiliary voltage in the 8 V to 12 V range.

4.5 V), the ADP1074 is enabled when the voltage at EN rises above

VEN ≥ 1.2 V and obtain the desired hysteresis. and becomes inactive when VEN is above the EN threshold. toggles the EN pin when the input voltage hovers at the threshold. Figure 14. Precision EN with Adjustable Hysteresis Start Procedure section for more details. directly from the output voltage of the power supply.

1.5 V correspond to a peak current of 0 A and 120 mV/R

Rev. D | Page 19 of 32 starts charging only when the primary current limit exceeds the load current requirement. The rate at which the SS1 pin voltage rises to the maximum current limit is given by dt = CSS1 × 1.5/(9.1 μA) The handshaking process is as follows. When VDD2 reaches the UVLO of approximately 3.5 V, the internal circuitry on the secondary side is activated and the ADP1074 initiates the following process: 1. The ADP1074 makes the voltage on the SS2 pin equal to the value on the FB pin, with an SS2 pin current, at ten times the nominal current source of 20 μA on the SS2 pin. 2. Simultaneously, the current limit on the primary (which is the voltage on SS1) is transferred over to the secondary side, and the voltage on the COMP pin is made equal to the instantaneous SS1 voltage ± 100 mV. There is a timeout for this process, which is 1.5 ms after the VDD2 UVLO threshold is crossed. When this process is satisfied, the transmission of the COMP signal occurs from the secondary to the primary side. The ADP1074 transmits the COMP signal by continuously sampling the analog signal at the COMP pin. The sampled value is then transmitted using a proprietary scheme to the primary side where the instantaneous value of the CS pin is compared to the COMP level to determine the falling edge of the NGATE pulse. The COMP signal is, therefore, a representation of the primary current limit. After COMP transmission begins, the primary side receives the signal and control is completely handed over to the secondary side when either the received level of COMP on the primary side is within ±100 mV, or up to 128 switching periods (typically 8) have passed, starting from the first pulse being transmitted to the primary side. Then, the control is handed over to the secondary side and the closed-loop soft start begins, where the SS2 capacitor is charged at a nominal rate of 20 μA. The output voltage then rises to the regulation voltage based on the SS2 pin voltage. The voltage on the SS2 pin continues to rise to 1.2 V, that is, the steady state voltage on the FB pin. At this stage, the power supply is in regulation, and the output voltage is at its target value. At the end of the soft start process, the voltage on the SS2 pin continues to rise to approximately 1.4 V. The instant that the handover takes place, SS1 is discharged to 0 V. In steady state, the FB pin (that is, the reference voltage) is 1.2 V. The SR1 and SR2 synchronous drivers begin to pulse after VDD2 crosses the UVLO threshold. If the voltage at the VDD2 pin is greater than the UVLO voltage, such as a soft start from the precharged output, or if the VDD2 pin is powered by an external supply, the secondary side assumes control from the moment the EN pin is enabled, and only SS2 is used for the soft start procedure. When initiating a soft start from the precharged output, the SS2 pin tracks the FB pin and then initiates a soft start. This process eliminates any glitches in the output voltage. When soft starting into a precharged output, the SRx gates are prevented from turning on until the SS2 voltage has reached the precharged voltage at the FB pin. This soft start scheme prevents the output from being discharged, and it prevents reverse current. Under abnormal situations, such as a shorted load or a transient condition on the load during the soft start process, FB may not be able to track SS2 accurately. If this occurs before the VDD2 UVLO threshold is crossed, SS1 is in control. If it occurs after the VDD2 UVLO threshold is crossed, SS2 tracks the FB pin and then continues with the soft start process until the regulation voltage is reached. In all conditions, control is handed over to the secondary if FB ≥ 1.2 V. When the secondary VDD2 is directly powered by the output of the converter, the minimum output voltage required is higher than the secondary UVLO voltage. For output voltages less than the secondary UVLO voltage, a third winding is needed to generate an auxiliary voltage to power the secondary side circuitry. Alternately, in most cases, a diode resistor capacitor combination from the switch node can provide the voltage to VDD2. OUTPUT VOLTAGE SENSING AND FEEDBACK The output voltage of the converter is set by a resistive divider to the FB pin. The resistive divider must be set in a manner such that the voltage at the FB pin is 1.2 V in steady state. The output voltage must be differentially sensed using the FB pin and the AGND2 pin. LOOP COMPENSATION AND STEADY STATE OPERATION The FB pin feeds into the negative terminal of a transconductance amplifier (or gm amplifier) with a gain of approximately 250 μA/V. The positive input terminal of the gm amplifier is connected to SS2, which provides the reference setpoint voltage. The output of the gm amplifier is connected to the COMP pin. The voltage on the COMP pin is representative of the current peak limit required to sustain regulation. This pin is continuously sampled, and the signal is transmitted to the primary side, where it is compared to the sensed primary current using a comparator. When the comparator trips, it causes NGATE to terminate. Typically, an RC network in series is connected between the COMP pin and AGND2 for compensation. A high frequency pole in the form of a capacitor can also be added in parallel to the RC network. The output of the gm amplifier is clamped to a minimum and maximum current of approximately −57 μA and +43 μA, respectively.

Rev. D | Page 20 of 32 The COMP node is clamped to a lower and higher level of approximately 0.7 V and 2.52 V, respectively. This is representative of the CS range from 0 mV to 120 mV. SLOPE COMPENSATION For a peak current mode controller with duty cycle higher than 50%, slope compensation is necessary for a stable operation. To set up an external compensation in the ADP1074, connect the external R RAMP resistor (see Figure 25) between CS and the current sense resistor, RSENSE, to set up the slope voltage ramp for the control signal. It is important to sense the signal differentially. See the Layout Guidelines section for more details. An internal ramp current starts from 0 μA at the minimum duty cycle (that is, the beginning of the switching period) and increases linearly toward a maximum of 20 μA at the end of the switching period. The slope of the voltage ramp is the ramp current times R RAMP. RRAMP is sized using the following equation: 20 μA OUT SENSE RAMP S VN 2 RRk t LN 1  where: k = 0.5 for nominal cases and k = 1 for deadbeat control. VOUT is the desired output voltage. L is the output inductor. N1 and N2 are the primary and secondary turns of the transformer. t S is the switching period. INPUT/OUTPUT CURRENT-LIMIT PROTECTION There is no direct current-limit sensing circuit on the secondary; the output current limit is indirectly limited by the cycle-by-cycle primary side current limit of 120 mV on the CS pin. The input peak current limit is set by connecting a sense resistor, RSENSE, from the source of the main MOSFET to PGND1 (see Figure 25), and the sensed voltage appears at the CS pin. To generate the slope-comp ramp, insert the slope compensation resistor, RRAMP, between CS and RSENSE. The CS current limit, VCSLIM, is internally set to 120 mV. Calculate the RSENSE value by 20 μACSLIM RAMP SENSE PKPRI VRR I  where: VCSLIM is the CS current limit. IPKPRI is the primary peak current. When the sensed input peak current is above the CS limit threshold, the controller operates in the cycle-by-cycle constant current-limit mode for 1.5 ms. Then the controller immediately shuts down the primary and secondary drivers. The controller then goes into hiccup mode for the next 40 ms and restarts the soft start sequence after this timeout period. The slope ramp can affect the accuracy of the current-limit threshold because the voltage drop across R RAMP contributes to the inaccuracy of the peak current limit. For instance, if the added slope ramp voltage is 20% of the current-limit threshold, the actual input peak current limit can be off by as much as 20% depending on where the peak current-limit threshold is tripped during the on cycle. In the event of an output short circuit, the controller treats this condition as an overcurrent event and enters the 40 ms hiccup mode. Under certain conditions, the ADP1074 exits OCP hiccup mode. In these conditions, the COMP pin is at the maximum clamp level, but the device does not enter hiccup mode. However, it is guaranteed that the PWMs are terminated whenever the CS maximum threshold is reached. The condition under which the ADP1074 skips entering hiccup mode is when VDD2 is powered through an auxiliary winding and an output short circuit occurs that results in the FB pin having a voltage that is <300 mV. This event is more prominent at high temperatures (>85°C), and can be exacerbated at higher temperatures. The root cause of the device exiting hiccup mode is due to the effect that the OCP hiccup mode feature has on the SS2 pin. During OCP recovery, the SS2 pin tracks the FB pin and attempts a soft start from the precharge sequence. During the time when SS2 tracks the FB pin, the SS2 pin voltage can be less than the FB pin for a short interval, which causes the COMP pin (output of the gm amplifier) to momentarily dip below the maximum COMP pin clamp level. This event means that the current limit required for the next few switching periods is less than the maxi- mum threshold and puts the device out of hiccup mode because the ADP1074 fails to register 1.25 ms worth of consecutive overcurrent cycles. The following scenarios guarantee OCP hiccup mode based on the configuration of the VDD2 power supply: 1. When VDD2 is powered directly from the output voltage, if a short circuit occurs on the output terminals of the load after steady state regulation is achieved, the voltage of the VDD2 pin is less than the UVLO, and the device enters hiccup mode for 200 ms, similar to the hiccup time described in the Remote System Reset section. 2. When VDD2 is powered through auxiliary winding or another configuration, when a short circuit occurs on the output terminals, the auxiliary winding is not shorted and maintains a positive voltage above the UVLO threshold of the VDD2 pin. To enter hiccup mode, it is recommended to use the circuit shown in Figure 15. The circuit operates as follows: when the output voltage goes low due to a short circuit, the D1 diode turns on, which pulls the base of the bipolar junction transistor low, shutting off VDD2. The system then enters hiccup mode, as described in the Remote System Reset section.

the SRx drivers and all internal circuits on the secondary side. to supply VDD2 with an auxiliary power supply greater than 5 V. as the ADP3624 or the ADP3654. ringing at the CS pin at the start of the switching period. Figure 17. Gate Delay and SR Dead Time Settings necessary to have a delay time between SR2 and NGATE. edge turn off simultaneously with an iCoupler delay. optimizes the dynamic performance of the output response.

Rev. D | Page 24 of 32 OCP/FEEDBACK RECOVERY During steady state, the FB pin is at 1.2 V. At this time, the SS2 pin voltage is 1.4 V. Under abnormal situations, such as an overload condition, the output voltage can dip severely. In such an event, the current limit is at the maximum level, and the COMP pin voltage is at its clamp level. If the two conditions of the COMP pin voltage being clamped and V FB < (1.2 V – 100 mV) are satisfied, the controller discharges the SS2 pin using a fast current sink (200 μA) to make the SS2 pin equal to the FB pin. The controller then attempts to perform a soft start from this precharged condition, that is, from the last known value of the output voltage. This process is how the OCP/feedback recovery feature operates. However, if at any time the voltage on the COMP pin is above the maximum clamp voltage for a period greater than 1.5 ms, the system enters hiccup mode. During the soft start from precharge, the output voltage rises at the same rate as determined by the capacitor on the SS2 pin. If, however, there is a detrimental fault in the power stage that prevents the rise of the output voltage, V FB does not track SS2, and when SS2 > (VFB + 100 mV), the COMP pin voltage increases to the clamp level, and the system again enters OCP/feedback recovery mode. OUTPUT VOLTAGE TRACKING The ADP1074 offers a tracking feature. During steady state, the FB pin is at 1.2 V. At this time, the SS2 pin voltage is at 1.4 V. Using an external DAC, the voltage on the SS2 pin can modulate the output voltage. It is recommended that the SS2 pin voltage be changed only after the VDD2 UVLO point is crossed, and control is handed over to the secondary side, or else the handover process does not occur smoothly, resulting in glitches in the output voltage. Ideally, the PGOOD pin can be used as a signal that indicates that regulation is achieved, to initiate the tracking. The SS2 voltage must be brought down from 1.4 V to 1.2 V, and it must be brought down even further to effect any change in the output voltage. The rate at which the output tracks the SS2 pin is dependent upon the overall system bandwidth. Note that while modulating the output voltage, if the FB pin voltage drops below (1.2 V − 100 mV = 1.1 V), the PGOOD pin toggles. REMOTE SYSTEM RESET For a remote (secondary side) system shutdown, an open-drain general-purpose input/output (GPIO) of an external micro- controller can be used to force the SS2 pin to 0 V. This pull-down causes the ADP1074 to regulate to 0 V, and the ADP1074 enters pulse skip mode or outputs a minimum duty cycle because the SS2 pin offsets because of the finite resistance of the GPIO. When VDD2 is charged from the output bus, this setup is equivalent to a system shutdown, because when VDD2 < VDD2 UVLO, the ADP1074 enters a special hiccup mode of 200 ms (instead of the standard 40 ms hiccup). When VDD2 is powered using auxiliary winding, the system regulates to the voltage proportional to the voltage on the SS2 pin and eventually enters the special hiccup mode previously mentioned, after the auxiliary rail decays below the VDD2 UVLO threshold. Therefore, the SS2 pin can achieve output tracking as well as a secondary side shutdown, also known as remote system reset, as shown in Figure 20.

Figure 20. Remote Software Reset with 200 ms Hiccup

Rev. D | Page 27 of 32 LAYOUT GUIDELINES The layout guidelines for the primary side are as follows: 1. Ground all the capacitors to their respective grounds. For example, ground the SS1 capacitor to AGND1. 2. Use the CS pin and the AGND1 pin to differentially sense the primary current measurement through the sense resistor. Do not cross the CS and AGND1 traces for current sensing across any switch nodes. 3. Place a capacitor (33 pF to 470 pF typical) close to the CS pin, connected to AGND1. 4. Connect the ground plane on the primary side to PGND1. 5. Connect AGND1 to PGND1 using a 0 Ω resistor. 6. Place resistors (1 Ω to 5 Ω typical) in series with NGATE and the main power MOSFET. These resistors aid in eliminating any ringing on the drive voltages. The layout guidelines for the secondary side are as follows: 1. Ground all the capacitors to their respective grounds. For example, ground the SS2 capacitor to AGND2. 2. Place resistors (1 Ω to 5 Ω) in series with SRx and the synchronous MOSFET. These resistors aid in eliminating any ringing on the drive voltages. 3. Connect the ground plane on the secondary side to PGND2. Connect the negative terminal of the output voltage to the PGND2 plane. 4. Use the FB pin and the AGND2 pin to remotely differentially sense the output voltage by connecting AGND2 to the negative terminal of the output voltage using a 0 Ω resistor. 5. Use a 100 nF capacitor on the MODE pin if light load mode is used in noisy environments.

Figure 25. Typical Application Circuit for Active Clamp Forward Topology

Figure 26. Typical Application Circuit for Active Clamp Forward Topology with Simple Start-Up Circuit and Bias Winding

Figure 27. Typical Application Circuit for Active Clamp Flyback Topology

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 24-Lead Standard Small Outline Package [SOIC_W]

0.75 REF

6.50 BSC

0.28 REF

Figure 29. 24-Terminal Land Grid Array [LGA]

Rev. D | Page 32 of 32 NOTES ©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D15627-6/20(D)