ADP1071-2ARWZ

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Isolated Synchronous Flyback Controller with Integrated iCoupler Data Sheet ADP1071-1/ADP1071-2 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Current mode controller for flyback topology ADP1071-1: programmable LLM or CCM for high VIN

applications

ADP1071-2: forced CCM operation Programmable slope compensation Integrated 5 kV isolation (wide body SOIC package) or 3.0 kV (LGA package) rated dielectric isolation voltage with Analog Devices, Inc., patented iCoupler technology Wide voltage supply range Primary VDD: up to 60 V (ADP1071-2 only) Secondary VDD2: up to 36 V Integrated 1 A primary side MOSFET driver Integrated 1 A secondary side MOSFET drivers for synchronous rectification Integrated error amplifier and <1% accurate reference voltage Programmable frequency range: 50 kHz to 600 kHz Duty cycle clamp limit 85% Programmable soft start and soft start from precharged load Protection features such as short circuit, output overvoltage, and overtemperature protection Power saving LLM using MODE pin (ADP1071-1only) Cycle by cycle input overcurrent protection Precision enable UVLO with hysteresis Frequency synchronization Safety and regulatory approvals (pending) UL recognition

5000 V rms for 1 minute per UL 1577 (for wide body

SOIC package)

3000 V rms for 1 minute per UL 1577 (for LGA package)

CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak (for wide body SOIC package) VIORM = 565 V peak (for LGA package) CQC certification per GB4943.1-2011 Available in 16-lead SOIC_W package and 24 terminal LGA package Isolated dc-to-dc or ac-to-dc power conversion Telecom, industrial Small cell PoE powered device Enterprise switches and routers FUNCTIONAL BLOCK DIAGRAM FLYBACK TOPOLOGY BIAS WINDING OUTPUTINPUT SYNCHRONOUS RECTIFIER OPTIONAL START-UP CIRCUITRY 15626-001 ADP1071-1/ ADP1071-2 Figure 1. GENERAL DESCRIPTION The ADP1071-1/ADP1071-2 are pulse-width modulation (PWM) current mode fixed frequency synchronous flyback controllers designed for isolated dc-to-dc power supplies. Analog Devices proprietary iCouplers® are integrated in the ADP1071-1/ADP1071-2 to eliminate the bulky signal trans- formers and optocouplers that transmit signals over the isolation boundary. Integrating the iCouplers reduces system design complexity, cost, and component count and improves overall system reliability. With the integrated isolators and metal-oxide semiconductor field effect transistor (MOSFET) drivers on both the primary and the secondary side, the ADP1071-1/ADP1071-2 offer a compact system level design and yield a higher efficiency than a diode rectified flyback converter at heavy loads. Output regulation is achieved by sensing the output voltage on the secondary side, where the feedback and the PWM signals are transmitted between the primary and secondary sides through the iCouplers. The ADP1071-1/ADP1071-2 are offered in a 16-lead SOIC_W package with an isolation voltage rating of 5 kV rms. The ADP1071-2 is designed for isolated dc-to-dc applications typically with an input voltage less than 36 V, and the ADP1071-1 targets high input voltage applications, in which the dc input voltage can exceed 60 V. The ADP1071-1/ADP1071-2 offer features such as input current protection, output overvoltage protection (OVP), undervoltage lockout (UVLO), precision enable with adjustable hysteresis, overtemperature protection (OTP), and power saving light load mode (LLM).

ADP1071-1/ADP1071-2 Data Sheet Rev. B | Page 2 of 27 TABLE OF CONTENTS Light Load Mode (LLM) and Continuous Conduction Mode

REVISION HISTORY

4/2019—Rev. A to Rev. B Change to Figure 2 Caption, Figure 3 Caption, and Added Figure 4; Renumbered Sequentially, Figure 5, and 11/2018—Rev. 0 to Rev. A 9/2018—Revision 0: Initial Version

Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 3 of 27 SPECIFICATIONS ADP1071-1: VREG1 = 9 V , VDD2 = 12 V , TA = −40°C to +125°C, unless otherwise noted. ADP1071-2: VIN = 24 V , VDD2 = 12 V , TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit ADP1071-1 SUPPLY (PRIMARY) Supply Voltage VREG1 1 µF capacitor from VREG1 to AGND1 4.7 8 12.5 V Quiescent Supply Current IVREG1 VREG1 > VREG1 UVLO, GATE pin unloaded At 100 kHz 3.8 mA At 300 kHz 4.6 mA At 600 kHz 6.8 mA IVREG1 VREG1 > VREG1 UVLO, GATE pin loaded with 2.2 nF At 100 kHz 5.5 mA At 300 kHz 10 mA At 600 kHz 16.6 mA VREG1 Start-Up Current IVREG1_STARTUP VEN < 1.2 V 160 µA VREG1 UVLO VREG1 rising 4.7 V VREG1 falling 4 V UVLO Hysteresis 0.19 V ADP1071-2 SUPPLY (PRIMARY) Supply Voltage VIN 4.7 µF capacitor from VIN to AGND1, 1 µF capacitor from VREG1 to AGND1 4.7 24 60 V Quiescent Supply Current IVIN VIN > VIN UVLO, GATE pin unloaded At 100 kHz 3.8 mA At 300 kHz 4.4 mA At 600 kHz 6.8 mA IVIN VIN > VIN UVLO, GATE pin loaded with 2.2 nF At 100 kHz 5.5 mA At 300 kHz 11 mA At 600 kHz 22 mA VIN Shutdown Current EN pin voltage (VEN) < 1.2 V, VREG1 = 0 V, VIN = 60 V 55 µA VIN and VREG1 Start-Up Current IVIN_STARTUP VEN < 1.2 V, VREG1 = 12 V, VIN = 12 V 160 µA VIN UVLO VIN rising 4.7 V VIN falling 4 V UVLO Hysteresis 0.19 V SWITCHING TIME Time from EN High to GATE Output Switching VEN > 1.2 V, 1 µF capacitor on VREG1 1 ms Time from EN Low to GATE Output Stops Switching VEN < 1.0 V, 1 µF capacitor on VREG1 1 µs

ADP1071-1/ADP1071-2 Data Sheet Rev. B | Page 4 of 27 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY (SECONDARY) Supply Voltage VDD2 4.7 µF capacitor from VDD2 to AGND2, 1 µF capacitor from VREG2 to AGND2 4.5 12 36 V Quiescent Supply Current IDD2 SR unloaded At 100 kHz 5.3 mA At 300 kHz 5.5 mA At 600 kHz 5.6 mA IDD2 SR loaded with 2.2 nF At 100 kHz 6.4 mA At 300 kHz 8.7 mA At 600 kHz 12.1 mA VDD2 UVLO Threshold VDD2 rising 3.55 V VDD2 falling 3 V UVLO Hysteresis 145 mV Secondary UVLO Hiccup Time 200 ms OSCILLATOR Switching Frequency (fS) RT resistance (RRT) = 480 kΩ (±1%) 50 − 10% 50 50 + 10% kHz RRT = 240 kΩ (±1%) 100 − 10% 100 100 + 10% kHz RRT = 120 kΩ (±1%) 200 − 10% 200 200 + 10% kHz RRT = 80 kΩ (±1%) 300 − 10% 300 300 + 10% kHz RRT = 60 kΩ (±1%) 400 − 10% 400 400 + 10% kHz RRT = 40 kΩ (±1%) 600 − 10% 600 600 + 10% kHz VREG1 PIN VREG1 Voltage Clamp VREG1 current (IVREG1) = 3 mA, VEN < 1.2 V 13.5 14.3 15.2 V VREG1 Clamp Series Resistance VREG1 forced current of 5 mA and 10 mA 16 Ω GATE DRIVERS (PRIMARY) GATE High Voltage IVREG1 = 20 mA, VIN > 9 V (ADP1071-2 only) 7.8 8 8.2 V Gate Short-Circuit Peak Current1 8 V on VREG1 1.0 A GATE Rise Time GATE loaded with 2.2 nF, 10% to 90% 17 ns GATE Fall Time GATE loaded with 2.2 nF, 90% to 10% 15 ns GATE Source Resistance RON_SOURCE Source = 100 mA 4 Ω GATE Sink Resistance RON_SINK Sink = 100 mA 2 Ω GATE Maximum Duty Cycle 84 % GATE Minimum On Time At 300 kHz, includes blanking time 175 ns SR DRIVER (SECONDARY) SR High Voltage IVREG2 = 15 mA, VDD2 > 5.5 V 4.9 5 5.1 V SR Short Circuit Peak Current1 5 V on VREG2 1.0 A SR Rise Time SR loaded with 2.2 nF, 10% to 90% 13 ns SR Fall Time SR loaded with 2.2 nF, 90% to 10% 10 ns SR Minimum On Time At 300 kHz 462 ns SR Source Resistance RON_SR_SOURCE Source = 100 mA 3 Ω SR Sink Resistance RON_SR_SINK Sink = 100 mA 1.5 Ω DEAD TIME SETTING (GATE TO SR) Dead time between SR falling and GATE rising 30 ns Dead time between GATE falling and SR rising 52 ns

Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 5 of 27 Parameter Symbol Test Conditions/Comments Min Typ Max Unit CURRENT-LIMIT SENSE (PRIMARY) CS Limit Threshold VCS_LIM Overcurrent sense limit threshold 120 mV CS Leading Edge Blanking Time 150 ns Current Source di/dt for Slope Compensation Switching period (tS) = 1/fS 20 µA per tS Overcurrent Protection (OCP) Comparator Delay 40 ns Time in OCP Before Entering Hiccup Mode 1.5 ms OCP Hiccup Time See the Input/Output Current-Limit Protection section 40 ms FB PIN AND ERROR AMPLIFIER Feedback Accuracy Voltage Temperature Coefficient 76 ppm/°C FB Input Bias Current −100 1 +100 nA Transconductance gm 230 250 270 µS Output Current Clamp Minimum −57 µA Maximum 43 µA COMP Clamp Voltage Maximum 2.52 V Minimum 0.7 V Open-Loop Gain 80 dB Output Shunt Resistance 5 GΩ Gain Bandwidth Product 1 MHz PRECISION ENABLE THRESHOLD EN Threshold VEN EN rising 1.14 1.2 1.26 V EN Hysteresis VEN < 1.2 V 4 µA VEN > 1.2 V 1 µA EN Hysteresis Current 3 µA LIGHT LOAD MODE (ADP1071-1 ONLY ) LLM Current Source Resistor from MODE to AGND1 5.5 6.5 7.5 µA TEMPERATURE Thermal Shutdown 155 °C Hysteresis −15 °C SOFT START Open Loop Soft Start Time on Primary tSS1 GATE resistor = 10 kΩ 16 × 775 tS GATE resistor = 22 kΩ 64 × 775 tS GATE resistor = 47 kΩ 256 × 775 tS GATE resistor = 100 kΩ 4 × 775 tS SS2 Current Source During startup 20 µA SS2 Discharging Current During a fault condition or soft stop 30 µA

ADP1071-1/ADP1071-2 Data Sheet Rev. B | Page 6 of 27 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SYNC PIN Synchronization Range 100 600 kHz Input Pulse Width 100 ns Number of Cycles Before Synchronization

7 Cycles

Low 0.4 V High 3 V Leakage Current 1 µA iCOUPLER DELAY COMP Signal Delay Through iCoupler 600 ns OVP PIN THRESHOLDS OVP Pin OV Threshold Overvoltage (OV) threshold for OVP pin 1.3 1.36 1.42 V OVP Pin OV Hysteresis 36 mV OVP Comparator Delay (Includes iCoupler Delay) 320 ns OVP Pin Leakage Current 1 µA OVP Hiccup Time before entering OVP hiccup mode 200 ms Hiccup time trigged by OVP event 200 ms 1 Short-circuit duration is less than 1 μs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit WIDE BODY SOIC iCOUPLER Rated Dielectric Insulation Voltage 1 minute duration 5 kV Minimum External Air Gap (Clearance) Measured from input terminals to output terminals, shortest distance through air 7.6 mm Minimum External Air Gap (Creepage) Measured from input terminals to output terminals, shortest distance path along body 7.6 mm Minimum Internal Gap (Internal Clearance) Insulation distance through insulation 0.030 mm Tracking Resistance (Comparative Tracking Index) CTI >400 V Isolation Group Material Group (DIN VDE 0110, 1/89, Table 1) II LAND GRID ARRAY (LGA) iCOUPLER Rated Dielectric Insulation Voltage 1 minute duration 2.5 kV Minimum External Air Gap (Clearance) Measured from input terminals to output terminals, shortest distance through air 4 mm Minimum External Air Gap (Creepage) Measured from input terminals to output terminals, shortest distance path along body 4 mm Minimum Internal Gap (Internal Clearance) Insulation distance through insulation 0.030 mm Tracking Resistance (Comparative Tracking Index) CTI >400 V Isolation Group Material Group (DIN VDE 0110, 1/89, Table 1) I

isolation waveforms and insulation levels. Table 3. Regulatory Information for Wide Body SOIC Package

780 V rms (1103 V peak)

389 V rms (552 V peak),

1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec. 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. Table 4. Regulatory Information for LGA Package

565 V peak, VIOTM = 4242 V peak

400 V rms (565 V peak)

200 V rms (283 V peak),

1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 sec. 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

PCB thermal design is required. Table 6. Thermal Resistance1

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

Table 7. Maximum Continuous Working Voltage Wide Body

1 Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details. Table 8. Maximum Continuous Working Voltage, LGA1 barrier. See the Insulation Lifetime section for more details.

Figure 2. ADP1071-1 SOIC_W Pin Configuration Figure 3. ADP1071-2 SOIC_W Pin Configuration Table 9. Pin Function Descriptions, Wide-Body SOIC pin. Connect a resistor from GATE to AGND1 to set up the open loop soft start time. 2 2 AGND1 Ground for the Primary Side.

4 Not

or higher) to force an LLM operation, or to a resistor to set up an LLM threshold voltage. 4 VIN Input Voltage (ADP1071-2 Only). See the Primary Side Supply, Input Voltage, and LDO section. voltage to this pin is guaranteed stable. Reference this pin to AGND1. 5 5 EN Precision Enable Input. The controller is enabled when EN is above the EN threshold voltage. This pin also has a programmable EN hysteresis. This pin is referenced to AGND1. sets up the input current limit. This pin is also used for the external slope compensator. 7 7 RT Switching Period Resistor. Connect a resistor from RT to AGND1 to set the oscillator frequency. start time on the secondary side. (gm) amplifier. Reference this pin to AGND2. from OVP to the output and AGND2. size of this capacitor can be reduced if the input voltage to VDD2 is guaranteed to be stable. 15 15 AGND2 Analog Ground on Secondary Side. 16 16 SR Driver Output for Synchronous Rectifier MOSFET.

EPAD1 AND EPAD2 ARE INTERNALLY TIED TO

AGND1 AND AGND2, RESPECTIVELY. Figure 4. ADP1071-1 LGA Pin Configuration

EPAD1 AND EPAD2 ARE INTERNALLY TIED TO

AGND1 AND AGND2, RESPECTIVELY. Figure 5. ADP1071-2 LGA Pin Configuration Table 10. Pin Function Descriptions, LGA 1 1 GATE Driver Output for the Main Power MOSFET on the Primary Side. GATE is a multifunction pin. Connect a resistor from the GATE pin to AGND1 to set up the open loop soft start time. 4 4 AGND1 Ground for the Primary Side. 5 5 VREG1 8 V Regulated LDO Output for the MOSFET Driver. Connect 1 µF or greater from VREG1 to AGND1.

6 Not

logic (2.5 V or higher) to force an LLM operation, or to a resistor to set up an LLM threshold voltage. 6 VIN Input Voltage (ADP1071-2 Only). See the Primary Side Supply, Input Voltage, and LDO section. input voltage to the VIN pin is guaranteed stable. Reference the VIN pin to AGND1. 7 7 EN Precision Enable Input. The controller is enabled when EN is above the EN threshold voltage. The EN pin also has a programmable EN hysteresis. The EN pin is referenced to AGND1. resistor sets up the input current limit. This pin is also used for the external slope compensator. used. The SYNC frequency is recommended to be within 10% of the frequency set by the RT pin. start time on the secondary side. m) amplifier. Reference the COMP pin to AGND2.

Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 11 of 27 18 18 OVP Output Overvoltage Protection. The OVP threshold is set at 1.36 V. Connect a resistive divider from the OVP pin to the output and AGND2. 19 19 VDD2 Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power supply for a self driven configuration. Connect a 4.7 µF capacitor from VDD2 to AGND2. The size of this capacitor can be reduced if the input voltage to VDD2 is guaranteed to be stable. 20 20 VREG2 5 V Regulated LDO Output for Internal Bias and Powering of the Drivers of the Synchronous Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 µF capacitor from VREG2 to AGND2. 21 21 AGND2 Analog Ground on Secondary Side. 22 22 NC No Connect. 23 23 NC No Connect. 24 24 SR Driver Output for Synchronous Rectifier MOSFET. EPAD1 Exposed Pad 1. Exposed pad is internally tied to AGND1. EPAD2 Exposed Pad 2. Exposed pad is internally tied to AGND2.

ADP1071-1/ADP1071-2 Data Sheet Rev. B | Page 14 of 27 THEORY OF OPERATION The ADP1071-1/ADP1071-2 are PWM, current mode, fixed frequency, synchronous flyback controllers designed for isolated dc-to-dc power supplies. Analog Devices iCouplers are integrated in the ADP1071-1/ADP1071-2 to eliminate the bulky signal transformers and optocouplers that transmit signals over the isolation boundary. Integrating the iCouplers reduces system design complexity, cost, and component count and improves overall system reliability. With the integrated isolators and MOSFET drivers on both the primary and the secondary side, the ADP1071-1/ADP1071-2 offer a compact system level design and yield a higher efficiency than a diode rectified flyback converter at heavy loads. Traditionally in a forward or flyback converter, a discrete optocoupler is used in the feedback path to transmit the signal from the secondary to the primary side, and an external trans- former is used for transmitting the PWM signal from the primary to the secondary side for synchronous rectification. However, the current transfer ratio (CTR) of the optocouplers degrades over time and over temperature and so the optocoupler must be replaced every 5 to 10 years, depending on the manu- facturing quality and optocoupler grade that determines the initial CTR. The ADP1071-1/ADP1071-2 eliminate the use of an optocoupler and signal transformer, thus reducing system cost, PCB area, and complexity, while improving system reliability without the issue of CTR degradation of the optocouplers. The ADP1071-1/ADP1071-2 controllers offer a complete solution for an isolated dc-to-dc power supply by integrating the 5 kV isolators and the primary and secondary control circuitries in one package. The PWM controls are performed on the primary side by sensing the input peak current cycle by cycle with a sense resistor at the source of the main switching MOSFET. The output of the converter is sensed by the secondary circuitry, which sends the feedback and PWM signals to the primary side via the 5 kV integrated isolators for a complete control loop solution. The primary circuitry in the ADP1071-1/ADP1071-2 includes an 8 V LDO, input current sensing, bias circuit, and MOSFET drivers including an active clamp reset driver, slope compensation, external frequency synchronization, PWM generator, and a programmable maximum duty cycle setting. The primary side also has pins for differential sensing of the current sense signal. The secondary circuitry includes the feedback compensation, a

5 V LDO regulator, an internal reference, two MOSFET drivers for

synchronous rectification, and a dedicated pin for overvoltage protection. Additionally, the secondary side features differential output voltage sensing and a programmable LLM setting. The integrated iCouplers carry out the communications between the primary and secondary sides by transmitting the feedback signal and the PWMs over the isolation barrier. The feedback signal and timing of synchronous rectifier PWMs are transmitted between the primary and the secondary sides, or between the secondary and primary sides, through the iCouplers using a proprietary transmission scheme. The ADP1071-1/ADP1071-2 also offer features such as input current protection, O V P, UVLO, precision enable with adjustable hysteresis, O T P, LLM, and tracking.

MOSFET driver at the GATE pin. an external start-up circuit. to the VIN pin and has a regulated output of 8 V at VREG1. that the LDO shuts off during normal operation. 14 V Zener diode is connected at VREG1. 5 V , the LDO regulator operates in dropout mode. with an auxiliary voltage in the 8 V to 12 V range. 4.5 V) and the voltage at the EN pin rises above 1.2 V . biasing is finished, the soft start procedure initiates. VEN ≥ 1.2 V and obtain the desired hysteresis. and becomes inactive when VEN is above the EN threshold. toggles the EN pin when the input voltage hovers at the threshold. Figure 18. Precision EN with Adjustable Hysteresis

Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 17 of 27 SOFT START PROCEDURE The following procedure assumes that the VDD2 pin is powered directly from the output voltage of the power supply. To ensure a smooth output voltage ramp during startup, the soft start sequence is controlled by two soft start control circuits, one in the primary (for open-loop soft start using the GATE pin) and the other in the secondary (for closed-loop soft start, using the SS2 pin). Proper handshaking between the primary side and the secondary side is needed prior to the secondary side taking control. The open-loop soft start time is determined by the resistor on the GATE pin prior to startup. The primary peak current is increased gradually every switching period. The slew rate of the increase in peak current is determined by selecting the GATE resistor prior to startup. The current increases from a minimum of 0 A to a maximum of 120 mV/R SENSE. This rate is the open- loop soft start. Four speeds are available: 4 × 775, 16 × 775, 64 × 775, and 256 × 775 switching periods for resistors 100 kΩ, 10 kΩ, 22 kΩ, and 47 kΩ, respectively. During this time, the ADP1071-1/ADP1071-2 start firing the PWM pulses and the output voltage continues to build up slowly if the average current on the secondary side exceeds the load current. Because the ADP1071-1/ADP1071-2 are current mode controllers, the output capacitor starts charging only when the primary current limit exceeds the load current requirement. The handshaking process is as follows. When VDD2 reaches the UVLO of approximately 3.5 V , the internal circuitry on the secondary side is activated and the ADP1071-1/ADP1071-2 initiate the following two processes: 1. The ADP1071-1/ADP1071-2 make the voltage on the SS2 pin equal to the value on the FB pin, with an SS2 pin current, at 10 times the nominal current source of 20 µA on the SS2 pin. 2. Simultaneously, the current limit on the primary side is transferred over to the secondary side and the voltage on the COMP pin is made equal to the instantaneous current limit of ±100 mV. There is a timeout for this process, which is 1.5 ms after the VDD2 UVLO threshold is crossed. When this process is satisfied, the transmission of the COMP signal occurs from the secondary to the primary side. The ADP1071-1/ ADP1071-2 transmit the COMP signal by continuously sampling the analog signal at the COMP pin. The sampled value is then transmitted using a proprietary scheme to the primary side where the instantaneous value of the CS pin is compared to the COMP level to determine the falling edge of the GATE pulse. The COMP signal is, therefore, a representation of the primary current limit. After COMP transmission begins, the primary side receives the signal and control is completely handed over to the secondary side when either the received level of COMP on the primary side is within ±100 mV or up to 128 switching periods (typically 8) have passed, starting from the first pulse being transmitted to the primary side. Then, after the control is handed over to the secondary side, the closed-loop soft start begins, where the SS2 capacitor is charged at a nominal rate of 20 µA. The output voltage then rises to the regulation voltage based on the SS2 pin voltage. The voltage on the SS2 pin continues to rise to 1.2 V , that is, the steady state voltage on the FB pin. At this stage, the power supply is in regulation, and the output voltage is at its target value. At the end of the soft start process, the voltage on the SS2 pin continues to rise to approximately 1.4 V . In steady state, the FB pin (that is, the reference voltage) is 1.2 V . The SR1 and SR2 synchronous drivers begin to pulse after VDD2 crosses the UVLO threshold. If the voltage at the VDD2 pin is greater than the UVLO voltage, such as a soft start from the precharged output, or if the VDD2 pin is powered by an external supply, the secondary side assumes control from the moment the EN pin is enabled, and only SS2 is used for the soft start procedure. When initiating a soft start from the precharged output, the SS2 pin tracks the FB pin and then initiates a soft start. This process eliminates any glitches in the output voltage. When soft starting into a precharged output, the SR gate is prevented from turning on until the SS2 voltage reaches the precharged voltage at the FB pin. This soft start scheme prevents the output from being discharged, and it prevents reverse current. Under abnormal situations, such as a shorted load or a transient condition on the load during the soft start process, FB may not be able to track SS2 accurately. If this condition occurs before the VDD2 UVLO threshold is crossed, the open loop soft start is in effect. If it occurs after the VDD2 UVLO threshold is crossed, SS2 tracks the FB pin and then continues with the soft start process until the regulation voltage is reached. In all conditions, control is handed over to the secondary side if FB ≥ 1.2 V . When the secondary VDD2 is directly powered by the output of the converter, the minimum output voltage required is higher than the secondary UVLO voltage. For output voltages less than the secondary UVLO voltage, a third winding is needed to generate an auxiliary voltage to power the secondary side circuitry. Alter- nately, in most cases, a diode resistor capacitor combination from the switch node can provide the voltage to VDD2.

ADP1071-1/ADP1071-2 Data Sheet Rev. B | Page 18 of 27 OUTPUT VOLTAGE SENSING AND FEEDBACK The output voltage of the converter is set by a resistive divider to the FB pin. The resistive divider must be set in a manner such that the voltage at the FB pin is 1.2 V in steady state. The output voltage must be differentially sensed using the FB pin and the AGND2 pin. LOOP COMPENSATION AND STEADY STATE OPERATION The FB pin feeds into the negative terminal of a transconductance amplifier (or gm amplifier) with a gain of approximately 250 µA / V. The positive input terminal of the gm amplifier is connected to SS2, which provides the reference setpoint voltage. The output of the gm amplifier is connected to the COMP pin. The voltage on the COMP pin is representative of the current peak limit required to sustain regulation. This pin is continuously sampled, and the signal is transmitted to the primary side, where it is compared to the sensed primary current using a comparator. When the comparator trips, it causes GATE to terminate. Typically, an RC network in series is connected between the COMP pin and AGND2 for compensation. A high frequency pole in the form of a capacitor can also be added in parallel to the RC network. The output of the gm amplifier is clamped to a minimum and max- imum current of approximately +40 µA and −65 µA, respectively. The COMP node is clamped to a lower and higher level of approximately 0.7 V and 2.52 V, respectively. This is representative of the CS range from 0 mV to 120 m V. SLOPE COMPENSATION For a peak current mode controller with a duty cycle higher than 50%, slope compensation is necessary for a stable operation. To set up an external compensation in the ADP1071-1/ADP1071-2, connect the external RRAMP resistor (see Figure 30) between CS and the current sense resistor, RSENSE, to set up the slope voltage ramp for the control signal. It is important to sense the signal differentially. See the Layout Guidelines section for more details. An internal ramp current starts from 0 µA at the minimum duty cycle (that is, the beginning of the switching period) and increases linearly toward a maximum of 20 µA at the end of the switching period. The slope of the voltage ramp is the ramp current times R RAMP. RRAMP is sized using the following equation: 20 μA OUT 2 SENSE RAMP S V NRRk tLN≥ ×× × where: k = 0.5 for nominal cases and k = 1 for deadbeat control. VOUT is the desired output voltage. L is the output inductor. N1 and N2 are the primary and secondary turns of the transformer. tS is the switching period. INPUT/OUTPUT CURRENT-LIMIT PROTECTION There is no direct current-limit sensing circuit in the secondary side, but the output current limit is indirectly set by sensing the input primary peak current cycle by cycle. A leading edge blanking time is added after the rising edge of the GATE signal to avoid picking up any unwanted noise or ringing at the CS pin at the start of the switching period. The input peak current limit is set by connecting a sense resistor, R SENSE, from the source of the main MOSFET to AGND1, and the sensed voltage appears at the CS pin. To generate the slope- comp ramp, insert the slope compensation resistor, RRAMP, between CS and RSENSE. The CS current limit, VCSLIM, is internally set to 120 m V. Calculate the RSENSE value by _ 20 μACS LIM RAMP SENSE PKPRI VRR I −×= where: VCS_LIM is the CS current limit. IPKPRI is the primary peak current. When the sensed input peak current is above the CS limit threshold, the controller operates in the cycle by cycle constant current limit mode for 1.5 ms. Then, the controller immediately shuts down the primary and secondary drivers. The controller then enters hiccup mode for the next 40 ms and restarts the soft start sequence after this timeout period. The slope ramp can affect the accuracy of the current-limit threshold because the voltage drop across RRAMP contributes to the inaccuracy of the peak current limit. For instance, if the added slope ramp voltage is 20% of the current-limit threshold, the actual input peak current limit can be off by as much as 20% depending on where the peak current-limit threshold is tripped during the on cycle. In the event of an output short circuit, the controller treats this condition as an overcurrent event and enters the 40 ms hiccup mode. Under certain situations, the ADP1071-1/ADP1071-2 exit OCP hiccup mode. In this condition, even though the COMP pin is at the maximum clamp level, the device does not enter hiccup mode. It is guaranteed that the PWMs are terminated whenever the CS maximum threshold is reached. The conditions under which this can occur are as follows. Under certain conditions, the ADP1071-1/ADP1071-2 exit OCP hiccup mode. In these conditions, the COMP pin is at the maximum clamp level, but the device does not enter hiccup mode. However, it is guaranteed that the PWMs are terminated whenever the CS maximum threshold is reached. The condition under which the ADP1071-1/ADP1071-2 skip entering hiccup mode is when VDD2 is powered through an auxiliary winding, and an output short circuit occurs that results in the FB pin having a voltage that is less than 300 mV . This event is more prominent at high temperatures (>85°C) and can be exacerbated at higher temperatures.

effect that the OCP hiccup mode feature has on the SS2 pin.

When VDD2 is powered directly from the output voltage, if a short circuit on the output terminals of the load occurs after steady state regulation is achieved, the VDD2 pin voltage is less than the UVLO threshold, and the device enters hiccup mode for 200 ms, similar to the hiccup time described in the Remote System Reset section.
When VDD2 is powered through auxiliary winding or another configuration, when a short circuit occurs on the output terminals, the auxiliary winding is not shorted and maintains a positive voltage above the VDD2 UVLO threshold. To enter hiccup mode, the following circuit is recommended, as shown in Figure 19. The circuit operates as follows: when the output voltage goes low due to a short circuit, the D1 diode turns on, which pulls the base of the bipolar junction transistor (BJT) low, shutting off VDD2. The system then enters hiccup mode, as described in the Remote System Reset section. R3 is sized to bias the Zener diode and R4 is sized such that ZENER − 1)/R4 > IZENER, where VZENER is the voltage of the diode and IZENER is the biasing current of the diode. This sizing ensures that the impedance of the resistor is less than the impedance of the diode, which causes the voltage of the diode to drop, and allows VDD2 to enter UVLO. If the output voltage is <5 V , the same procedure can be used to size the R4 resistor. If a discrete LDO is not used, a simple resistor and diode connector to the output voltage is sufficient. In this case, the R4 resistor is sized to limit the current through the D1 diode when the output voltage is 0 V during a short circuit event. Because the bandwidth of the system is high, the ADP1071-1/ADP1071-2 are able to maintain voltage regulation at the proper voltage level, even if the auxiliary winding voltage is higher than the output voltage. The soft start and soft start from precharge conditions is met with the addition of this circuit due to the bandwidth of the overall system. 500Ω 100Ω VDD2 VOUT AGND2 ~6.3V ZENER VOUT 100Ω ALTERNATE OPTION FROM AUXILIARY WINDING ~10V 15626-118

Figure 19. Recommended Circuit to Guarantee Hiccup Mode and secondary MOSFET drivers (GATE and SR) are held low. the ADP1071-1/ADP1071-2 restart with a soft start sequence. fS is the switching frequency. R is the resistor on the RT pin. clamp is internally set to 85%. continues to operate with the internal oscillator frequency.

clock is able to lock onto the dithered clock cycle by cycle. recommended power supply range at VDD2 is from 6 V to 36 V. supply VDD2 with an auxiliary power supply greater than 5 V. external MOSFET driver such as the ADP3624 or the ADP3654. exceeds 1.36 V for a sustained period of 200 µs. and SR is provided, as shown in Figure 20. Figure 20. Gate to SR Dead Time from zero to full duty cycle instantaneously. time, optimizes the dynamic performance of the output response. cycles with minimum on time. termination at a negative current. IMODE is the current flowing out of the MODE pin. For full time CCM operation, connect MODE to AGND1. forced CCM. Pulse skipping is not available in the ADP1071-2.

Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 21 of 27 SOFT STOP The ADP1071-2 employs a soft stop feature that brings the output voltage gradually down to zero by using the SS2 pin as a reference. During the soft stop procedure, the SS2 pin is discharged to zero by a current sink of approximately 1.5 times the value during closed- loop soft start. When the voltage at EN drops below the EN threshold, the SR secondary driver shuts off immediately, and the primary GATE pulse width gradually decreases the duty cycle from the last known condition to the minimum pulse width and down to zero, causing the output voltage to decrease. The soft stop feature prevents any reverse current when the controller is shut down. When the output voltage decreases below the VDD2 UVLO threshold, there is no transmission of the COMP signal to the primary side. Therefore, the output voltage continues to decrease at the rate at which the load current discharges the output capacitor. When the load is at a minimum or at no load, the output voltage does not discharge because any reduction in duty cycle or current limit does not discharge the output voltage linearly. OCP/FEEDBACK RECOVERY During steady state, the FB pin is at 1.2 V . At this time, the SS2 pin voltage is 1.4 V . Under abnormal situations, such as an overload condition, the output voltage can dip severely. In such an event, the current limit is at the maximum level, and the COMP pin voltage is at its clamp level. If the two conditions of the COMP pin voltage being clamped and VFB < (1.2 V − 100 mV) are satisfied, the controller discharges the SS2 pin using a fast current sink (200 µA) to make the SS2 pin equal to the FB pin. The controller then attempts to perform a soft start from this precharged condition, that is, from the last known value of the output voltage. This process is how the OCP/feedback recovery feature operates. However, if at any time the voltage on the COMP pin is above the maximum clamp voltage for a period greater than 1.5 ms, the system enters hiccup mode. During the soft start from precharge, the output voltage rises at the same rate as determined by the capacitor on the SS2 pin. The SS2 pin voltage determines the current limit during this period. If, however, there is a detrimental fault in the power stage that prevents the rise of the output voltage, V FB does not track SS2 and when SS2 > (VFB + 100 mV), the COMP pin voltage increases to the clamp level and the system again enters the OCP/feedback recovery mode. OUTPUT VOLTAGE TRACKING The ADP1071-1/ADP1071-2 offer a tracking feature. During steady state, the FB pin is at 1.2 V . At this time, the SS2 pin voltage is at 1.4 V. Using an external digital-to-analog converter (DAC), the voltage on the SS2 pin can modulate the output voltage. It is recommended that the SS2 pin voltage be changed only after the VDD2 UVLO point is crossed, and control is handed over to the secondary side, or else the handover process does not occur smoothly, resulting in glitches in the output voltage. The SS2 voltage must be brought down from 1.4 V to 1.2 V , and it must be brought down even further to effect any change in the output voltage. The rate at which the output tracks the SS2 pin is dependent upon the overall system bandwidth. REMOTE SYSTEM RESET For a remote (secondary side) system shutdown, an open-drain general-purpose input/output (GPIO) of an external microcontroller can be used to force the SS2 pin to 0 V . This pull-down causes the ADP1071-1/ADP1071-2 to regulate to 0 V, a n d t h e ADP1071-1/ADP1071-2 enter pulse skip mode or output a minimum duty cycle because the SS2 pin offsets because of the finite resistance of the GPIO. When the VDD2 is charged from the output bus, this setup is equivalent to a system shutdown because when VDD2 < VDD2 UVLO, the ADP1071-1/ADP1071-2 enter a special hiccup mode of 200 ms, (instead of the standard 40 ms hiccup). When VDD2 is powered using auxiliary winding, the system regulates to the voltage proportional to the voltage on the SS2 pin and eventually enters the special hiccup mode previously mentioned, after the auxiliary rail decays below the VDD2 UVLO threshold. Therefore, the SS2 pin can achieve output tracking as well as a secondary side shutdown, also known as remote system reset, as shown in Figure 21.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]

0.75 REF

6.50 BSC

0.28 REF

Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 27 of 27 ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADP1071-1ARWZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ADP1071-1ARWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ADP1071-1ARWZ-R7 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ADP1071-1ACCZ −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6 ADP1071-1ACCZ-RL −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6 ADP1071-1ACCZ-R7 −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6 ADP1071-2ARWZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ADP1071-2ARWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ADP1071-2ARWZ-R7 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ADP1071-2ACCZ −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6 ADP1071-2ACCZ-RL −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6 ADP1071-2ACCZ-R7 −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6 ADP1071-1EVALZ ADP1071-1 Evaluation Board with Wide-Body IC ADP1071-2EBZ12.1V ADP1071-2 Evaluation Board with Wide-Body IC 1 Z = RoHS Compliant Part. ©2018–2019 Analog Devices, Inc. All rights reserved. Trade marks and registered trademarks are the property of their respective owners. D15626-0-4/19(B)

Summary

Isolated Synchronous Flyback Controller 4/2019-Rev. A to Rev. B

Description