ADP1053ACPZ-R7

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Document overview

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Technical content

Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.

FEATURES

Configurable 8-PWM engine with up to 3 channels 2 independent digitally controlled channel outputs Voltage mode PWM control with 625 ps resolution Remote voltage sensing on both channels Programmable compensation filters Voltage feedforward option Flexible start-up sequencing and tracking Switching frequency: 50 kHz to 625 kHz Frequency synchronization Independent channel protections: OVP and OCP 2 independent OTP circuits Programmable fault protection sequence Volt-second balance and dual-phase current balance for interleaved configurations On-board EEPROM PMBus-compliant Graphical user interface (GUI) for ease of programming Available in a 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Isolated dc-to-dc power supplies Intermediate rail power supplies Nonisolated dc-to-dc power converter GENERAL DESCRIPTION The ADP1053, based on a voltage mode PWM architecture, is a flexible, application dedicated digital controller designed for isolated and nonisolated dc-to-dc power supply applications. The ADP1053 enables highly efficient power supply design and facilitates the introduction of intelligent power management techniques to improve energy efficiency at a system level. The ADP1053 provides control, monitoring, and protection of up to three independent channel outputs. The eight flexible PWM outputs can be configured as three independent channels: two regulated channels with feedback control plus one additional unregulated channel with a fixed duty cycle. The frequency of these three channels can be programmed individually from 50 kHz to 625 kHz; all channels can be synchronized internally or to an external signal. All eight PWM outputs can also be assigned to enable a single- channel solution, which may be required in high power, high efficiency applications. Features include differential voltage sensing, fast current sensing, flexible start-up sequencing and tracking, and synchronization between devices to reduce low frequency system noise. Protection and monitoring features include overcurrent protection (OCP), undervoltage protection (UVP), overvoltage protection (OVP), and overtemperature protection (OTP). SIMPLIFIED TYPICAL APPLICATION CIRCUIT DRIVER DRIVER DRIVER 10241-001 ADP1053 PWM OUTPUTS CS2–_A CS2+_A VS+_A VS–_A RSENSE VOUT A+ VOUT A– LOAD VIN_DC iCoupler DUPLICATE THE ABOVE SCHEMATICS FOR CHANNEL B VOUT B+ VOUT B– Figure 1.

Rev. A | Page 2 of 84 TABLE OF CONTENTS Overtemperature Protection (OTP) and Overtemperature

Rev. A | Page 3 of 84 EEPROM_DATA_00 Through EEPROM_DATA_15 Manufacturer-Specific Extended Command Register Channel A/Channel B Current Sense and Limit Setting Channel A/Channel B Voltage Sense and Limit Setting Soft Start, Digital Filter, and Modulation Setting Registers ..60 Fast OCP and Channel C Current Sense Setting Registers...69

REVISION HISTORY

6/12—Rev. 0 to Rev. A Changes to Source Current and Temperature Readings According 1/12—Revision 0: Initial Version

Rev. A | Page 4 of 84 The ADP1053 provides local and remote differential sensing of the output voltage, which is converted to the digital domain using high speed, high resolution Σ-Δ converters. The proprie- tary conversion system maximizes the bandwidth of the converter and minimizes output noise due to digital quantization error, thus dramatically reducing the power consumption of the digital controller. Configurable compensation networks provide three poles and two zeros to control feedback loop stability and optimize output response. In addition, a programmable feedforward feature can be enabled to enhance input voltage response. The ADP1053 provides extensive protection and monitoring capabilities. For example, each regulated output has its own independent voltage threshold, and overvoltage protection is provided for each regulated output. The protection and moni- toring features combine to eliminate the possibility of a single point of failure. Fast overcurrent protection is provided to protect the system from short circuits. Accurate current sensing and overcurrent limit protections are also included. In addition, two overtemp- erature protection circuits are provided for use with 100 kΩ thermistors to sense the hot spots. Other protection and monitoring features include a program- mable power-on (PSON) function and power-good monitoring for Channel A and Channel B. All these features are programmable through the PMBus/I interface. This interface is also used for calibration. Additional information, such as input current, output current, and fault flag status, can be read via the PMBus/I 2C interface. The built-in EEPROM is used to store programmed values and instructions. System reliability is improved through a built-in checksum and redundancy of critical circuits. In the event of a system fault, the EEPROM can be configured to capture the first instance of failure; this stored fault data can be analyzed to improve overall system reliability and reduce failure mode analysis time. The ADP1053 is designed to maximize ease of use and reduce time to market with the provision of a comprehensive, easy to use graphical user interface (GUI) that allows programming of most parameters and protection and monitoring limits. The ADP1053 is available in a 40-lead LFCSP package and operates from a single 3.3 V supply. FUNCTIONAL BLOCK DIAGRAM ADP1053 10241-002 ADC ADC ADC ADC ADC ADCDAC DAC PWM ENGINE DIGITAL CORE 1.2V 1.2V 1.2V ADC ADCCS1_A CS1_B CS OUT1 8kBYTE EEPROM I2C INTERFACE CS2+_A CS2–_A PGND_B OVP_B OUT3 OUT4 OUT2 OUT5 OUT6 OUT7 OUT8 PGOOD_A FLGI/SYNI FLGO/SYNO PSON_A PSON_B PGOOD_B RTD2 RTD1 ADD ADC ACSNSADC UVLO LDO OSC VREF RES VDD DGND VCORE AGND SDA SCL Figure 2.

Rev. A | Page 5 of 84 SPECIFICATIONS VDD = 3.0 V to 3.6 V , TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit SUPPLY VDD 3.0 3.3 3.6 V IDD PWM pins unloaded Normal operation (PSON high) 30 mA Power supply off (PSON low) 30 mA Shutdown (VDD below UVLO) 100 μA During EEPROM programming IDD + 8 mA POWER-ON RESET UVLO Threshold VDD Rising 3.0 V VDD Falling 2.750 2.85 2.975 V OVLO Threshold 3.7 3.9 4.1 V OVLO Debounce When set to 2 μs 2 μs When set to 500 μs 500 μs VCORE PIN Output Voltage 330 nF capacitor between VCORE and DGND 2.3 2.5 2.7 V OSCILLATOR AND PLL PLL Frequency RES = 10 kΩ 200 MHz DPWM Resolution 625 ps VS_A, VS_B VOLTAGE SENSE Input Voltage Differential voltage from VS+_A to VS−_A and from VS+_B to VS−_B 0 1 1.6 V Input Voltage FSR 1.6 V VS_A, VS_B Accurate ADCs Valid Input Voltage Range 0 1.5 V ADC Register Update Rate 100 Hz Resolution 12 Bits Measurement Accuracy From 0% to 100% of valid input voltage −2.8 +2.1 % FSR −44.8 +33.6 mV From 10% to 90% of valid input voltage −1.35 +2.1 % FSR −21.6 +33.6 mV From 900 mV to 1.1 V −1.2 +1.65 % FSR −19.2 +26.4 mV Temperature Stability From 900 mV to 1.1 V −0.1 +0.1 mV/°C Common-Mode Voltage Offset Voltage from VS−_A and VS−_B to AGND to achieve measurement accuracy −200 0 +200 mV VS_A, VS_B High Speed ADCs Equivalent Resolution At 390.6 kHz switching frequency 6 Bits Dynamic Range Regulation voltage 300 mV to 1.4 V ±10 mV VS_A, VS_B UVP Based on VS_A, VS_B accurate ADC Threshold Accuracy Same as accurate ADC measurement accuracy specifications Comparator Update Speed 10 ms OVP_A, OVP_B PINS Threshold Accuracy −1.7 +1.6 % Propagation Delay (Latency) Debounce time not included 58 110 ns

Rev. A | Page 6 of 84 Parameter Test Conditions/Comments Min Typ Max Unit AC SENSE Input Voltage Voltage from ACSNS to AGND 0 1 1.6 V Input Voltage FSR 1.6 V ACSNS ADC Valid Input Voltage Range 0 1 1.4 V ADC Register Update Rate 800 Hz Resolution 11 Bits Measurement Accuracy From 10% to 90% of valid input voltage −1.25 +1.8 % FSR −20 +28.8 mV From 0% to 100% of valid input voltage −5.4 +1.9 % FSR −86.4 +30.4 mV ACSNS Threshold Accuracy Same as ACSNS ADC measurement accuracy specifications Comparator Update Speed 1 ms CS, CS1_A, CS1_B CURRENT SENSE Input Voltage Voltage from CS/CS1_A/CS1_B to AGND 0 1.6 V Input Voltage FSR 1.6 V CS, CS1_A, CS1_B ADCs Valid Input Voltage Range 0 1 1.4 V ADC Register Update Rate 100 Hz Resolution 12 Bits Measurement Accuracy From 10% to 90% of valid input voltage −1.3 +1.8 % FSR −20.8 +28.8 mV From 0% to 100% of valid input voltage −5.6 +1.8 % FSR −89.6 +28.8 mV Fast OCP Threshold Value 1.18 1.2 1.22 V Propagation Delay (Latency) Debounce/blanking time not included 58 110 ns CS2_A, CS2_B CURRENT SENSE Input Voltage Differential voltage from CS2+_A to CS2−_A and from CS2+_B to CS2−_B 0 120 mV Input Voltage FSR 120 mV Common-Mode Voltage Common-mode voltage from CS2+_A/ CS2−_A and CS2+_B/CS2−_B to AGND to achieve measurement accuracy 0.8 1 1.3 V CS2_A, CS2_B ADCs Valid Input Voltage Range 0 120 mV Resolution 12 Bits Measurement Accuracy Low-Side Mode with User Trim VOUT = 0 V, 5 kΩ level-shifting resistor From 0 mV to 110 mV −1.85 +2.1 % FSR −2.22 +2.52 mV From 110 mV to 120 mV −6.1 +1.5 % FSR −6.36 +0.84 mV High-Side Mode with User Trim VOUT = 11 V, 5 kΩ level-shifting resistor From 0 mV to 110 mV −1.6 +2.3 % FSR −1.92 +2.76 mV From 110 mV to 120 mV −5.3 +0.7 % FSR −6.36 +0.84 mV

Rev. A | Page 7 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Accurate OCP Threshold Accuracy Same as ADC accuracy ADC Register Update Rate 100 Hz Current Sink (High Side) VOUT = 11 V, 5 kΩ level-shifting resistor 1.81 1.9 1.99 mA Current Source (Low Side) VOUT = 0 V, 5 kΩ level-shifting resistor 180 230 280 μA Fast Reverse Current Threshold (CS2+, CS2−) Threshold Accuracy −17 mV setting −23.2 −17 −9.6 mV −27 mV setting −34.7 −27 −18.1 mV Threshold Speed Debounce time = 40 ns 110 150 ns RTD1, RTD2 TEMPERATURE SENSE PINS Input Voltage Voltage from RTDx to AGND 0 1.6 V Input Voltage FSR 1.6 V Source Current Set to 46 μA 44.3 46 47.3 μA Set to 40 μA 38.6 40 42 μA Set to 30 μA 28.8 30 31.7 μA Set to 20 μA 18.8 20 21.5 μA Set to 10 μA (factory default setting) 9.1 10 11 μA RTD1, RTD2 ADCs Valid Input Voltage Range 0 1.28 V ADC Register Update Rate 100 Hz Resolution 12 Bits Measurement Accuracy From 2% to 20% of valid input voltage −0.3 +0.45 % FSR −4.8 +7.2 mV From 0% to 100% of valid input voltage −2.6 +1.6 % FSR −41.6 +25.6 mV Temperature Readings According to Internal Linearization Scheme Factory trimmed to 10 μA; Register 0xFE80 and Register 0xFE81 = 0x00; NTC R0 = 100 kΩ, 1%; beta = 4250, 1%; REXT = 16.5 kΩ, 1% T = 25°C to 100°C 7 °C T = 100°C to 125°C 5 °C OTP1, OTP2, OTW1, OTW2 Threshold Accuracy T = 85°C with 100 kΩ||16.5 kΩ −0.9 +0.25 % FSR −14.4 +4 mV T = 100°C with 100 kΩ||16.5 kΩ 0.5 1.1 % FSR 8 17.6 mV Comparator Update Speed 10 ms OUT1 TO OUT8, FLGO/SYNO PINS Digital output pins Output Low Voltage, VOL Source current = 10 mA 0.4 V Output High Voltage, VOH Source current = 10 mA VDD − 0.4 V Rise Time CLOAD = 50 pF 4.5 ns Fall Time CLOAD = 50 pF 2.5 ns PGOOD_A, PGOOD_B PINS Open-drain output pins Output Low Voltage, VOL 0.4 V PSON_A, PSON_B, FLGI/SYNI PINS Digital input pins Input Low Voltage, VIL 0.8 V Input High Voltage, VIH VDD − 0.8 V SDA/SCL PINS Input Low Voltage, VIL 0.8 V Input High Voltage, VIH VDD − 0.8 V Output Low Voltage, VOL 0.8 V Leakage Current −5 +5 μA

pending EEPROM qualification. Figure 3. Serial Bus Timing Diagram

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance lines, see the AN-772 Application Note.

23 CS1_B

24 PGOOD_B

25 CS2+_B

26 CS2–_B

27 OVP_B

28 PGND_B

29 VS–_B

30 VS+_B

21 PSON_B

1. THE EXPOSED PAD ON THE UNDERSIDE OF THE

PACKAGE SHOULD BE SOLDERED TO AGND. Figure 4. Pin Configuration Table 4. Pin Function Descriptions 1 VS+_A Noninverting Input of the Voltage Sense ADC for Channel A Loop Control. This signal is referenced to VS−_A. 3 PGND_A Reference Pin for Channel A Overvoltage Protection (OVP_A). 4 OVP_A Overvoltage Protection Comparator Input for Channel A. This signal is referenced to PGND_A. be 1 V for optimal operation. EEPROM_CRC, or SOFTSTART_FILTER_A flag is set. The ACSNS and OTW1 flags can also be programmed to be included. 8 CS1_A CS1 ADC Input and Fast Current Sense Input for Channel A. This signal is referenced to AGND. resistor divider network. The nominal voltage at this pin should be 1 V. This signal is referenced to AGND. 10 PSON_A Power Supply On Input for Channel A. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND. use. This signal is referenced to AGND.

Rev. A | Page 11 of 84 Pin No. Mnemonic Description 19 SDA PMBus/I2C Serial Data Input and Output (Open-Drain). This signal is referenced to AGND. 20 SCL PMBus/I2C Serial Clock Input and Output (Open-Drain). This signal is referenced to AGND. 21 PSON_B Power Supply On Input for Channel B. This signal is referenced to DGND. 22 CS CS ADC Input and Fast Current Sense Input for Overcurrent Protection and Current Monitoring. This signal is referenced to AGND. 23 CS1_B CS1 ADC Input and Fast Current Sense Input for Channel B. This signal is referenced to AGND. 24 PGOOD_B Power-Good Output (Open-Drain) for Channel B. This signal is referenced to AGND. This pin is controlled by the PGOOD_B flag and is driven low when the flag is set. The PGOOD_B flag is set when the POWER_SUPPLY_B, UVP_B, EEPROM_CRC, or SOFTSTART_FILTER_B flag is set. The ACSNS and OTW2 flags can also be programmed to be included. 25 CS2+_B Noninverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should be 1 V for optimal operation. 26 CS2−_B Inverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should be 1 V for optimal operation. 27 OVP_B Overvoltage Protection Comparator Input for Channel B. This signal is referenced to PGND_B. 28 PGND_B Reference Pin for Channel B Overvoltage Protection (OVP_B). 29 VS−_B Inverting Input of the Voltage Sense ADC for Channel B Loop Control. There should be a low ohmic connection to AGND. 30 VS+_B Noninverting Input of the Voltage Sense ADC for Channel B Loop Control. This signal is referenced to VS−_B. 31 FLGI/SYNI Flag Input/Synchronization Input. When this pin is programmed as a flag input, an external signal can be input to generate a flag condition. The polarity is configurable. When this pin is programmed as a synchronization input, the input signal is used as a reference for the internal PWM frequencies. This signal is referenced to AGND. 32 FLGO/SYNO Flag Output/Synchronization Output. When this pin is programmed as a flag output, it can be used to indicate the light load mode operation. The polarity is configurable. When this pin is programmed as a synchronization output, it can be used as a frequency reference for synchronization. This signal is referenced to AGND. 33 RTD2 Thermistor ADC Input from Zone 2. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed from this pin to AGND. This signal is referenced to AGND. 34 DGND IC Digital Ground. Reference ground for the digital circuitry of the ADP1053. This pin should be star-connected to AGND. 35 VCORE Output of 2.5 V Regulator. Connect a 330 nF capacitor between this pin and DGND. 36 VDD Positive Supply Voltage, 3.0 V to 3.6 V. This signal is referenced to AGND. Connect a 330 nF capacitor from VDD to AGND. 37 AGND IC Common Analog Ground. This pin should be star-connected to DGND. 38 RES Resistor Input. This pin sets the internal voltage reference for the ADP1053. Connect a 10 kΩ resistor (±1%) from RES to AGND. This signal is referenced to AGND. 39 ADD PMBus/I2C Address Select Input. Connect a resistor from ADD to AGND (see the PMBus/I2C Address section). This signal is referenced to AGND. 40 RTD1 Thermistor ADC Input from Zone 1. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed from this pin to AGND. This signal is referenced to AGND. EP Exposed Pad The exposed pad on the underside of the package should be soldered to AGND.

Figure 5. Application Circuit 1—Buck Preregulator Followed by a Fixed PWM Full-Bridge Topology with Synchronous Rectification

Figure 6. Application Circuit 2—Two Output Channels with Only One Full-Bridge Rectifier

time before the start of the switching cycle. Figure 9. SYNO Timing function, the synchronization function is disabled. Channel C has the lowest priority. internal frequency but not the operating switching frequency. synchronization clock is at 105 kHz. Figure 10. Synchronization Timing monitoring, control, and protection of the power supply output. see the Power Supply Calibration and Trim section. 16 readings per switching cycle.

6 BITS

Figure 11. Voltage Sense Configuration

points for the control loop. accuracy for the ADC reading. ADC2 for the high speed feedback loop. the noise is higher (see Figure 12). Figure 12. Noise Performance for Nyquist Rate and Σ-Δ ADCs ADP1053: a low frequency ADC and a high frequency ADC. Table 7. Equivalent Resolution for High Frequency ADC OVP flags, see the Overvoltage Protection (OVP) Flags section. power supply when the current exceeds the preset current limit. signals at the pins are fed into ADCs for current monitoring. sensing are shown in Figure 13 and Figure 14.

the CS2 (CS2_A/CS2_B) Readings section. driver circuit under extreme conditions.

12 BITS

Figure 17. SR FET Reverse Current Protection the VS_A and VS_B Readings section). the closed-loop operation until the GO command is executed. value before implementing it for closed-loop operation. flag is also set but is not cleared. unchanged, and the VS_SET_ERR_x flag is set. Register 0xFE86 (for VS_A) and Register 0xFE87 (for VS_B). ADP1053 adjusts the voltage setting with the preset slew rate.

light load conditions based on the value of CS2_A and CS2_B. reading of CS2_A and CS2_B, respectively. dently with Bits[3:0] of Register 0xFE1A and Register 0xFE1B.

• The LIGHTLOAD_A/LIGHTLOAD_B flag is set.
• The configured PWM outputs (programmable using Register 0xFE69 and Register 0xFE6A) are disabled.
• The feedback digital filter changes to the values for the light load condition. When a channel exits light load mode, the light load flag is cleared, the disabled PWM outputs are reenabled, and the feedback filter changes back to the values for normal mode. The signal at the FLGO/SYNO pin can be configured as a flag output by setting Bit 3 of Register 0xFE0F. This signal can be programmed to respond to either the LIGHTLOAD_A or LIGHTLOAD_B flag using Bit 4 of Register 0xFE0F. The polarity of the FLGO/SYNO pin can be set to inverted or noninverted using Bit 5 of Register 0xFE0F. ADP1053 VOUT FLGO/SYNO DRIVER DRIVER 10241-019 PWM OUTPUTS

Figure 20. Phase Shedding in Dual-Phase Buck Controller the PGOOD_A and PGOOD_B flags. 200 ms, 320 ms, or 600 ms using Register 0xFE09. register, depending on the configured settings in Register 0xFE7A. tied together and triggered by the same signal.

OUT3 and OUT4 are configured for negative modulation.

• OUT1: The rising edge is fixed. At the beginning of soft start, the falling edge is located at t F1 − tSS_C1 = 0, which means a zero duty cycle. The edge moves to the right during soft start and stops at the tF1 value of 4 μs.
• OUT2: The rising edge is fixed. At the beginning of soft start, the falling edge is located at t F2 − tSS_C2 = 4.8 μs, which means a zero duty cycle. The edge moves to the right during soft start and stops at the tF2 value of 8.8 μs.
• OUT3: The falling edge is fixed. At the beginning of soft start, the rising edge is located at tR3 − tSS_C1 = 0.2 μs. The edge moves to the right during soft start and stops at the t R3 value of 4.2 μs.
• OUT4: The falling edge is fixed. At the beginning of soft start, the rising edge is located at t R4 − tSS_C2 = 5 μs. The edge moves to the right during soft start and stops at the t R4 value of 9 μs. To implement soft start for Channel C using a different PWM timing configuration, the user can configure additional bit settings in Register 0xFE68.
• When Bit 3 is set, tSS_C1 is forced to follow tSS_C2.
• When Bit 2 is set, tSS_C2 = |tS − tR2|, where tS is the switching cycle for Channel C.
• When Bit 1 is set, tSS_C1 = |tF3 − tR3|.
• When Bit 0 is set, tSS_C2 = |tF4 − tR4|. Bits[7:6] of Register 0xFE68 are used to prevent the unintentional overlap of the PWM outputs, especially when synchronization is enabled. When Bit 7 is set, the falling edges of OUT1, OUT2, OUT5, and OUT6 are always after the rising edges in one cycle during soft start. Bit 6 is valid only when Bit 7 of Register 0xFE68 is set to 1. If Bit 6 is set to 0, the rising edges of OUT3, OUT4, OUT7, and OUT8 are always after the falling edges in one cycle during soft start. If Bit 6 is set to 1, the falling edges of OUT3, OUT4, OUT7, and OUT8 are always after the rising edges in one cycle during soft start. Flag Timing During Soft Start The user can program which flags are active during the soft start. All flags are active at the end of the soft start. For more information, see the Flag Blanking During Soft Start section. For either regulated channel of the ADP1053, the following procedure occurs after the user turns on the power supply (enables PSON_A or PSON_B). See Figure 22. 1. The PSON signal is enabled at t = t 0. The ADP1053 checks that initial flags are OK. 2. The ADP1053 waits for the tDON time before it begins to ramp up the power stage reference voltage at t1. 3. When the output voltage reaches a steady state, the soft start is completed, and the SOFTSTART_FILTER_A or SOFTSTART_FILTER_B flag is cleared. 4. The PGOOD signal waits for the t DGOOD time before it is enabled at t3. The values for tDON_A, tDON_B, tDGOOD_A, and tDGOOD_B are all programmable. tDON tDGOOD t0 t1 t2 t3 PSON VOUT SOFTSTART_ FILTER FLAG PGOOD POWER_ SUPPLY FLAG 10241-021

Figure 22. Soft Start Timing Diagram The restart delay time can be programmed using Register 0xFE88.

• The PGOOD_A or PGOOD_B fault flag is set.
• Depending on the fault and how it is configured, the POWER_SUPPLY_A or POWER_SUPPLY_B flag is enabled after a programmed time.

Rev. A | Page 24 of 84 Digital Filters During Soft Start A dedicated filter is used during soft start. The filter is disabled at the end of the soft start routine, after which the voltage loop digital filter is used. The soft start filter gain is programmable using Bits[1:0] of Register 0xFE3E and Register 0xFE3F. The soft start filter is used during the reference ramp time until the high frequency ADCs of VS_A/VS_B are settled. The user can program a debounce time for detecting the settling of the high frequency ADC using Bits[5:4] of Register 0xFE3E and Register 0xFE3F . The debounce time can be set to 5 ms or 10 ms with Bit 5. During the time that the soft start filter is used, the SOFTSTART_FILTER_x flag is set. SYNCHRONOUS RECTIFIER (SR) SOFT START The turning on of the synchronous rectification (SR) signals (OUT3, OUT4, OUT7, and OUT8) during a soft start can be programmed in two ways. The SR signals can either be turned on to their full PWM values immediately, or they can be turned on in a soft start fashion, which ensures a smooth output ramp during the soft start. SR soft start changes the rising edge of the PWM output. Note that the falling edge of an SR PWM output should not be modu- lated. When turned on in a soft start, the rising edge of the SR PWM output starts at the same instant as the falling edge, which means a zero duty cycle. The rising edge moves left in a step of 40 ns per 1, 4, 16, or 64 switching cycles (programmable using Register 0xFE67). In this way, the SR output ramps up from a zero duty cycle to the desired duty cycle. When the rising edge reaches 0, it wraps to restart at the end of the switching cycle. When the ADP1053 is programmed to use SR during soft start, the falling edge of SR outputs must be set to a lower value than the rising edge of the following PWM output. VOLT-SECOND BALANCE AND CURRENT BALANCE The ADP1053 has two dedicated circuits to maintain current balance/volt-second balance. To configure a PWM output for volt-second balance or current balance, program Bit 4 in the appropriate PWM output setting register. (The PWM output setting registers are Register 0xFE43, Register 0xFE47, Register 0xFE4B, Register 0xFE4F, Register 0xFE53, Register 0xFE57, Register 0xFE5B, and Register 0xFE5F .) Volt-second balance control can be disabled during soft start using Bit 3 of Register 0xFE08. The balance control gains are programmable in Register 0xFE72. The maximum modulation limit on the duty cycles is program- mable at 80 ns and 160 ns using Bit 6 of Register 0xFE72. When OUT1, OUT2, OUT3, and OUT4 are used for balance control, the user can enable or disable the rising and falling edges using Register 0xFE62 and Register 0xFE63. The direction of the modulation is also programmable. When OUT5, OUT6, OUT7, and OUT8 are used for balance control, the user can enable or disable the rising and falling edges using Register 0xFE64. The modulation direction is fixed. When OUT5 and OUT7 are used and edge modulation for balance control is enabled, increasing the balance control modulation moves the edge to the right. For OUT6 and OUT8, increasing the balance control modulation moves the edge to the left. Volt-Second Balancing (Based on CS Pin Signal) Volt-second balance control is based on the sensed signal at the CS pin following the rising edge of the OUT1 and OUT2 signals. When enabled, volt-second balance control makes the programmed adjustment to the enabled PWM edges. This feature can be effectively used in full-bridge applications, eliminating the need for a dc blocking capacitor. The circuit monitors the dc current flowing in both halves of the full bridge, stores this information, and compensates the PWM drive signals to ensure equal current flow in both halves of the full bridge. The time required for the circuit to operate effectively can be programmed and is typically in the range of 100 ms. Therefore, during a transient condition, the volt-second balance relies on the overcurrent condition to limit the PWM duty cycle. Volt-second balance control uses the CS signal; it can be assigned to Channel A or Channel C using Bit 7 of Register 0xFE72. When volt-second balance control is used, OUT1 and OUT2 must be assigned to the appropriate channel (Channel A or Channel C) because the balance control circuit looks only for the rising edges of OUT1 and OUT2 to start the balance control integration. When the CS signal in the half cycle after the rising edge of OUT1 is higher than the signal in the half cycle after the rising edge of OUT2, the modulation value increases. The PWM output edges move according to the values programmed in Register 0xFE62. Leading edge blanking functions can also be used at the sensed CS signals for more accurate control results. The blanking time follows the CS OCP blanking time. For more information, see the Overcurrent Protection (OCP) Flags section. Current Balancing (Based on CS1/CS2 Pin Signals) Current balancing with regulated feedback is designed for oper- ation in dual-phase, single-output topologies. Current balancing is implemented to control the balance between CS1_A and CS1_B or between CS2_A and CS2_B (use Bit 3 of Register 0xFE72 to select CS1_A/CS1_B or CS2_A/CS2_B). For dual-phase current balance control, when the CS1_A or CS2_A value is larger than the CS1_B or CS2_B value, the modulation value increases. The actions for different PWM output edges are programmable using Register 0xFE62, Register 0xFE63, and Register 0xFE64.

fault conditions are programmable. the thresholds and limits, see the Flag Registers section. scale range (FSR) of the signal that is measured. and Register 0xFED6, respectively) are updated every 10 ms. that the ADC output code is limited to 1.4 V/781.25 μV = 1792. By default, the current reading ADCs are updated every 10 ms. 100 kΩ thermistor, the voltage on the RTDx pin is 1 V at 25°C. pin. The ADC has a 1 kHz bandwidth and 12-bit resolution. section and the Temperature Linearization Scheme section. Figure 23. RTD Pin Internal Details

the average value at the end of the 10 ms period.

1.6 V and a resolution of 12 bits, which means that the LSB size

achieve linearization (see Figure 24). Figure 24. Temperature Measurement Using Thermistor (see the Calibrating for Accuracy section). (Register 0xFE80 and Register 0xFE81, respectively). temperatures in the industrial range. the Temperature Linearizat ion S cheme section. equation to match the specific NTC thermistor used. For example, at 60°C, the NTC at the RTDx pin is 21.82 kΩ. when linearizing measured temperatures in the industrial range. the value of the current source to 10 μA, 20 μA, 30 μA, or 40 μA. source set by Bits[7:6]; a decimal value of 63 adds 9.84375 μA. There is no negative adjustment to the current source. 0 causing error curves to shift accordingly). accuracy of these measurements. X is the temperature value in °C. the sign bit, which is always equal to 0. N is the twos complement integer exponent (Bits[15:11]). reading result is represented in 8-bit decimal format in °C. from Register 0xFED7 and Register 0xFED8.

• Housekeeping flags, such as VDD_OV , EEPROM_CRC, and EEPROM_UNLOCKED.
• Flags that can be programmed for protection responses, such as OVP_A, OVP_B, UVP_A, UVP_B, ACSNS, CS_OCP , CS1_A_OCP , CS1_B_OCP , CS2_A_OCP , CS2_B_OCP , OTP1, OTP2, FLAGIN, REVERSE_A, and REVERSE_B.
• Status flags, such as PGOOD_A, PGOOD_B, POWER_ SUPPLY_A, POWER_SUPPLY_B, POWER_SUPPLY_C, MODULATION_A, MODULATION_B, SOFTSTART_ FILTER_A, SOFTSTART_FILTER_B, VS_SET_ERR_A, VS_SET_ERR_B, LIGHTLOAD_A, LIGHTLOAD_B, FLAGOUT, OTW1, and OTW2. For detailed descriptions of the flags, see the Flag Registers section. The debounce time of some flags is programmable (see Table 9). The debounce time is the time during which the fault condition must be continuously triggered before the flag is set. Refer to the corresponding register settings for details.

Table 9. Debounce Time of Flags more information, see the Protection Actions section. cleared regardless of the VDD voltage. requires a PSON_A/PSON_B reset to restart. 0xFE26 for Channel A and Register 0xFE27 for Channel B. Actions section and the Flag Configuration Registers section. Note that UVP is ignored when its threshold value is set to 0. is an additional debounce and delay time of up to 10 ms.

for this flag can be set to 0 μs or 100 μs using Register 0xFE0F. Actions section and the Flag Configuration Registers section. down the part and restart it using Bit 5 of Register 0xFE06. OTP2, FLAGIN, REVERSE_A, and REVERSE_B.

• No action (flag ignored).
• Disable PWM outputs in Channel A.
• Disable PWM outputs in Channel B.
• Disable all PWM outputs. After the condition that triggered one of these flags is resolved and the flag is cleared, the ADP1053 can be programmed to respond as follows:
• Reenable the disabled PWM outputs immediately with no soft start.
• After the reenable delay time elapses, reenable the disabled PWM outputs with a soft start sequence.
• Keep the PWM outputs disabled; the PSON signal must be used to reenable the PWM outputs with a soft start sequence. — If the flag action is to disable the PWM outputs in Channel A, resetting PSON_A reenables the disabled PWM outputs. — If the flag action is to disable the PWM outputs in Channel B, resetting PSON_B reenables the disabled PWM outputs. — If the flag action is to disable all PWM outputs, resetting both PSON_A and PSON_B reenables all PWM outputs. The first flag with an action that causes the PWM outputs to be disabled and a resolution that includes a soft start is recorded as the first flag ID. For more information, see the First Flag ID Recording section. A reenable delay can be set for all flags; this delay is used if the configured action for a flag is to reenable the PWM outputs after the reenable delay. This delay can be set to 250 ms, 500 ms, 1 sec, or 2 sec using Bits[7:6] of Register 0xFE06 (see Figure 28). An additional PSON delay can be added to the reenable delay for each channel using Bits[7:5] of Register 0xFE7B. This delay is used to control the turn-on timing of different channels. t0 t1 tD_REENABLE OR tD_REENABLE + tD_PSON FLAG VOUT 10241-026

Figure 28. Flag Reenable Delay be programmed to be blanked using Bit 6 of Register 0xFE08. the soft start (see the Flag Blanking During Soft Start section). corresponding flag is set but there are no related actions.

• FLAGIN, OTP1, OTP2, and ACSNS flags (all channels)
• UVP_A and REVERSE_A (Channel A)
• UVP_B and REVERSE_B (Channel B) The following flags can be programmed to be blanked during soft start using Register 0xFE07.
• CS_OCP flag (Channel C)
• OVP_A, CS1_A_OCP , and CS2_A_OCP flags (Channel A)
• OVP_B, CS1_B_OCP , and CS2_B_OCP flags (Channel B) Note that if a flag is blanked during soft start, it is also blanked during the PSON delay time. LATCHED FLAGS The ADP1053 also has a set of latched flag registers (Register 0xFEC5 to Register 0xFEC9). Flags in a latched flag register remain set so that intermittent faults can be detected. Reading a latched flag register resets the flags in that register (provided that the fault no longer exists). A PSON signal can also reset the latched flags.
• PSON_A resets the flags in Register 0xFEC5, Register 0xFEC7, Register 0xFEC8, and Register 0xFEC9.
• PSON_B resets the flags in Register 0xFEC6 through Register 0xFEC9.

• Flags that are configured to be ignored
• Flags whose configured action causes PWM outputs to be disabled but which do not use a soft start to reenable the PWM outputs after the fault is resolved For more information, see the Protection Actions section. The first flag ID registers give the user more information for fault diagnosis than a simple flag. These registers also store the previous first flag ID. The status of the first flag ID registers can be downloaded to the EEPROM (set Bit 5 of Register 0xFE08). The contents of the first flag ID registers are stored until read by the user. The flag ID is also saved in EEPROM. In this way, the user can read the flag information even if the ADP1053 is powered off.

Figure 29. First Flag ID Timing the first flag ID of the fault that shut down Channel B. Bit 5 to 0 in Register 0xFE08. Table 10. First Flag ID Timing EEPROM is then updated to save this information. the EEPROM is then updated to save this information.

Rev. A | Page 32 of 84 POWER SUPPLY CALIBRATION AND TRIM The ADP1053 allows the entire power supply to be calibrated and trimmed digitally in the production environment. It can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors, current transformers, and resistor dividers, as well as for its own internal circuitry. The part comes factory trimmed, but it can be retrimmed by the user to compensate for the errors introduced by external components in the system. To unlock the trim registers for write access, write to the TRIM_PASSWORD register (Command 0xD6). Write the trim password twice (the factory default password is 0xFF). The trim registers are Register 0xFE10 through Register 0xFE17, Register 0xFE1C, Register 0xFE1D, Register 0xFE6E, Register 0xFE73, Register 0xFE74, Register 0xFE77, and Register 0xFE7C through Register 0xFE7F. For complete information about these registers, see the Manufacturer-Specific Extended Command Register Descriptions section. CS, CS1_A, AND CS1_B GAIN TRIM To calibrate the CS, CS1_A, and CS1_B ADCs, 1 V is applied between the CS/CS1_A/CS1_B pin and AGND. The CS/CS1_A/ CS1_B gain trim register (Register 0xFE6E, Register 0xFE10, or Register 0xFE11, respectively) is altered until the CS/CS1_A/ CS1_B value in the appropriate value register reads 2560 decimal (0xA00). The CS, CS1_A, and CS1_B value registers are Register 0xFED0, Register 0xFED1, and Register 0xFED2, respectively. CS2_A AND CS2_B OFFSET AND GAIN TRIM CS2_A and CS2_B Offset Trim Offset errors are caused by the combined mismatch of the external level-shifting resistors and internal current sources. The offset trim has both an analog and a digital component. With 0 V at the CS2 input, the desired ADC reading is 0 LSB. The analog offset trim is performed to achieve a differential input voltage of 0 V . The digital offset trim is performed to achieve an ADC reading of 0 LSB. It is important to perform the offset trim in the following order. 1. Select high-side or low-side current sensing using Register 0xFE1A or Register 0xFE1B. 2. Set the digital offset trim setting to 0x00 using Register 0xFE14 or Register 0xFE15. 3. Adjust the CS2 analog offset trim value (Register 0xFE16 or Register 0xFE17) until the CS2 value in Register 0xFED3 or Register 0xFED4 reads as close to 100 decimal as possible. 4. Increase the CS2 digital offset trim register value (Register 0xFE14 or Register 0xFE15) until the CS2 value in Register 0xFED3 or Register 0xFED4 reads 0. The offset trim is now complete. With 0 V at the CS2 input, the ADC code now reads 0. CS2_A and CS2_B Gain Trim The gain trim removes any errors introduced by the sense resistor tolerance. 1. Apply a known current (IOUT) across the sense resistor. 2. Adjust the CS2 gain trim value in Register 0xFE12 or Register 0xFE13 until the CS2 value in Register 0xFED3 or Register 0xFED4 reads the value calculated by this formula: CS2 Value = I OUT × RSENSE × (4096/120 mV) where RSENSE is the sense resistor value. For example, if IOUT = 4.64 A and RSENSE = 20 mΩ, CS2 Value = 4.64 A × 20 mΩ × (4096/120 mV) = 3168 (decimal). The CS2 circuit is now trimmed. After the current sense trim is performed, the OCP limits and settings should be configured. VS_A AND VS_B GAIN TRIM The voltage sense inputs are optimized for sensing signals at 1 V and cannot sense a signal greater than 1.5 V . In a 28 V system, a resistor divider is required to reduce the 28 V signal to below 1.5 V . It is recommended that the 28 V signal be reduced to 1 V for best performance. The resistor divider can introduce errors, which need to be trimmed. The ADCs output a digital word of 2560 decimal (0xA00) when there is exactly 1 V at their inputs. ACSNS GAIN TRIM The voltage sense inputs are optimized for ACSNS pin signals at 1 V and cannot sense a signal greater than 1.5 V . A resistor divider is required to reduce the sensed voltage signal to below 1.5 V . It is recommended that the ACSNS voltage signal be reduced to 1 V for best performance. The resistor divider can introduce errors, which need to be trimmed. The following procedure should be used: 1. Apply nominal voltage at the sense point to achieve a voltage of approximately 1 V at the ACSNS pin. 2. Adjust the ACSNS gain trim register (Register 0xFE77) until the ACSNS reading in Register 0xFED9 is 0x500 (1280 decimal).

Rev. A | Page 33 of 84 RTD1, RTD2, OTP1, AND OTP2 TRIM The following procedure should be used: 1. Heat the thermistor or power supply to a known tempera- ture that is equal to the OTP threshold. 2. Adjust the RTD1 or RTD2 gain trim register (Register 0xFE73 or Register 0xFE74) until the RTD1 or RTD2 value register (Register 0xFED7 or Register 0xFED8) gives the correct temperature reading at this temperature. 3. Adjust the OTP1 or OTP2 threshold register (Register 0xFE75 or Register 0xFE76) until the OTP1 or OTP2 flag is set. This procedure achieves the most accurate OTP , because it takes into account the part-to-part variations of the ADP1053 and the thermistor used. LAYOUT GUIDELINES This section explains best practices that should be followed to ensure optimal performance of the ADP1053. In general, all related control components should be placed as close to the ADP1053 as possible. CS2+_A, CS2+_B, CS2−_A, and CS2−_B The routing of the tracks from the sense resistor to the ADP1053 should be laid out in parallel to each other. The tracks should be kept close together and as far from switch nodes as possible. VS+_A, VS+_B, VS−_A, and VS−_B The routing of the tracks from the remote voltage sense point to the ADP1053 should be laid out in parallel to each other. The tracks should be kept close together and as far from switch nodes as possible. VDD Place decoupling capacitors as close to the part as possible. A 330 nF capacitor from VDD to AGND is recommended. SDA and SCL The routing of the tracks should be laid out in parallel to each other. The tracks should be kept close together and as far from switch nodes as possible. CS, CS1_A, and CS1_B Run the tracks from the current sense transformer to the ADP1053 in parallel to each other. The tracks should be kept close together and as far from switch nodes as possible. Exposed Pad The exposed pad underneath the ADP1053 should be soldered to AGND. VCORE Place the 330 nF capacitor to DGND as close to the part as possible. RES Place the 10 kΩ resistor to AGND as close to the part as possible. RTD1 and RTD2 Route a single trace to the ADP1053 from the thermistors. Place the thermistors close to the hottest part of the power supply. AGND Create an AGND ground plane and make a single-point (star) connection to the power supply system ground.

Rev. A | Page 34 of 84 PMBus/I2C COMMUNICATION The PMBus slave allows a device to interface to a PMBus- compliant master device, as specified by the PMBus Power System Management Protocol Specification (Revision 1.1, February 5, 2007). The PMBus slave is a 2-wire interface that can be used to communicate with other PMBus-compliant devices and is compatible in a multimaster, multislave bus configuration. The function of the PMBus slave is to decode the command sent from the master device and respond as requested. Communi- cation is established using an I2C-like 2-wire interface with a clock line (SCL) and data line (SDA). The PMBus slave is designed to externally move chunks of 8-bit data (bytes) while maintaining compliance with the PMBus protocol. The PMBus protocol is based on the SMBus Specification (Version 2.0, August 2000). The SMBus specification is, in turn, based on the Philips I 2C Bus Specification (Version 2.1, January 2000). The PMBus incorporates the following features:

• Slave operation on multiple device systems
• 7-bit addressing
• 100 kHz and 400 kHz data rates
• General call address support
• Support for clock low extension (clock stretching)
• Separate multibyte receive and transmit FIFO
• Extensive fault monitoring OVERVIEW The PMBus slave module is a 2-wire interface that can be used to communicate with other PMBus-compliant devices. Its trans- fer protocol is based on the Philips I2C transfer mechanism. The ADP1053 is always configured as a slave device in the overall system. The ADP1053 communicates with the master device using one data pin (SDA) and one clock pin (SCL). Because the ADP1053 is a slave device, it cannot generate the clock signal. However, it is capable of clock-stretching the SCL line to put the master device in a wait state when it is not ready to respond to the master’s request. Communication is initiated when the master device sends a command to the PMBus slave device. Commands can be read or write commands, in which case data is transferred between the devices in a byte wide format. Commands can also be send commands, in which case the command is executed by the slave device upon receiving the stop bit. The stop bit is the last bit in a complete data transfer, as defined in the PMBus/I 2C communi- cation protocol. During communication, the master and slave devices send acknowledge (A) or not-acknowledge (A) bits as a method of handshaking between devices. See the PMBus speci- fication for a more detailed description of the communication protocol. When communicating with the master device, it is possible for illegal or corrupted data to be received by the PMBus slave device. In this case, the PMBus slave device should respond to the invalid command or data, as defined by the PMBus specifi- cation, and indicate to the master device that an error or fault condition has occurred. This method of handshaking can be used as a first level of defense against inadvertent programming of the slave device that can potentially damage the chip or system. The PMBus specification defines a set of generic PMBus commands that is recommended for a power management system. However, each PMBus device manufacturer can choose to implement and support certain commands as it deems fit for its system. In addition, the PMBus device manufacturer can choose to implement manufacturer-specific commands whose functions are not included in the generic PMBus command set. The list of standard PMBus and manufacturer-specific commands can be found in the PMBUS Command Set (Supported by the ADP1053) section and the Manufacturer-Specific Extended Command List section. PMBus/I2C ADDRESS The PMBus address of the ADP1053 is set by connecting an external resistor from the ADD pin to AGND. Table 11 lists the recommended resistor values and associated PMBus addresses. Seven different addresses can be used.

Table 11. PMBus Address Settings and Resistor Values The recommended resistor values in Table 11 can vary by ±2 kΩ. multiple slave devices will be corrupted. For more information, see the General Call Support section.

Rev. A | Page 37 of 84 DATA TRANSMISSION FAULTS Data transmission faults occur when two communicating devices violate the PMBus communication protocol, as specified in the PMBus specification. See the PMBus specification for more information about each fault condition. Corrupted Data, PEC (Item 10.8.1) Parity error checking. Not supported. Sending Too Few Bits (Item 10.8.2) Transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been sent. Not supported; any transmitted data is ignored. Reading Too Few Bits (Item 10.8.3) Transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been read. Not supported; any received data is ignored. Host Sends or Reads Too Few Bytes (Item 10.8.4) If a host ends a packet with a stop condition before the required bytes are sent/received, it is assumed that the host intended to stop the transfer. Therefore, the PMBus does not consider this to be an error and takes no action, except to flush any remain- ing bytes in the transmit FIFO. Host Sends Too Many Bytes (Item 10.8.5) If a host sends more bytes than are expected for the corre- sponding command, the PMBus slave considers this a data transmission fault and responds as follows:

• NACKs all unexpected bytes as they are received
• Flushes and ignores the received command and data
• Sets the CML bit in the STATUS_BYTE register Host Reads Too Many Bytes (Item 10.8.6) If a host reads more bytes than are expected for the corre- sponding command, the PMBus slave considers this a data transmission fault and responds as follows:
• Sends all 1s (0xFF) as long as the host continues to request data
• Sets the CML bit in the STATUS_BYTE register Device Busy (Item 10.8.7) The PMBus slave device is too busy to respond to a request from the master device. Not supported. DATA CONTENT FAULTS Data content faults occur when data transmission is successful, but the PMBus slave device cannot process the data that is received from the master device. Improperly Set Read Bit in the Address Byte (Item 10.9.1) All PMBus commands start with a slave address with the R/W bit cleared (set to 0), followed by the command code. If a host starts a PMBus transaction with R/W set in the address phase (equivalent to an I2C read), the PMBus slave considers this a data content fault and responds as follows:
• ACKs the address byte
• NACKs the command and data bytes
• Sends all 1s (0xFF) as long as the host continues to request data
• Sets the CML bit in the STATUS_BYTE register Invalid or Unsupported Command Code (Item 10.9.2) If an invalid or unsupported command code is sent to the PMBus slave, the code is considered to be a data content fault, and the PMBus slave responds as follows:
• NACKs the illegal/unsupported command byte and data bytes
• Flushes and ignores the received command and data
• Sets the CML bit in the STATUS_BYTE register Reserved Bits (Item 10.9.5) Accesses to reserved bits are not a fault. Writes to reserved bits are ignored, and reads from reserved bits return 0. Write to Read-Only Commands If a host performs a write to a read-only command, the PMBus slave considers this a data content fault and responds as follows:
• NACKs all unexpected data bytes as they are received
• Flushes and ignores the received command and data
• Sets the CML bit in the STATUS_BYTE register Note that this is the same error described in the Host Sends Too Many Bytes (Item 10.8.5) section. Read from Write-Only Commands If a host performs a read from a write-only command, the PMBus slave considers this a data content fault and responds as follows:
• Sends all 1s (0xFF) as long as the host continues to request data
• Sets the CML bit in the STATUS_BYTE register Note that this is the same error described in the Host Reads Too Many Bytes (Item 10.8.6) section.

Rev. A | Page 38 of 84 EEPROM The ADP1053 has a built-in EEPROM controller that is used to communicate with the embedded 8K × 8-byte EEPROM. The EEPROM, also called Flash®/EE, is partitioned into two major blocks: the INFO block and the main block. The INFO block contains 128 8-bit bytes, and the main block contains 8K 8-bit bytes. The main block is further partitioned into 16 pages, each page containing 512 bytes. The function of the EEPROM controller is to decode the operation that is requested by the ADP1053 and to provide the required timing to the EEPROM interface. Data is written to or read from the EEPROM, as requested by the decoded command. Features of the EEPROM controller include

• Separate page erase functions for each page in the EEPROM
• Single-byte and multibyte (block) read of the INFO block with up to 128 bytes at a time
• Single-byte and multibyte (block) write and read of the main block with up to 256 bytes at a time
• Automatic upload on start-up from the user settings to the internal registers
• Separate commands to upload and download data from the factory default or user settings to the internal registers OVERVIEW The EEPROM controller provides an interface between the ADP1053 core logic and the built-in EEPROM. The user can control data access to and from the EEPROM through this controller interface. Separate PMBus commands are available for the read, write, and erase operations to the EEPROM. Communication is initiated by the master device sending a command to the PMBus slave device to access data from or send data to the EEPROM. Read, write, and erase commands are supported. Data is transferred between devices in a byte wide format. Using a read command, data is received from the EEPROM and transmitted to the master device. Using a write command, data is received from the master device and stored in the EEPROM through the EEPROM controller. PAGE ERASE OPERATION INFO Block Page Erase The INFO block consists of 128 bytes organized as a single page. The page erase operation to the INFO block erases (sets high) all bits of the 128-byte page. The INFO block erase oper- ation is part of a sequence of actions that occurs when the first flag information is saved into the EEPROM. Essentially, the page is first erased before the contents of the first flag registers are written to the erased page. There is no separate command to erase the INFO block. Main Block Page Erase The main block consists of 16 equivalent pages of 512 bytes each, numbered Page 0 to Page 15. Page 0 and Page 1 of the main block are reserved for storing the default settings and user settings, respectively. The user cannot perform a page erase operation to Page 0 or Page 1. Page 2 and Page 3 are reserved for internal use, and their contents should not be erased. Only Page 4 to Page 15 of the main block should be used to store data. To erase any page from Page 4 to Page 15, the EEPROM must first be unlocked for access. For instructions on how to unlock the EEPROM, see the Unlock the EEPROM section. Page 4 to Page 15 of the main block can be individually erased using the EEPROM_PAGE_ERASE command (Command 0xD4). For example, to perform a page erase of Page 10, execute the following command: ASP AAD ATA BYTEW7-BIT SLAVE ADDRESS COMMAND CODE MASTER TO SLAVE SLAVE TO MASTER 10241-028

Figure 38. Example Erase Command In this example, Command Code = 0xD4 and Data Byte = 0x0A. operation to complete before executing the next PMBus command. must first be erased (set high) for that byte to be writable. as that byte has not been written to a low previously. read, starting from the first byte of the page.

1. Set number of return bytes = 2.

Rev. A | Page 39 of 84 3. Read two bytes from the INFO block. RS AAAS r0xF1W7-BIT SLAVE ADDRESS 7-BIT SLAVE ADDRESS PABYTE COUNT = 0x80 DATA BYTE

1 AA DATA BYTE

Note that the block read command to the INFO block can read a maximum of 128 bytes. However, only the first two bytes are used to store the first flag information. Read from Main Block, Page 0 and Page 1 Page 0 and Page 1 of the main block are reserved for storing the default settings and user settings, respectively, and are meant to prevent third-party access to this data. To read from Page 0 or Page 1, the user must first unlock the EEPROM (see the Unlock the EEPROM section). After the EEPROM is unlocked, Page 0 and Page 1 are readable using the EEPROM_DATA_xx commands, as described in the Read from Main Block, Page 2 to Page 15 section. Note that when the EEPROM is locked, a read from Page 0 or Page 1 returns invalid data. Read from Main Block, Page 2 to Page 15 Data in Page 2 to Page 15 of the main block is always readable, even with the EEPROM locked. The data in the EEPROM main block can be read one byte at a time or in multiple bytes in series using the EEPROM_DATA_xx commands (Command 0xB0 to Command 0xBF). Before executing this command, the user must program the number of bytes to read using the EEPROM_NUM_RD_BYTES command (Command 0xD2). The user can also program the offset from the page boundary where the first read byte is returned using the EEPROM_ADDR_OFFSET command (Command 0xD3). In the following example, three bytes from Page 4 are read from the EEPROM, starting from the fifth byte of that page. 1. Set number of return bytes = 3. ASP AA0 x030xD2W7-BIT SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER 10241-032 2. Set address offset = 5. AS PAAA 0x00 0x050xD3W7-BIT SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER 10241-033 3. Read three bytes from Page 4. RS AAAS r0xB4W7-BIT SLAVE ADDRESS 7-BIT SLAVE ADDRESS PA. ..BYTE COUNT = 0x03 DATA BYTE Note that the block read command can read a maximum of 256 bytes for any single transaction. WRITE OPERATION (BYTE WRITE AND BLOCK WRITE) Write to INFO Block The user cannot write directly to the INFO block; this block is used by the ADP1053 to store the first flag information (see the First Flag ID Recording section). Write to Main Block, Page 0 and Page 1 Page 0 and Page 1 of the main block are reserved for storing the default settings and user settings, respectively. The user cannot perform a direct write operation to Page 0 or Page 1 using the EEPROM_DATA_xx commands. A user write to Page 0 or Page 1 returns a not-acknowledge. To program the register contents of Page 1 of the main block, it is recommended that the STORE_ USER_ALL command be used (Command 0x15). See the Save Register Settings to User Settings section. Write to Main Block, Page 2 and Page 3 Page 2 and Page 3 of the main block are reserved for internal use and their contents should not be written to. Only Page 4 to Page 15 should be used to store data. Write to Main Block, Page 4 to Page 15 Before performing a write to Page 4 through Page 15 of the main block, the user must first unlock the EEPROM (see the Unlock the EEPROM section). Data in Page 4 to Page 15 of the EEPROM main block can be programmed (written to) one byte at a time or in multiple bytes in series using the EEPROM_DATA_xx commands (Command 0xB0 to Command 0xBF). Before executing this command, the user can program the offset from the page boundary where the first byte is written using the EEPROM_ ADDR_OFFSET command (Command 0xD3). If the targeted page has not yet been erased, the user can erase the page as described in the Main Block Page Erase section. In the following example, four bytes are written to Page 9, starting from the 256 th byte of that page. 1. Set address offset = 256. AS PAAA 0x01 0x000xD3W7-BIT SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER 10241-035 2. Write four bytes to Page 9. ASA A BYTE COUNT = 40xB9W7-BIT SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER PAA. . .DATA BYTE 1 DATA BYTE 4 10241-036 Note that the block write command can write a maximum of 256 bytes for any single transaction.

Rev. A | Page 40 of 84 EEPROM PASSWORD On power-up, the EEPROM is locked and protected from accidental writes or erases. Only reads from Page 2 to Page 15 are allowed when the EEPROM is locked. Before any data can be written (programmed) to the EEPROM, the EEPROM must be unlocked for write access. After it is unlocked, the EEPROM is opened for reading, writing, and erasing. On power-up, Page 0 and Page 1 are also protected from read access, and the EEPROM must first be unlocked to read these pages. Unlock the EEPROM To unlock the EEPROM, perform two consecutive writes with the correct password (default = 0xFF) using the EEPROM_ PASSWORD command (Command 0xD5). The EEPROM_ UNLOCKED flag (Bit 4 of Register 0xFEC3) is set to indicate that the EEPROM is unlocked for write access. Lock the EEPROM To lock the EEPROM, write any byte other than the correct password using the EEPROM_PASSWORD command (Command 0xD5). The EEPROM_UNLOCKED flag is cleared to indicate that the EEPROM is locked from write access. Change the EEPROM Password To change the EEPROM password, first write the correct password using the EEPROM_PASSWORD command (Command 0xD5). Immediately write the new password using the same command. The password is now changed to the new password. DOWNLOADING EEPROM SETTINGS TO INTERNAL REGISTERS Download User Settings to Registers The user settings are stored in Page 1 of the EEPROM main block. These settings are downloaded from the EEPROM into the registers under the following conditions:

• On power-up. The user settings are automatically down- loaded into the internal registers, powering the part up in a state previously saved by the user.
• On execution of the RESTORE_USER_ALL command (Command 0x16). This command allows the user to force a download of the user settings from Page 1 of the EEPROM main block into the internal registers. Download Factory Default Settings to Registers The factory default settings are stored in Page 0 of the EEPROM main block. The factory default settings can be downloaded from the EEPROM into the internal registers using the RESTORE_ DEFAULT_ALL command (Command 0x12). When this command is executed, the EEPROM password is also reset to the factory default setting of 0xFF. SAVING REGISTER SETTINGS TO THE EEPROM The register settings cannot be saved to the factory default set- tings located in Page 0 of the EEPROM main block. This is to prevent the user from accidentally overriding the factory trim settings and default register settings. Save Register Settings to User Settings The register settings can be saved to the user settings located in Page 1 of the EEPROM main block using the STORE_USER_ALL command (Command 0x15). Before this command can be executed, the EEPROM must first be unlocked for writing (see the Unlock the EEPROM section). After the register settings are saved to the user settings, any subsequent power cycle automatically downloads the latest stored user information from the EEPROM into the internal registers. Note that execution of the STORE_USER_ALL command auto- matically performs a page erase to Page 1 of the EEPROM main block, after which the register settings are stored in the EEPROM. Therefore, it is important to wait at least 35 ms for the operation to complete before executing the next PMBus command. EEPROM CRC CHECKSUM As a simple method of checking that the values downloaded from the EEPROM are consistent with the internal registers, a CRC checksum is implemented.
• When the data from the internal registers is saved to the EEPROM (Page 1 of the main block), the total number of 1s from all the registers is counted and written into the EEPROM as the last byte of information. This is called the CRC checksum.
• When the data is downloaded from the EEPROM into the internal registers, a similar counter that sums all 1s from the values loaded into the registers is saved. This value is compared with the CRC checksum from the previous upload operation. If the values match, the download operation was successful. If the values differ, the EEPROM download operation failed, and the EEPROM_CRC fault flag is set (Bit 1 of Register 0xFEC2). To read the EEPROM CRC checksum value, execute the EEPROM_CRC_CHKSUM command (Command 0xD1). This command returns the CRC checksum accumulated in the counter during the download operation. Note that the CRC checksum is an 8-bit cyclical accumulator that wraps around to 0 when 255 is reached.

dramatically reduces power supply design and development time. for the latest software and a user guide. Figure 39. ADP1053 GUI, PWM Setup Window

registers, which share the same hexadecimal value as the PMBus command code. Table 12. PMBus Command List 0x03 CLEAR_FAULTS Send byte 0 Clear all fault bits in the STATUS_WORD register. 0x15 STORE_USER_ALL Send byte 0 Save user settings from registers to EEPROM (Page 1). EEPROM must first be unlocked. 0x16 RESTORE_USER_ALL Send byte 0 Download user settings from EEPROM (Page 1) to registers. 0x19 CAPABILITY Read byte 1 Allow host system to determine capabilities of PMBus device. 0x78 STATUS_BYTE Read byte 1 Return low byte of STATUS_WORD. 0x79 STATUS_WORD Read word 2 Return low byte and high byte of STATUS_WORD. 0x8D READ_TEMPERATURE_1 Read word 2 Return temperature reading (in degrees Celsius). READ_TEMPERATURE_1 = Y × 2N. 0x8E READ_TEMPERATURE_2 Read word 2 Return temperature reading (in degrees Celsius). READ_TEMPERATURE_2 = Y × 2N. 0x98 PMBUS_REVISION Read byte 1 Read PMBus revision that device is compliant with. 0x99 MFR_ID Read block 1 Read manufacturer’s ID. 0x9A MFR_MODEL Read block 1 Read manufacturer’s device model number. 0x9B MFR_REVISION Read block 1 Read manufacturer’s device revision number. 0xB0 EEPROM_DATA_00 Read block Variable Block read from Page 0. EEPROM must first be unlocked. 0xB1 EEPROM_DATA_01 Read block Variable Block read from Page 1. EEPROM must first be unlocked. for write. Page 2 should not be written to. for write. Page 3 should not be written to.

Rev. A | Page 43 of 84 Command Code Command Name SMBus Transaction Type Number of Data Bytes Description 0xD1 EEPROM_CRC_CHKSUM Read byte 1 Return CRC checksum value from EEPROM download operation. 0xD2 EEPROM_NUM_RD_BYTES Read/write byte 1 Set number of read bytes returned when using the EEPROM_DATA_xx commands. 0xD3 EEPROM_ADDR_OFFSET Read/write word 2 Set address offset of current EEPROM page. 0xD4 EEPROM_PAGE_ERASE Write byte 1 Perform page erase on selected page (Page 4 to Page 15). Wait 35 ms for each page erase operation. EEPROM must first be unlocked. Page 0 and Page 1 erase is not allowed. 0xD5 EEPROM_PASSWORD Write byte 1 Write the password to this register twice to unlock the EEPROM and/or change the EEPROM password. 0xD6 TRIM_PASSWORD Write byte 1 Write the password to this register twice to unlock the trim registers for write access. 0xF1 EEPROM_INFO Read/write block Variable Read first flag information.

Table 13. Manufacturer-Specific Extended Command List

Rev. A | Page 45 of 84 Command Name 0xFE58 OUT7 rising edge timing (MSBs) 0xFE59 OUT7 falling edge timing (MSBs) 0xFE5A OUT7 rising and falling edge timing (LSBs) 0xFE5B OUT7 settings 0xFE5C OUT8 rising edge timing (MSBs) 0xFE5D OUT8 falling edge timing (MSBs) 0xFE5E OUT8 rising and falling edge timing (LSBs) 0xFE5F OUT8 settings 0xFE60 PWM output pin disable GO Command Register 0xFE61 GO commands Balance Control Registers 0xFE62 Balance control on OUT1 and OUT2 0xFE63 Balance control on OUT3 and OUT4 0xFE64 Balance control on OUT5, OUT6, OUT7, and OUT8 Synchronization Setting Registers 0xFE65 OUT1 and OUT2 shutdown in Channel C synchronization 0xFE66 OUT1 through OUT8 dead time adjustment in synchronization SR and Channel C Soft Start Setting Registers 0xFE67 Synchronous rectifier (SR) soft start 0xFE68 Channel C soft start Light Load PWM Disable Registers 0xFE69 Channel A light load mode PWM output disable 0xFE6A Channel B light load mode PWM output disable Fast OCP and Channel C Current Sense Setting Registers 0xFE6B CS1_A blanking reference edge 0xFE6C CS1_B blanking reference edge 0xFE6D OUT3, OUT4, OUT7, and OUT8 cycle-by-cycle OCP response 0xFE6E CS gain trim 0xFE6F CS OCP settings 0xFE70 CS1_A OCP settings 0xFE71 CS1_B OCP settings 0xFE72 Balance control settings Temperature Sense and Protection Setting Registers 0xFE75 OTP1 threshold 0xFE76 OTP2 threshold ACSNS and Feedforward Setting Registers 0xFE77 ACSNS gain trim 0xFE78 ACSNS setting PSON Registers 0xFE79 Channel A PSON setting 0xFE7A Channel B PSON setting 0xFE7B Additional flag reenable delay and Channel C PSON setting Command Name RTD Trim Registers 0xFE73 RTD1 gain trim 0xFE74 RTD2 gain trim 0xFE7C RTD1 offset trim (MSB) 0xFE7D RTD1 offset trim (LSBs) 0xFE7E RTD2 offset trim (MSB) 0xFE7F RTD2 offset trim (LSBs) 0xFE80 RTD1 current source settings 0xFE81 RTD2 current source settings Customized Registers 0xFE82 Custom register 0xFE83 REVERSE_A/REVERSE_B flag configuration 0xFE84 REVERSE_A flag settings 0xFE85 REVERSE_B flag settings 0xFE86 VS_A slew rate for output voltage adjustment 0xFE87 VS_B slew rate for output voltage adjustment 0xFE88 Power supply software reset control 0xFE89 CS, CS1, and CS2 ADC update rate 0xFE8A OTW1/OTW2 settings Flag Registers 0xFEC0 Flag Register 1 0xFEC1 Flag Register 2 0xFEC2 Flag Register 3 0xFEC3 Flag Register 4 0xFEC4 Flag Register 5 0xFEC5 Latched Flag Register 1 0xFEC6 Latched Flag Register 2 0xFEC7 Latched Flag Register 3 0xFEC8 Latched Flag Register 4 0xFEC9 Latched Flag Register 5 0xFECA Channel A first flag ID 0xFECB Channel B first flag ID Value Registers 0xFED0 CS value 0xFED1 CS1_A value 0xFED2 CS1_B value 0xFED3 CS2_A value 0xFED4 CS2_B value 0xFED5 VS_A value 0xFED6 VS_B value 0xFED7 RTD1 value 0xFED8 RTD2 value 0xFED9 ACSNS value 0xFEDA Channel A duty cycle value 0xFEDB Channel B duty cycle value

Command 0x03, send byte, no data. This command clears all fault bits in the STATUS_WORD register. Table 14. Command 0x10—WRITE_PROTECT 7 Write Protect 1 R/W Setting this bit disables writes to all commands except for WRITE_PROTECT. 6 Write Protect 2 R/W Setting this bit disables writes to all commands except for WRITE_PROTECT, OPERATION, and PAGE. ON_OFF_CONFIG, and VOUT_COMMAND. Command 0x12, send byte, no data. This command downloads the factory default settings from EEPROM (Page 0) into operating memory. Command 0x15, send byte, no data. This command copies the entire contents of operating memory into EEPROM (Page 1 of the main block). The EEPROM must first be unlocked. This command allows host systems to determine the capabilities of the PMBus device. Table 15. Command 0x19—CAPABILITY (Default Value = 0x20)

7 Packet error

R Always reads 0. Packet error checking (PEC) is not supported. R Return the device PMBus speed capability. Always reads 01 (maximum bus speed is 400 kHz). 4 SMBALERT# R Always reads 0. SMBALERT# pin and SMBus alert response protocol are not supported.

This command returns the lower byte of the STATUS_WORD command. A value of 1 in this command indicates that a fault has occurred. Table 16. Command 0x78—STATUS_BYTE 7 BUSY R Always reads 0. Not supported. 6 PSON_OFF R Always reads 0. Not supported. 5 VOUT_OV R Always reads 0. Not supported. 4 IOUT_OC R Always reads 0. Not supported. 3 VIN_UV R Always reads 0. Not supported. 2 TEMPERATURE R Always reads 0. Not supported. 1 CML R 1 = communications, memory, or logic fault.

0 NONE_OF_THE_

R Always reads 0. Not supported. A value of 1 in this command indicates that a fault has occurred. Table 17. Command 0x79—STATUS_WORD 15 VOUT R Always reads 0. Not supported. 14 IOUT/POUT R Always reads 0. Not supported. 13 INPUT R Always reads 0. Not supported. 12 MFR R Always reads 0. Not supported. 11 POWER_GOOD# R Always reads 0. Not supported. 10 FANS R Always reads 0. Not supported. 9 OTHER R Always reads 0. Not supported. 8 UNKNOWN R Always reads 0. Not supported. 7 BUSY R Always reads 0. Not supported. 6 PSON_OFF R Always reads 0. Not supported. 5 VOUT_OV R Always reads 0. Not supported. 4 IOUT_OC R Always reads 0. Not supported. 3 VIN_UV R Always reads 0. Not supported. 2 TEMPERATURE R Always reads 0. Not supported. 1 CML R 1 = communications, memory, or logic fault. R Always reads 0. Not supported. linear mode format (X = Y × 2N). Table 18. Command 0x8D—READ_TEMPERATURE_1 [15:11] Exponent R Return the exponent (N) used in linear mode format (X = Y × 2N). [10:8] High bits R Mantissa high bits (Y[10:8]) used in linear mode format (X = Y × 2N). [7:0] Low byte R Mantissa low byte (Y[7:0]) used in linear mode format (X = Y × 2N). Table 19. Command 0x8E—READ_TEMPERATURE_2 [15:11] Exponent R Return the exponent (N) used in linear mode format (X = Y × 2N). [10:8] High bits R Mantissa high bits (Y[10:8]) used in linear mode format (X = Y × 2N). [7:0] Low byte R Mantissa low byte (Y[7:0]) used in linear mode format (X = Y × 2N).

Table 20. Command 0x98—PMBUS_REVISION (Default Value = 0x11) [7:0] Revision R Return the revision of PMBus that the device is compliant with. Table 21. Command 0x99—MFR_ID (Default Value = 0x41) [7:0] MFR_ID R Return the manufacturer’s ID. Table 22. Command 0x9A—MFR_MODEL (Default Value = 0x53) [7:0] Model R Return the manufacturer’s model number. Table 23. Command 0x9B—MFR_REVISION [7:0] Revision R Return the manufacturer’s revision number. of the EEPROM main block. For more information, see the EEPROM section. Table 24. Command 0xD1—EEPROM_CRC_CHKSUM [7:0] CRC checksum R Return the CRC checksum value from the EEPROM download operation. Table 25. Command 0xD2—EEPROM_NUM_RD_BYTES R/W Set the number of read bytes returned when using the EEPROM_DATA_xx commands. Table 26. Command 0xD3—EEPROM_ADDR_OFFSET [15:0] Address offset R/W Set the address offset of the current EEPROM page.

Table 27. Command 0xD4—EEPROM_PAGE_ERASE Page 1. Page 2 and Page 3 are reserved for internal use and their contents should not be erased. Table 28. Command 0xD5—EEPROM_PASSWORD change the EEPROM password. The factory default password is 0xFF. Table 29. Command 0xD6—TRIM_PASSWORD Command 0xF1, read/write block. This command reads the first flag data from the EEPROM.

cleared. Bits[7:6] of Register 0xFE06 set the global flag reenable delay time. Table 30. Register 0xFE00 to Register 0xFE06—Flag Configuration Registers Table 31. Register 0xFE00 to Register 0xFE05—Flag Configuration Register Bit Descriptions These bits specify the action to take when the flag is set. R/W These bits specify the action to take after the flag is cleared. [3:2] Flag action R/W These bits specify the action to take when the flag is set. R/W These bits specify the action to take after the flag is cleared.

Table 32. Register 0xFE06—Flag Reenable Delay, VDD_OV, and FLAGIN Configuration These bits specify the global delay from when a flag is cleared to the soft start process. 5 VDD_OV flag ignore R/W This bit enables or disables the VDD_OV flag. part shuts down. When the flag is cleared, the part restarts. 1 = VDD_OV flag is always cleared.

4 VDD_OV flag

R/W This bit sets the debounce time for the VDD_OV flag. [3:2] FLAGIN action R/W These bits specify the action to take when the FLAGIN flag is set. R/W These bits specify the action to take after the FLAGIN flag is cleared. flags are also blanked: REVERSE_A and UVP_A. During the soft start of Channel B, these flags are also blanked: REVERSE_B and UVP_B. Table 33. Register 0xFE07—Flag Blanking During Soft Start 6 CS_OCP blanking R/W 0 = blank CS_OCP flag during Channel C soft start. 1 = do not blank CS_OCP flag. 5 OVP_B blanking R/W 0 = blank OVP_B flag during Channel B soft start. 1 = do not blank OVP_B flag. 4 OVP_A blanking R/W 0 = blank OVP_A flag during Channel A soft start. 1 = do not blank OVP_A flag. 3 CS2_B_OCP blanking R/W 0 = blank CS2_B_OCP flag during Channel B soft start. 1 = do not blank CS2_B_OCP flag. 2 CS2_A_OCP blanking R/W 0 = blank CS2_A_OCP flag during Channel A soft start. 1 = do not blank CS2_A_OCP flag. 1 CS1_B_OCP blanking R/W 0 = blank CS1_B_OCP flag during Channel B soft start. 1 = do not blank CS1_B_OCP flag. 0 CS1_A_OCP blanking R/W 0 = blank CS1_A_OCP flag during Channel A soft start. 1 = do not blank CS1_A_OCP flag.

whether the output is disabled. Table 34. Register 0xFE08—Volt-Second Balance Blanking and SR Disable During Soft Start

6 ACSNS reenable

R/W This bit specifies whether the ACSNS flag is blanked during the flag reenable time. 0 = do not blank the ACSNS flag during the flag reenable time. 1 = blank the ACSNS flag during the flag reenable time. 5 First flag ID update R/W This bit specifies whether the first flag ID is saved in the EEPROM. 0 = first flag ID is not saved in the EEPROM. 1 = first flag ID is saved in the EEPROM.

4 Flag shutdown

R/W This bit specifies when the PWM outputs are shut down after a flag is triggered. 0 = PWM outputs are shut down at the end of the PWM cycle. 1 = PWM outputs are shut down immediately.

3 Volt-second balance

by Bit 7 of Register 0xFE72). 0 = do not blank volt-second balance control during Channel A or Channel C soft start. 1 = blank volt-second balance control during Channel A or Channel C soft start. soft start of Channel C, if these outputs are assigned to Channel C. 0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel C. 1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel C. soft start of Channel B, if these outputs are assigned to Channel B. 0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel B. 1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel B. soft start of Channel A, if these outputs are assigned to Channel A. 0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel A. 1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel A. Table 35. Register 0xFE09—PGOOD Debounce condition is met to when the PGOOD_B flag is set. condition is met to when the PGOOD_B flag is cleared.

condition is met to when the PGOOD_A flag is set. condition is met to when the PGOOD_A flag is cleared. Table 36. Register 0xFE0A, Register 0xFE0B, and Register 0xFE0C—Switching Frequency for Channel A, Channel B, and Channel C These bits set the switching frequency to a multiple of the synchronization input frequency. [5:0] Switching frequency R/W These bits set the switching frequency.

Rev. A | Page 54 of 84 Bits Bit Name R/W Description [5:0] Switching frequency R/W Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz) 0 1 1 0 0 1 240.4 0 1 1 0 1 0 250.0 0 1 1 0 1 1 260.4 0 1 1 1 0 0 271.7 0 1 1 1 0 1 284.1 0 1 1 1 1 0 297.6 0 1 1 1 1 1 312.5 1 0 0 0 0 0 320.5 1 0 0 0 0 1 328.9 1 0 0 0 1 0 337.8 1 0 0 0 1 1 347.2 1 0 0 1 0 0 357.1 1 0 0 1 0 1 367.6 1 0 0 1 1 0 378.8 1 0 0 1 1 1 390.6 1 0 1 0 0 0 396.8 1 0 1 0 0 1 403.2 1 0 1 0 1 0 409.8 1 0 1 0 1 1 416.7 1 0 1 1 0 0 423.7 1 0 1 1 0 1 431.0 1 0 1 1 1 0 438.6 1 0 1 1 1 1 446.4 1 1 0 0 0 0 454.5 1 1 0 0 0 1 463.0 1 1 0 0 1 0 471.7 1 1 0 0 1 1 480.8 1 1 0 1 0 0 490.2 1 1 0 1 0 1 500.0 1 1 0 1 1 0 510.2 1 1 0 1 1 1 520.8 1 1 1 0 0 0 531.9 1 1 1 0 0 1 543.5 1 1 1 0 1 0 555.6 1 1 1 0 1 1 568.2 1 1 1 1 0 0 581.4 1 1 1 1 0 1 595.2 1 1 1 1 1 0 609.8 1 1 1 1 1 1 625.0

is used to set the tSYNC_DELAY time. Figure 40. Synchronization Timing Table 37. Register 0xFE0D—Frequency Synchronization Delay Time the SYNI pin signal. Each LSB corresponds to 80 ns resolution. Table 38. Register 0xFE0E—SYNO Selection and Synchronization Enable [7:4] Reserved R/W Reserved. 3 SYNO selection R/W 0 = select Channel C as the SYNO reference. 1 = select Channel A as the SYNO reference.

2 Enable Channel C

R/W Setting this bit enables frequency synchronization for Channel C.

1 Enable Channel B

R/W Setting this bit enables frequency synchronization for Channel B.

0 Enable Channel A

R/W Setting this bit enables frequency synchronization for Channel A. Table 39. Register 0xFE0F—Flag/Synchronization Pin Functions

6 Channel B filter

setting prevents additional delays when the PWM outputs in Channel B use 180° interleaving. 0 = normal mode. A high signal on the FLGO/SYNO pin sets FLAGOUT. 1 = inverted. A low signal on the FLGO/SYNO pin sets FLAGOUT. 4 FLAGOUT selection R/W This bit configures the FLGO/SYNO pin to respond to the LIGHTLOAD_A or LIGHTLOAD_B flag. 0 = LIGHTLOAD_A flag triggers FLAGOUT. 1 = LIGHTLOAD_B flag triggers FLAGOUT.

3 FLGO/SYNO pin

R/W This bit configures the FLGO/SYNO pin as a flag output or a synchronization output. 0 = FLGO/SYNO pin used as a synchronization output (SYNO). 1 = FLGO/SYNO pin used as a flag output (FLAGOUT). 0 = normal mode. A high signal on the FLGI/SYNI pin sets FLAGIN. 1 = inverted. A low signal on the FLGI/SYNI pin sets FLAGIN.

1 FLAGIN debounce

R/W This bit sets the debounce time for FLAGIN. 0 = 0 μs debounce time for FLAGIN. 1 = 100 μs debounce time for FLAGIN.

0 FLGI/SYNI pin

R/W This bit configures the FLGI/SYNI pin as a flag input or a synchronization input. 0 = FLGI/SYNI pin used as a synchronization input (SYNI). 1 = FLGI/SYNI pin used as a flag input (FLAGIN).

Table 40. Register 0xFE10—CS1_A Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 41. Register 0xFE11—CS1_B Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 42. Register 0xFE12—CS2_A Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 43. Register 0xFE13—CS2_B Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 44. Register 0xFE14—CS2_A Digital Offset Trim value. For more information, see the CS2_A and CS2_B Offset Trim section. Table 45. Register 0xFE15—CS2_B Digital Offset Trim value. For more information, see the CS2_A and CS2_B Offset Trim section. Table 46. Register 0xFE16—CS2_A Analog Offset Trim 6 Analog trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 47. Register 0xFE17—CS2_B Analog Offset Trim 6 Analog trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced.

Register 0xFE18 sets the CS2_A OCP threshold, and Register 0xFE19 sets the CS2_B OCP threshold. Table 48. Register 0xFE18 and Register 0xFE19—CS2_A OCP Threshold and CS2_B OCP Threshold The GUI converts the voltage to current based on the value of the current sensing resistor. The valid range of the register code is from 2 to 241 decimal. for Channel A. Register 0xFE1B sets the same values for Channel B. Table 49. Register 0xFE1A and Register 0xFE1B—CS2_A/CS2_B High-Side/Low-Side Setting and Channel A/Channel B Light Load

7 High-side/low-side

R/W This bit configures the part for high-side resistor current sensing or low-side current sensing. 0 = CS2_A or CS2_B is configured for low-side sensing. 1 = CS2_A or CS2_B is configured for high-side sensing. These bits set the CS2_A_OCP/CS2_B_OCP flag debounce time.

4 LIGHTLOAD_A/

R/W This bit specifies whether to blank the LIGHTLOAD_A/LIGHTLOAD_B flag during soft start. 0 = do not blank the LIGHTLOAD_A/LIGHTLOAD_B flag during Channel A/Channel B soft start. 1 = blank the LIGHTLOAD_A/LIGHTLOAD_B flag during Channel A/Channel B soft start. the threshold to enter light load mode (96 LSBs = 2.34% of the full range, that is, 2.8125 mV). When these bits are set to 0, the LIGHTLOAD_A/LIGHTLOAD_B flag is always cleared. Table 50. Register 0xFE1C—VS_A Gain Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. VS_A and VS_B Gain Trim section. Table 51. Register 0xFE1D—VS_B Gain Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. VS_A and VS_B Gain Trim section.

Table 52. Register 0xFE1E—VS_A Reference Maximum Limit [7:6] Reserved R/W Reserved. MSBs for the reference limit. The factory default setting is 0x3F. Table 53. Register 0xFE1F—VS_B Reference Maximum Limit [7:6] Reserved R/W Reserved. MSBs for the reference limit. The factory default setting is 0x3F. Table 54. Register 0xFE20—VS_A Reference Minimum Limit [7:6] Reserved R/W Reserved. MSBs for the reference limit. The factory default setting is 0x00. Table 55. Register 0xFE21—VS_B Reference Minimum Limit [7:6] Reserved R/W Reserved. MSBs for the reference limit. The factory default setting is 0x00. Table 56. Register 0xFE22—VS_A Reference Setting (MSBs) operation, the output of the VS_A ADC is regulated to the reference setting value. Table 57. Register 0xFE23—VS_B Reference Setting (MSBs) operation, the output of the VS_B ADC is regulated to the reference setting value. Table 58. Register 0xFE24—VS_A Reference Setting (LSBs) [7:4] Reserved R/W Reserved. the output of the VS_A ADC is regulated to the reference setting value. Table 59. Register 0xFE25—VS_B Reference Setting (LSBs) [7:4] Reserved R/W Reserved. the output of the VS_B ADC is regulated to the reference setting value.

Table 60. Register 0xFE26—OVP_A Setting These bits set the OVP_A flag debounce time. Table 61. Register 0xFE27—OVP_B Setting These bits set the OVP_B flag debounce time. Table 62. Register 0xFE28—UVP_A Setting

7 UVP_A flag

R/W This bit sets the UVP_A flag debounce time. threshold corresponds to 12.5 mV. When these bits are set to 0, the UVP_A flag is always cleared. Table 63. Register 0xFE29—UVP_B Setting

7 UVP_B flag

R/W This bit sets the UVP_B flag debounce time. threshold corresponds to 12.5 mV. When these bits are set to 0, the UVP_B flag is always cleared.

Table 64. Register 0xFE2A—Channel A Soft Start Ramp Rate [7:2] Reserved R/W Reserved. based on VREF = 2/3 full-scale range (FSR). Table 65. Register 0xFE2B—Channel B Soft Start Ramp Rate [7:2] Reserved R/W Reserved. based on VREF = 2/3 full-scale range (FSR). Figure 41. Digital Filter Programmability Table 66. Register 0xFE2C—Channel A Normal Mode Low Frequency Gain Table 67. Register 0xFE2D—Channel B Normal Mode Low Frequency Gain

Table 68. Register 0xFE2E—Channel A Normal Mode Zero Setting Table 69. Register 0xFE2F—Channel B Normal Mode Zero Setting Table 70. Register 0xFE30—Channel A Normal Mode Pole Setting Table 71. Register 0xFE31—Channel B Normal Mode Pole Setting Table 72. Register 0xFE32—Channel A Normal Mode High Frequency Gain Table 73. Register 0xFE33—Channel B Normal Mode High Frequency Gain Table 74. Register 0xFE34—Channel A Light Load Mode Low Frequency Gain Table 75. Register 0xFE35—Channel B Light Load Mode Low Frequency Gain Table 76. Register 0xFE36—Channel A Light Load Mode Zero Setting

Table 83. Register 0xFE3D—Channel B Modulation Limit This register sets the maximum duty cycle modulation limit for PWM outputs in Channel B. timing (see Figure 42). The step size of an LSB depends on the switching frequency. Table 84. Register 0xFE3E—Channel A Feedforward and Soft Start Digital Filter Setting [7:6] Reserved R/W Reserved.

5 High frequency ADC

R/W This bit sets the debounce time for detecting the settling of the VS_A high frequency ADC.

4 High frequency ADC

ADC at the end of a soft start. The debounce time is set using Bit 5.

3 Feedforward ADC

feedforward control of Channel A. Do not set this bit to 0. 2 Feedforward enable R/W This bit enables or disables feedforward control on Channel A. 0 = feedforward control disabled on Channel A. 1 = feedforward control enabled on Channel A. These bits set the low-pass filter gain for Channel A during soft start. Table 85. Register 0xFE3F—Channel B Feedforward and Soft Start Digital Filter Setting [7:6] Reserved R/W Reserved. R/W This bit sets the debounce time for detecting the settling of the VS_B high frequency ADC. ADC at the end of a soft start. The debounce time is set using Bit 5. feedforward control of Channel B. Do not set this bit to 0. 2 Feedforward enable R/W This bit enables or disables feedforward control on Channel B. 0 = feedforward control disabled on Channel B. 1 = feedforward control enabled on Channel B. These bits set the low-pass filter gain for Channel B during soft start.

Table 89. Register 0xFE43/0xFE47/0xFE4B/0xFE4F/0xFE53/0xFE57/0xFE5B/0xFE5F—OUT1 to OUT8 Settings 7 OUT X 180° delay R/W Setting this bit adds a 180° delay to the timing of the OUTX edges. 0 0 OUTX assigned to Channel A. 0 1 OUTX assigned to Channel B. 1 0 OUTX assigned to Channel C with soft start enabled. 1 1 OUTX assigned to Channel C with soft start disabled.

4 Current/volt-second

on the specific PWM output (OUTX = OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, or OUT8). 0 = OUTX modulated by volt-second balance control. 1 = OUTX modulated by dual-phase current balance control. 3 t RX modulation enable R/W 0 = no PWM modulation of the tRX edge. 1 = PWM modulation acts on the tRX edge. 2 t RX modulation sign R/W 0 = positive sign. Increase of PWM modulation moves tRX right. 1 = negative sign. Increase of PWM modulation moves tRX left. 1 t FX modulation enable R/W 0 = no PWM modulation of the tFX edge. 1 = PWM modulation acts on the tFX edge. 0 t FX modulation sign R/W 0 = positive sign. Increase of PWM modulation moves tFX right. 1 = negative sign. Increase of PWM modulation moves tFX left. Table 90. Register 0xFE60—PWM Output Pin Disable 7 OUT8 disable R/W Setting this bit disables the OUT8 output. 6 OUT7 disable R/W Setting this bit disables the OUT7 output. 5 OUT6 disable R/W Setting this bit disables the OUT6 output. 4 OUT5 disable R/W Setting this bit disables the OUT5 output. 3 OUT4 disable R/W Setting this bit disables the OUT4 output. 2 OUT3 disable R/W Setting this bit disables the OUT3 output. 1 OUT2 disable R/W Setting this bit disables the OUT2 output. 0 OUT1 disable R/W Setting this bit disables the OUT1 output. Table 91. Register 0xFE61—GO Commands [7:4] Reserved R/W Reserved. shadow registers used to calculate the switching frequency. shadow registers used to calculate the PWM edge timing. shadow registers used to calculate the VS_B voltage reference. shadow registers used to calculate the VS_A voltage reference.

than the CS1_B or CS2_B value, the modulation value increases. Table 92. Register 0xFE62—Balance Control on OUT1 and OUT2 7 t R2 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT2, tR2. 6 t R2 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tR2 right. 1 = negative sign. Increase of balance control modulation moves tR2 left. 5 t F2 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT2, tF2. 4 t F2 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tF2 right. 1 = negative sign. Increase of balance control modulation moves tF2 left. 3 t R1 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT1, tR1. 2 t R1 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tR1 right. 1 = negative sign. Increase of balance control modulation moves tR1 left. 1 t F1 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT1, tF1. 0 t F1 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tF1 right. 1 = negative sign. Increase of balance control modulation moves tF1 left. Table 93. Register 0xFE63—Balance Control on OUT3 and OUT4 7 t R4 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT4, tR4. 6 t R4 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tR4 right. 1 = negative sign. Increase of balance control modulation moves tR4 left. 5 t F4 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT4, tF4. 4 t F4 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tF4 right. 1 = negative sign. Increase of balance control modulation moves tF4 left. 3 t R3 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT3, tR3. 2 t R3 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tR3 right. 1 = negative sign. Increase of balance control modulation moves tR3 left. 1 t F3 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT3, tF3. 0 t F3 balance direction R/W 0 = positive sign. Increase of balance control modulation moves tF3 right. 1 = negative sign. Increase of balance control modulation moves tF3 left. Table 94. Register 0xFE64—Balance Control on OUT5, OUT6, OUT7, and OUT8 7 t R8 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT8, tR8. An increase of balance control modulation moves tR8 left. 6 t F8 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT8, tF8. An increase of balance control modulation moves tF8 left. 5 t R7 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT7, tR7. An increase of balance control modulation moves tR7 right. 4 t F7 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT7, tF7. An increase of balance control modulation moves tF7 right. 3 t R6 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT6, tR6. An increase of balance control modulation moves tR6 left. 2 t F6 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT6, tF6. An increase of balance control modulation moves tF6 left. 1 t R5 balance setting R/W Setting this bit enables modulation from balance control on the rising edge of OUT5, tR5. An increase of balance control modulation moves tR5 right. 0 t F5 balance setting R/W Setting this bit enables modulation from balance control on the falling edge of OUT5, tF5. An increase of balance control modulation moves tF5 right.

switches in a totem-pole structure—the operation of the power stage may be significantly affected. the dead time between the falling edge of OUTX and the rising edge of OUTY is kept the same at tS/2 − tFX. Figure 44. PWM Output Edge Adjustment in Channel C Synchronization Table 95. Register 0xFE65—OUT1 and OUT2 Shutdown in Channel C Synchronization assigned to Channel C, this bit must be set to 0. assigned to Channel C, this bit must be set to 0. [5:0] Reserved R/W Reserved. Table 96. Register 0xFE66—OUT1 Through OUT8 Dead Time Adjustment in Synchronization 7 OUT8 adjustment R/W Setting this bit adjusts both edges of OUT8 by (tS − tSYNC)/2. 6 OUT7 adjustment R/W Setting this bit adjusts both edges of OUT7 by (tS − tSYNC)/2. 5 OUT6 adjustment R/W Setting this bit adjusts both edges of OUT6 by (tS − tSYNC)/2. 4 OUT5 adjustment R/W Setting this bit adjusts both edges of OUT5 by (tS − tSYNC)/2. 3 OUT4 adjustment R/W Setting this bit adjusts both edges of OUT4 by (tS − tSYNC)/2. 2 OUT3 adjustment R/W Setting this bit adjusts both edges of OUT3 by (tS − tSYNC)/2. 1 OUT2 adjustment R/W Setting this bit adjusts both edges of OUT2 by (tS − tSYNC)/2. 0 OUT1 adjustment R/W Setting this bit adjusts both edges of OUT1 by (tS − tSYNC)/2.

Table 97. Register 0xFE67—Synchronous Rectifier (SR) Soft Start [7:6] Reserved R/W Reserved. cycles are required to move the SR PWM output left in 40 ns. 3 OUT8 SR soft start R/W Setting this bit enables SR soft start for OUT8. 2 OUT7 SR soft start R/W Setting this bit enables SR soft start for OUT7. 1 OUT4 SR soft start R/W Setting this bit enables SR soft start for OUT4. 0 OUT3 SR soft start R/W Setting this bit enables SR soft start for OUT3. Table 98. Register 0xFE68—Channel C Soft Start

7 OUT1, OUT2, OUT5,

rising edges in one cycle during a soft start.

6 OUT3, OUT4, OUT7,

R/W This bit is valid only when Bit 7 is set to 1. to Channel C. The duty cycle ramp rate is set to 40 ns per 1, 2, 4, or 8 switching cycles. 3 Global variation R/W Setting this bit enables global variation during Channel C soft start. OUT8 variation during soft start. 1 = all outputs use the time variation calculated by the OUT2 timing.

2 OUT2 soft start

R/W This bit selects the variation of the OUT2 on time during Channel C soft start. 0 = variation of OUT2 during soft start is tF2 − tR2. 1 = variation of OUT2 during soft start is tS − tR2, where tS is the switching cycle.

1 OUT1, OUT3, OUT5,

during Channel C soft start. If Bit 3 = 1, the setting of this bit is ignored. 0 = rising and falling edges of OUT1 determine OUT1, OUT3, OUT5, and OUT7 variation. 1 = rising and falling edges of OUT3 determine OUT1, OUT3, OUT5, and OUT7 variation.

0 OUT2, OUT4, OUT6,

during Channel C soft start. If Bit 3 = 1, the setting of this bit is ignored. 0 = rising and falling edges of OUT2 determine OUT2, OUT4, OUT6, and OUT8 variation. 1 = rising and falling edges of OUT4 determine OUT2, OUT4, OUT6, and OUT8 variation.

Table 99. Register 0xFE69—Channel A Light Load Mode PWM Output Disable 7 OUT8 disable R/W Setting this bit disables the OUT8 output when Channel A is in light load mode. 6 OUT7 disable R/W Setting this bit disables the OUT7 output when Channel A is in light load mode. 5 OUT6 disable R/W Setting this bit disables the OUT6 output when Channel A is in light load mode. 4 OUT5 disable R/W Setting this bit disables the OUT5 output when Channel A is in light load mode. 3 OUT4 disable R/W Setting this bit disables the OUT4 output when Channel A is in light load mode. 2 OUT3 disable R/W Setting this bit disables the OUT3 output when Channel A is in light load mode. 1 OUT2 disable R/W Setting this bit disables the OUT2 output when Channel A is in light load mode. 0 OUT1 disable R/W Setting this bit disables the OUT1 output when Channel A is in light load mode. Table 100. Register 0xFE6A—Channel B Light Load Mode PWM Output Disable 7 OUT8 disable R/W Setting this bit disables the OUT8 output when Channel B is in light load mode. 6 OUT7 disable R/W Setting this bit disables the OUT7 output when Channel B is in light load mode. 5 OUT6 disable R/W Setting this bit disables the OUT6 output when Channel B is in light load mode. 4 OUT5 disable R/W Setting this bit disables the OUT5 output when Channel B is in light load mode. 3 OUT4 disable R/W Setting this bit disables the OUT4 output when Channel B is in light load mode. 2 OUT3 disable R/W Setting this bit disables the OUT3 output when Channel B is in light load mode. 1 OUT2 disable R/W Setting this bit disables the OUT2 output when Channel B is in light load mode. 0 OUT1 disable R/W Setting this bit disables the OUT1 output when Channel B is in light load mode. Table 101. Register 0xFE6B—CS1_A Blanking Reference Edge [7:4] Reserved R/W Reserved.

3 OUT6 rising edge

0 = no blanking at OUT6 rising edge. 1 = blanking time referenced to OUT6 rising edge.

2 OUT5 rising edge

0 = no blanking at OUT5 rising edge. 1 = blanking time referenced to OUT5 rising edge.

1 OUT2 rising edge

0 = no blanking at OUT2 rising edge. 1 = blanking time referenced to OUT2 rising edge.

0 OUT1 rising edge

0 = no blanking at OUT1 rising edge. 1 = blanking time referenced to OUT1 rising edge.

Table 102. Register 0xFE6C—CS1_B Blanking Reference Edge [7:4] Reserved R/W Reserved. 0 = no blanking at OUT6 rising edge. 1 = blanking time referenced to OUT6 rising edge. 0 = no blanking at OUT5 rising edge. 1 = blanking time referenced to OUT5 rising edge. 0 = no blanking at OUT2 rising edge. 1 = blanking time referenced to OUT2 rising edge. 0 = no blanking at OUT1 rising edge. 1 = blanking time referenced to OUT1 rising edge. Table 103. Register 0xFE6D—OUT3, OUT4, OUT7, and OUT8 Cycle-by-Cycle OCP Response [7:4] Reserved R/W Reserved.

3 OUT8 cycle-by-cycle

turn on. The falling edge of the SR output still follows the programmed value.

2 OUT7 cycle-by-cycle

turn on. The falling edge of the SR output still follows the programmed value.

1 OUT4 cycle-by-cycle

turn on. The falling edge of the SR output still follows the programmed value.

0 OUT3 cycle-by-cycle

turn on. The falling edge of the SR output still follows the programmed value. Table 104. Register 0xFE6E—CS Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. CS1_A, and CS1_B Gain Trim section. Table 105. Register 0xFE6F—CS OCP Settings 7 CS OCP ignored R/W Setting this bit causes the CS OCP comparator output to be ignored. The flag is always cleared. ignored. The CS OCP blanking time is measured from OUT1 and OUT2.

occur before the CS_OCP flag is set. action. This action is programmed in Register 0xFE04, Bits[3:0]. Table 106. Register 0xFE70 and Register 0xFE71—CS1_A OCP and CS1_B OCP Settings

7 CS1_A/CS1_B OCP

OUT6 (programmed in Register 0xFE6B and Register 0xFE6C). occur before the CS1_A_OCP/CS1_B_OCP flag is set. the flag triggers an action. This action is programmed in Register 0xFE00.

Table 107. Register 0xFE72—Balance Control Settings

7 Channel selection for

R/W Setting this bit selects Channel A or Channel C for volt-second balance control. 0 = use Channel C for volt-second balance control. 1 = use Channel A for volt-second balance control.

6 Volt-second balance

R/W This bit sets the modulation limit on the duty cycles from the volt-second control circuit. 0 = maximum volt-second control modulation is ±160 ns. 1 = maximum volt-second control modulation is ±80 ns. These bits set the volt-second balance control loop gain.

3 Sensing selection for

R/W Setting this bit selects CS1_A/CS1_B or CS2_A/CS2_B for current balance control. 0 = use CS2_A/CS2_B for current balance control. 1 = use CS1_A/CS1_B for current balance control.

2 Current balance

R/W This bit sets the modulation limit on the duty cycles from the current control circuit. 0 = maximum current control modulation is ±160 ns. 1 = maximum current control modulation is ±80 ns. These bits set the current balance control loop gain. Table 108. Register 0xFE73—RTD1 Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] RTD1 gain trim R/W This value calibrates the RTD1 sensing gain (see the RTD1, RTD2, OTP1, and OTP2 Trim section). Table 109. Register 0xFE74—RTD2 Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] RTD2 gain trim R/W This value calibrates the RTD2 sensing gain (see the RTD1, RTD2, OTP1, and OTP2 Trim section).

Register 0xFE75 sets the OTP1 threshold value. The debounce time of the OTP1 flag is 100 ms. Table 110. Register 0xFE75—OTP1 Threshold 256 threshold settings from 0 mV to 800 mV. One LSB corresponds to 800 mV/256 = 3.125 mV. for this register value is 2 to 244 (decimal). Register 0xFE76 sets the OTP2 threshold value. The debounce time of the OTP2 flag is 100 ms. Table 111. Register 0xFE76—OTP2 Threshold 256 threshold settings from 0 mV to 800 mV. One LSB corresponds to 800 mV/256 = 3.125 mV. for this register value is 2 to 244 (decimal). Table 112. Register 0xFE77—ACSNS Gain Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced.

Table 113. Register 0xFE78—ACSNS Setting

7 ACSNS flag included

time for this function is set with Bit 6.

6 Debounce of ACSNS

the ACSNS flag is always cleared. For more information, see the ACSNS Flag section. These bits set the ACSNS flag debounce time. Table 114. Register 0xFE79—Channel A PSON Setting 7 PSON_A polarity R/W Setting this bit inverts the polarity of the PSON_A pin signal when hardware PSON_A is used. 0 = normal mode. A high signal on the PSON_A pin turns on Channel A. 1 = inverted. A low signal on the PSON_A pin turns on Channel A. 6 Software PSON_A R/W When software PSON_A is used, setting this bit turns on Channel A. These bits specify which signal or signals are used as the PSON_A control. 0 0 Always on. Channel A is always on. 0 1 Hardware PSON_A. The PSON_A pin turns Channel A on and off. 1 0 Software PSON_A. Bit 6 turns Channel A on and off.

Table 115. Register 0xFE7A—Channel B PSON Setting 7 PSON_B polarity R/W Setting this bit inverts the polarity of the PSON_B pin signal when hardware PSON_B is used. 0 = normal mode. A high signal on the PSON_B pin turns on Channel B. 1 = inverted. A low signal on the PSON_B pin turns on Channel B. 6 Software PSON_B R/W When software PSON_B is used, setting this bit turns on Channel B. These bits specify which signal or signals are used as the PSON_B control. 0 0 Always on. Channel B is always on. 0 1 Hardware PSON_B. The PSON_B pin turns Channel B on and off. 1 0 Software PSON_B. Bit 6 turns Channel B on and off. These bits specify the delay from when the PSON_B signal is set to when the soft start of Channel B begins. These bits specify the delay from when the PSON_B signal is cleared to when Channel B is turned off. Table 116. Register 0xFE7B—Additional Flag Reenable Delay and Channel C PSON Setting

7 Channel C

cleared and before Channel C begins a soft start. 0 = no additional delay is added to the reenable delay. 1 = additional PSON_C delay is added to the reenable delay.

6 Channel B

cleared and before Channel B begins a soft start. 0 = no additional delay is added to the reenable delay. 1 = additional PSON_B delay is added to the reenable delay.

5 Channel A

cleared and before Channel A begins a soft start. 0 = no additional delay is added to the reenable delay. 1 = additional PSON_A delay is added to the reenable delay.

4 PSON_C control

R/W 0 = Channel C is always on. 1 = Either PSON_A or PSON_B must be set to turn on Channel C. These bits specify the delay from when the PSON_C signal is set to when the soft start of Channel C begins. These bits specify the delay from when the PSON_C signal is cleared to when Channel C is turned off.

Table 117. Register 0xFE7C—RTD1 Offset Trim (MSB) [7:2] Reserved R/W Reserved. 1 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced.

0 RTD1 offset trim

Table 118. Register 0xFE7D—RTD1 Offset Trim (LSBs) applied to the RTD1 ADC reading. Table 119. Register 0xFE7E—RTD2 Offset Trim (MSB) [7:2] Reserved R/W Reserved. 1 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced.

0 RTD2 offset trim

Table 120. Register 0xFE7F—RTD2 Offset Trim (LSBs) applied to the RTD2 ADC reading. Table 121. Register 0xFE80—RTD1 Current Source Settings [7:6] RTD1 current setting R/W These bits set the size of the current source on the RTD1 pin. The factory default setting is 10 μA. 156.25 nA, independent of the RTD1 current source setting specified by Bits[7:6]. Table 122. Register 0xFE81—RTD2 Current Source Settings [7:6] RTD2 current setting R/W These bits set the size of the current source on the RTD2 pin. The factory default setting is 10 μA. 156.25 nA, independent of the RTD2 current source setting specified by Bits[7:6].

Table 123. Register 0xFE82—Custom Register be used to store user software or hardware revision information. Table 124. Register 0xFE83—REVERSE_A/REVERSE_B Flag Configuration These bits specify the action to take when the REVERSE_B flag is set. R/W These bits specify the action to take after the REVERSE_B flag is cleared. These bits specify the action to take when the REVERSE_A flag is set. R/W These bits specify the action to take after the REVERSE_A flag is cleared. Table 125. Register 0xFE84 and Register 0xFE85—REVERSE_A/REVERSE_B Flag Settings [7:4] Reserved R/W Reserved. 3 Debounce time R/W This bit sets the debounce time for the REVERSE_A and REVERSE_B flags. falls below this threshold, the REVERSE_A or REVERSE_B flag is triggered.

Table 126. Register 0xFE86 and Register 0xFE87—VS_A/VS_B Slew Rate for Output Voltage Adjustment [7:4] Reserved R/W Reserved. These bits specify the slew rate.

0 Slew rate adjust

R/W Setting this bit enables output voltage adjustment with the slew rate specified by Bits[3:1]. Table 127. Register 0xFE88—Power Supply Software Reset Control [7:4] Reserved R/W Reserved. These bits specify the delay after the power supply is turned off and before the part is restarted.

1 Channel B SW reset

of the power supply and the restarting of the part. This restart delay is set using Bits[3:2].

0 Channel A SW reset

of the power supply and the restarting of the part. This restart delay is set using Bits[3:2]. Table 128. Register 0xFE89—CS, CS1, and CS2 ADC Update Rate [7:2] Reserved R/W Reserved.

Table 129. Register 0xFE8A—OTW1/OTW2 Settings 7 OTW2 flag debounce R/W This bit sets the OTW2 flag debounce time.

6 OTW2 triggers

R/W This bit specifies whether the OTW2 flag triggers PGOOD_B. 0 = OTW2 does not trigger PGOOD_B. These bits set the OTW2 threshold. 3 OTW1 flag debounce R/W This bit sets the OTW1 flag debounce time.

2 OTW1 triggers

R/W This bit specifies whether the OTW1 flag triggers PGOOD_A. 0 = OTW1 does not trigger PGOOD_A. These bits set the OTW1 threshold. reset. Note that latched flag bits are clocked on a low-to-high transition only. Table 130. Register 0xFEC0—Flag Register 1 and Register 0xFEC5—Latched Flag Register 1 (1 = Fault, 0 = Normal Operation) 7 POWER_SUPPLY_A R Channel A power supply is off and the PWM outputs are disabled. This bit stays high until PSON_A is asserted.

1 LIGHTLOAD_A R Channel A is in light load mode (CS2_A current is below the light

Table 131. Register 0xFEC1—Flag Register 2 and Register 0xFEC6—Latched Flag Register 2 (1 = Fault, 0 = Normal Operation) 7 POWER_SUPPLY_B R Channel B power supply is off and the PWM outputs are disabled. This bit stays high until PSON_B is asserted.

1 LIGHTLOAD_B R Channel B is in light load mode (CS2_B current is below the light

Table 132. Register 0xFEC2—Flag Register 3 and Register 0xFEC7—Latched Flag Register 3 (1 = Fault, 0 = Normal Operation) Table 133. Register 0xFEC3—Flag Register 4 and Register 0xFEC8—Latched Flag Register 4 (1 = Fault, 0 = Normal Operation) 6 POWER_SUPPLY_C R Channel C power supply is off and the PWM outputs are disabled. This bit stays high until PSON_C is asserted.

5 FLAGOUT R The FLGO/SYNO pin is set in response to the LIGHTLOAD_A or

Table 134. Register 0xFEC4—Flag Register 5 and Register 0xFEC9—Latched Flag Register 5 (1 = Fault, 0 = Normal Operation)

1 REVERSE_B R CS2_B reverse current falls below the CS2_B reverse current

0 REVERSE_A R CS2_A reverse current falls below the CS2_A reverse current

ID of the fault that shut down Channel B. For more information, see the First Flag ID Recording section. Table 135. Register 0xFECA and Register 0xFECB—Channel A and Channel B First Flag ID [3:0] Current first flag ID R These bits return the flag fault ID of the fault that caused the shutdown of Channel A or Channel B.

Rev. A | Page 82 of 84 Table 136. Register 0xFED0—CS Value

Description

[15:4] CS voltage value R This register contains the 12-bit CS current information. The range of the CS input pin is from nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal). [3:0] Reserved R Reserved. Table 137. Register 0xFED1—CS1_A Value nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal). Table 138. Register 0xFED2—CS1_B Value nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal). Table 139. Register 0xFED3—CS2_A Value Table 140. Register 0xFED4—CS2_B Value Table 141. Register 0xFED5—VS_A Value nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal). Table 142. Register 0xFED6—VS_B Value nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal).

Table 143. Register 0xFED7—RTD1 Value R This register contains the 12-bit RTD1 temperature information as determined from the RTD1 pin. bits is 0xA00 (2560 decimal). Table 144. Register 0xFED8—RTD2 Value R This register contains the 12-bit RTD2 temperature information as determined from the RTD2 pin. bits is 0xA00 (2560 decimal). Table 145. Register 0xFED9—ACSNS Value The nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0x500 (1280 decimal). Table 146. Register 0xFEDA—Channel A Duty Cycle Value of the duty cycle. At 100% duty cycle, the value in this register is 0xFFF (4095 decimal). Table 147. Register 0xFEDB—Channel B Duty Cycle Value of the duty cycle. At 100% duty cycle, the value in this register is 0xFFF (4095 decimal).

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] registered trademarks are the property of their respective owners.