ADP1048ARQZ-R7

ADP1047 AD | Alldatasheet

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Technical content

Digital Power Factor Correction Controller with Accurate AC Power Metering Data Sheet ADP1047/ADP1048

FEATURES

Flexible digital power factor correction (PFC) controller Single phase operation (ADP1047); interleaved and bridgeless operation (ADP1048) True rms ac power metering Enhanced dynamic response Optimized light load efficiency performance Output voltage adjustment Frequency reduction Inrush current control Switching frequency spread spectrum for improved EMI External frequency synchronization PMBus compliant Programmable ac line fault detection and protection Programmable output fault detection and protection Extensive fault protection for high reliability systems Frequency range from 30 kHz to 400 kHz 8 kB EEPROM Programming via easy-to-use graphical user interface (GUI)

APPLICATIONS

AC/DC power supplies for applications Computing server and storage Network and communication infrastructure Industrial and medical GENERAL DESCRIPTION The ADP1047/ADP1048 are digital power factor correction (PFC) controllers that provide accurate input power metering capability and inrush current control for ac/dc systems. The ADP1047 is designed for single phase PFC applications; the ADP1048 is designed especially for interleaved and bridgeless PFC applications. The digital PFC function is based on a conventional boost PFC with multiplication of the output voltage feedback combined with the input current and voltage to provide optimum harmonic correction and power factor for ac/dc systems. All signals are converted into the digital domain to provide maximum flexibility; all key parameters can be reported and adjusted via the PMBus™ interface. The ADP1047/ADP1048 allow users to optimize system performance, maximize efficiency across the load range, and reduce design time to market. The ADP1047/ADP1048 provide accurate rms measurement of input voltage, current, and power. This information can be reported to the microcontroller of the power supply via the PMBus interface. TYPICAL APPLICATIONS CIRCUIT RES RTD ADD SYNC INRUSH SCL SDA VAC VFB OVP NC ILIM PGND AGND CS– PSON DGND CS+ PWM2 VCORE PWM AC_OK PGOOD VDD ADP1047 VREC RELAY VOUT BULK CAPACITOR 3.3V PMBus AC INPUT 09696-101 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 2 of 84 TABLE OF CONTENTS Standard PMBus Commands Supported by the

Data Sheet ADP1047/ADP1048 Rev. 0 | Page 3 of 84 EEPROM_DATA_00 Through EEPROM_DATA_15

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 4 of 84 Power Metering Offset Trim for Low Line Input Register .... 72 CS ADC Offset Trim for High (750 mV) Range Register .... 78 Power Metering Offset Trim for High Line Input Register .. 79 Power Metering Gain Trim for High Line Input Register .... 80 Current Loop Filter Gain for Low Line Input and Light Current Loop Filter Zero for Low Line Input and Light Current Loop Filter Gain for High Line Input and Light Current Loop Filter Zero for High Line Input and Light

REVISION HISTORY

9/11—Revision 0: Initial Version

capability to reduce the output voltage at light load. via an external sensing device. an easy-to-use GUI. No complex programming is required. over an ambient temperature range of −40°C to +85°C. Figure 2. Typical Interleaved Application, ADP1048

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 6 of 84 SPECIFICATIONS VDD = 3.3 V , TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Supply Voltage VDD 3.0 3.3 3.6 V Supply Current IDD Normal operation (PSON high) and no load on PWM output 17 40 mA Supply Current for Programming IDD_PK During EEPROM programming (50 ms) IDD + 8 mA Shutdown Current IDD_SD 100 μA POWER-ON RESET Power-On Reset VDD rising 1.8 3 V Undervoltage Lockout UVLO VDD falling 2.75 2.85 2.95 V Overvoltage Lockout OVLO 3.7 3.9 4.1 V VCORE PIN Output Voltage Range Temperature = 25°C 2.26 2.45 2.65 V PWM OUTPUTS PWM, PWM2 pins Output Low Voltage VPWMOL Sink current = 10 mA 0.4 V Output High Voltage VPWMOH Source current = 10 mA VDD − 0.4 V Rise Time CLOAD = 50 pF 4 ns Fall Time CLOAD = 50 pF 4 ns VAC ADC Input Voltage Range 0 1.6 V Leakage Current 5 μA Equivalent Resolution 11 Bits Voltage Sense Measurement Accuracy From 2.5% to 97.5% of input voltage range VDD = 3.3 V −1.3 +1.3 % FSR VDD varies from 3.0 V to 3.6 V −1.99 +1.99 % FSR VFB ADC Input Voltage Range 0 1.6 V Equivalent Resolution 11 Bits Voltage Sense Measurement Accuracy From 2.5% to 97.5% of input voltage range VDD = 3.3 V −1.2 +1.2 % FSR VDD varies from 3.0 V to 3.6 V −1.72 +1.72 % FSR CURRENT SENSE ADC High Input Voltage Range 0 750 mV Low Input Voltage Range 0 500 mV Equivalent Resolution 11 Bits Current Sense Measurement Accuracy From 0% to 97.5% of input voltage range VDD = 3.3 V −1.7 +1.7 % FSR VDD varies from 3.0 V to 3.6 V −2.06 +2.06 % FSR Current Source 10 kΩ level shifting resistor, VCS+ − VCS− = 0 V High Input 74 μA Low Input 84 μA Current Source Resolution ±0.03 % RTD PIN Input Voltage Range 0 0.8 V Current Source Accuracy 9 10 11 μA Equivalent Resolution 14 Bits

Data Sheet ADP1047/ADP1048 Rev. 0 | Page 7 of 84 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Voltage Sense Measurement Accuracy From 2.5% to 97.5% of input voltage range VDD = 3.3 V −1.52 +1.52 % FSR VDD varies from 3.0 V to 3.6 V −1.97 +1.97 % FSR IBAL PIN (ADP1048 ONLY) Interleaved operation mode Input Voltage Range 0 0.8 V Equivalent Resolution 11 Bits Channel Mismatch DC input and acquiring time window on each channel is 526 μs −5 +5 % FSR POWER METER Measurement Accuracy From 2.5% to 97.5% of input voltage range VDD = 3.3 V −2.3 +2.3 % FSR VDD varies from 3.0 V to 3.6 V −2.75 +2.75 % FSR SWITCHING FREQUENCY Frequency Range Programmable 30 400 kHz Accuracy −3.85 +3.85 % OSCILLATOR, CLOCK, AND PLL Oscillator Frequency 1.516 1.56 1.62 MHz Digital Clock Frequency 200 MHz PLL Frequency 200 MHz RES PIN Temperature Stability −120 0 +120 ppm/°C PGOOD, AC_OK PINS Output Low Voltage 0.8 V Output High Voltage 2.0 V FAST OVERCURRENT PROTECTION Fast OCP Threshold Positive Signal 1455 1500 1550 mV Negative Signal 452 500 523 mV Current Source Accuracy ±4.4 % Current Source Resolution ±3.2 % Propagation Delay From threshold trip to PWM disabled 140 ns RMS OVERCURRENT PROTECTION RMS Accuracy VDD = 3.3 V −1.7 +1.7 % Propagation Delay AC line frequency = 50 Hz 12 ms FAST OVERVOLTAGE PROTECTION Fast OVP Threshold Fully programmable from 1 V to 1.5 V Rising Register 0xFE2F, Bits[6:0] 1 1.5 V Falling Register 0xFE30, Bits[6:0] 1 1.5 V OVP Threshold Minimum Step 3.9 mV Accuracy −4 +4 LSB Propagation Delay (Latency) Does not include blanking/debounce 120 ns Blanking Time Blanking after threshold reprogramming 10 μs ACCURATE OVERVOLTAGE PROTECTION Accuracy VDD = 3.3 V −1.2 +1.2 % Propagation Delay AC line frequency = 50 Hz 12 ms OPEN-LOOP PROTECTION VFB Error Threshold ΔVFB ±33 ±111 ±242 mV Propagation Delay 200 ns Debounce Time 10 μs Common-Mode Input Range −0.2 +1.6 V

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 8 of 84 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SDA, SCL PINS VDD = 3.3 V Input Low Voltage 0.8 V Input High Voltage 2.2 V Output Low Voltage 0.4 V Pull-Up Current 100 350 μA Leakage Current −5 +5 μA SERIAL BUS TIMING Clock Frequency 10 100 400 kHz Glitch Immunity tSW 50 ns Bus Free Time tBUF 1.3 μs Start Condition Hold Time tHD;STA 0.6 μs Start Condition Setup Time tSU;STA 0.6 μs Stop Condition Setup Time tSU;STO 0.6 μs Data Hold Time tHD;DAT 300 ns Data Setup Time tSU;DAT 100 ns SCL Low Timeout tTIMEOUT 25 35 ms SCL Low Time tLOW 1.3 μs SCL High Time tHIGH 0.6 μs Clock Low Extend Time tLOW;SEXT 25 ms SCL, SDA Rise Time tR 20 300 ns SCL, SDA Fall Time tF 20 300 ns EEPROM RELIABILITY Endurance 10,000 Cycles Data Retention Temperature = 85°C 20 Years

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance

NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. ADP1047 Pin Configuration Figure 4. ADP1048 Pin Configuration Table 4. Pin Function Descriptions 1 AGND Analog Ground. AGND should be connected directly to DGND. 2 VAC Input Line Voltage Sense. The VAC signal is referred to PGND. regulation. It is used as the analog voltage input to the VFB ADC. 4 OVP Overvoltage Protection. The OVP signal is referred to PGND. This signal is used for redundant overvoltage protection. 6 ILIM Fast Current Limiting. This pin is referred to PGND. 7 NC/IBAL ADP1047: No Connect. Do not connect to this pin. ADP1048: Current Balancing Input for Interleaved Operation. The IBAL input is referred to PGND. protection. A 0.1%, 10 kΩ resistor must be used to connect to this circuit. protection. A 0.1%, 10 kΩ resistor must be used to connect to this circuit. 10 DGND Digital Ground. DGND should be connected directly to AGND. 12 VCORE Output of 2.5 V Regulator. Connect a 100 nF capacitor from VCORE to DGND. 13 PWM PWM Output for PFC Regulation. The PWM signal is referred to AGND. 14 PWM2 Auxiliary PWM Output (ADP1047) or Interleaved PWM Output (ADP1048). The PWM2 signal is referred to AGND. 15 AC_OK Open-Drain Output. User-configurable signal from a combination of flags. The AC_OK signal is referred to AGND. 16 PGOOD Open-Drain Output. User-configurable signal from a combination of flags. The PGOOD signal is referred to AGND. 17 INRUSH Inrush Current Control Signal to an External Inrush Driver. This open-drain output is referred to AGND. 18 SYNC Allows parallel PFC controllers to synchronize to reduce interference. This pin is referred to DGND. 19 SCL I2C Serial Clock Input. The SCL signal is referred to DGND. 20 SDA I2C Serial Data Input and Output (Open-Drain). The SDA signal is referred to DGND. 21 ADD Address Select Input. Connect a resistor from ADD to AGND (see the PMBus Address section). 22 RTD Thermistor Input. A thermistor is placed from RTD to AGND. The RTD signal is referred to AGND. 23 RES Internal Voltage Reference. Connect a 0.1%, 50 kΩ resistor from RES to AGND.

• Power factor correction control loop (see the Power Factor Correction Control Loop section)
• The output is decimated at the switching frequency for the control loop. The effective number of bits (ENOB) is >7 when the current loop bandwidth is 10 kHz; the ENOB is >10 when the current loop bandwidth is 1 kHz.
• Advanced input power metering (see the Advanced Input Power Metering section)
• The 11-bit result is calculated and updated at each half line cycle for high accuracy ac line current and input power monitoring and for overcurrent protection (accurate OCP).
• PMBus digital communication (see the PMBus Digital Communication section) This section describes the internal architecture of the chip. RMS INPUT OVERCURRENT PROTECTION CURRENT SENSE The ADP1047/ADP1048 provide rms overcurrent protection (OCP). RMS OCP (or accurate OCP) is distinct from the instan- taneous pulse-by-pulse fast overcurrent protection and is based on the rms value of the input ac current. Current sensing is used for the control, protection, and monitor- ing of the PFC stage. For normal operation, the power factor correction control loop requires inductor current information. The typical implementation uses a sense resistor on the input bus. A combination of two current transformers in series with the power switch and the boost diode can be used to reconstruct the inductor current and minimize losses in the resistive shunt, but, in general, a good quality shunt resistor provides much better accuracy in measuring input current and input power. The measured value is compared to the limit set in the IIN_OC_FAULT_LIMIT register (Register 0x5B) at the end of each half cycle of the ac line. If the limit is exceeded, the action programmed in the IIN_OC_FAULT_RESPONSE register (Register 0x5C) is triggered. In addition, an input current warning limit can be programmed in the IIN_OC_W ARN_LIMIT register (Register 0x5D). This warning limit has no action attached to it, but it sets flags in the STATUS_BYTE register (Register 0x78, Bit 0), the STATUS_WORD register (Register 0x79, Bit 13), and the STATUS_INPUT register (Register 0x7C, Bit 1). The inputs to the current sense ADC are differential. A pair of matched current sources is provided to level shift the negative signal across the current sense element in the input range of the current sense ADC (see Figure 7). 09696-005 11-BITADC CS– CS+ 10kΩ10kΩ VDD ADP1047/ADP1048 IL FAST OVERCURRENT PROTECTION (ILIM PIN) A dedicated current limiting pin (ILIM) is provided to protect the part from pulse-by-pulse overcurrent events. When the threshold is crossed, the PWM pulse is terminated. This action is independent of any programming of the fast OCP flag. The next switching cycle resumes normally. Additional actions can be programmed (see Table 5). The OCP comparator on the ILIM pin can accept positive or negative signals; the pin is referred to PGND (power ground) and has programmable level shifting current sources (see Table 5). These sources can be changed during normal operation to adapt to the level at which the overcurrent protection is triggered.

Figure 7. Current Sense Configuration response in Register 0xFE00. EEPROM of the ADP1047/ADP1048.

comparator and a fast comparator. therefore, the response of this OVP is relatively slow. using the VOUT_OV_FAULT_LIMIT register (Register 0x40). The programmed value is the dc average voltage. threshold using Register 0xFE50. external resistor divider to match the divider applied to VFB. sensing the output voltage to improve system reliability. and take the appropriate programmed action. threshold is set using a DAC. Table 6. Programmable Options for Fast Overvoltage Protection (Fast OVP)

has its own dedicated voltage reference. The detailed control loop configuration is illustrated in Figure 14. k is related to the switching frequency. used to calculate all stability criteria for the power supply. optimize different operating conditions.

• Low line current filter
• High line current filter
• Fast voltage compensation filter The ADP1047/ADP1048 can be configured to switch auto- matically between the high and low line filters when the rms value of the ac line crosses the programmed threshold between the high and low lines. (The high line threshold is programmed in Register 0xFE35; the low line threshold is programmed in Register 0xFE36.) The ADP1047/ADP1048 check for the value of the rms input voltage at each half line cycle. When a transition between the high and low line threshold is detected, the part waits for four full line cycles before switching to the correct filter at the zero crossing of the input line cycle. This is done to avoid spurious transitions due to a missing or distorted voltage line cycle. During soft start, one of four combinations of filters can be used, depending on whether the fast loop mode is enabled and whether the high line or low line is detected for soft start (see Table 8). 09696-010+ VFB HV (z)VREF VEA + IL IREF DUTY CYCLE HI (z) VAC V2AC_RMS

Figure 14. Control Loop Digital Filters Table 8. Summary of the PFC Digital Compensation Filters for Soft Start

The switching frequency of the PWM outputs can be programmed from 30 kHz to 400 kHz using Register 0xFE1B, Bits[5:0] (see Table 9). Table 9. Switching Frequency Settings from 30 kHz to 400 kHz (Register 0xFE1B, Bits[5:0])

early warning for the host system, thereby increasing reliability. Five main parameters are related to ac line detection.

• V AC_THRESHOLD_SET (Register 0xFE25)
• V AC_THRESHOLD_READ (Register 0xFE26)
• MIN_AC_PERIOD_SET (Register 0xFE27)
• MAX_AC_PERIOD_SET (Register 0xFE28) AC Line Period and Zero Crossing The input ac line period is measured every half period of the ac line cycle and is reported in the V AC_LINE_PERIOD register (Register 0xFE85). During the first 40 ms, the ac line period is measured between two consecutive falling crossings of the threshold value, which is set in the V AC_THRESHOLD_SET register (Register 0xFE25, Bits[6:0]). The ac line period is then measured between two consecutive falling crossings and compared to the average value of the input line voltage, which is calculated during each half line period. The V AC average reading can be found in the V AC_ THRESHOLD_READ register (Register 0xFE26, Bits[6:0]). If the measured period is larger than MAX_AC_PERIOD_SET or smaller than MIN_AC_PERIOD_SET, the default, MAX_AC_ PERIOD_SET, is used as the value of the period. As shown in Figure 17, the two consecutive crossing points, B and C, are used to determine the zero-crossing point of the ac line. The middle point between B and C is calculated as the zero-crossing point. This information is used by the control loop, as well as the power metering block. VAC AVERAGE (REG 0xFE26) VAC THRESHOLD (REG 0xFE25) HALF AC LINE PERIOD AB C 09696-013

Figure 17. AC Line Period Detection

The PSON signal is used to enable or disable the PFC stage. soft start procedure, as shown in Figure 21. turn-on is not relevant with mechanical relays). start time programmed in Register 0xFE2D, Bits[2:0]. 728 ms (set in Register 0xFE2D, Bits[2:0]). (that is, two of the rectified half line cycles). two of the rectified half line cycles). line period, MAX_AC_PERIOD_SET (Register 0xFE28), is used. Figure 21. Soft Start and Inrush Current Control Timing

used to store all of the settings for the thresholds. to accommodate different situations.

• Input current: READ_IIN (Register 0x89)
• Output voltage: READ_VOUT (Register 0x8B)
• Input power: READ_PIN (Register 0x97) 09696-022 CS+ PGND VAC CS– ADC AVG AVG VIN PIN IIN ADC AVG

0 LINE CYCLES

Figure 24. Block Diagram of Power Monitoring Table 10. Data Format and Range for VIN, IIN, PIN, and VOUT

temperature. The limits for the fault conditions are programmable. are exceeded. These flags are described in Table 11 and Table 12. example, POWER_GOOD# = 1 indicates a problem. inverted at the pin to provide active high signals. individually programmable (typically, fault flags). Register 0xFE81, and Register 0xFE82. Table 11. Summary of Manufacturer-Specific Flags MAX_MODULATION 0xFE80[7] The maximum modulation limit is reached. MIN_MODULATION 0xFE80[6] The minimum modulation limit is reached. (one of the two voltage dividers is probably disconnected or malfunctioning). the period is used and this flag is set. SOFT_START 0xFE80[1] The system is in soft start sequence; fast loop filter is in use. EEPROM_UNLOCKED 0xFE81[6] EEPROM is unlocked and its contents can be written. EEPROM_CRC 0xFE81[5] The downloaded contents of the EEPROM are incorrect. SYNC_LOCK 0xFE81[1] External synchronization frequency is locked.

the programmed action takes place as shown in Figure 25. mation, see the PMBus Fault Flag Response section.

001 TO 110 = TRY 1 TO 6 TIMES

Figure 25. Standard PMBus Fault Response Table 12. Summary of Standard PMBus Flags Implemented on the ADP1047/ADP1048 overvoltage flag: Register 0x7A[7] and Register 0xFE80[4] (FAST_OVP). CML 0x78[1] Communications, memory, or logic fault. NONE_OF_THE_ABOVE 0x78[0] A fault or warning not listed in Register 0x78[7:1]. in Register 0x7C, Bits[7:0]). Register 0xFE81, and Register 0xFE82). pin. The POWER_GOOD# flag is an inverted version of the PGOOD pin. UNKNOWN 0x79[8] A fault or warning not listed in Bits[15:1].

Data Sheet ADP1047/ADP1048 Rev. 0 | Page 27 of 84 Name Address Description Action STATUS_VOUT (0x7A) VOUT_OV_FAULT 0x7A[7] The output voltage is above the VOUT_OV_FAULT_LIMIT. Programmable VOUT_OV_WARN 0x7A[6] The output voltage is above the VOUT_OV_WARN_LIMIT. VOUT_UV_WARN 0x7A[5] The output voltage is below the VOUT_UV_WARN_LIMIT. VOUT_UV_FAULT 0x7A[4] The output voltage is below the VOUT_UV_FAULT_LIMIT. Programmable STATUS_INPUT (0x7C) VIN_OV_FAULT 0x7C[7] The input voltage on VAC is larger than the value in VIN_OV_FAULT_LIMIT. Programmable VIN_UV_WARN 0x7C[5] The input voltage on VAC is smaller than the value in VIN_UV_WARN_LIMIT. VIN_UV_FAULT 0x7C[4] The input voltage on VAC is smaller than the value in VIN_UV_FAULT_LIMIT. Programmable VIN_LOW 0x7C[3] VAC is lower than VIN_OFF. This signal shuts down the power supply. Can set AC_OK flag IIN_OC_FAULT 0x7C[2] The input current measured on the CS ADC is larger than the value in IIN_OC_FAULT_LIMIT. Programmable IIN_OC_WARN 0x7C[1] The input current measured on the CS ADC is larger than the value in IIN_OC_WARN_LIMIT. Can set AC_OK flag PIN_OP_WARN 0x7C[0] Input overpower warning. STATUS_TEMPERATURE (0x7D) OT_FAULT 0x7D[7] The measured temperature is above the value set in OT_FAULT_LIMIT. Programmable OT_WARN 0x7D[6] The measured temperature is above the value set in OT_WARN_LIMIT. PMBus FAULT FLAG RESPONSE All standard PMBus fault response registers follow the same format. The six standard PMBus fault response registers are

• VOUT_OV_FAULT_RESPONSE (Register 0x41)
• VOUT_UV_FAULT_RESPONSE (Register 0x45)
• OT_FAULT_RESPONSE (Register 0x50)
• VIN_OV_FAULT_RESPONSE (Register 0x56)
• VIN_UV_FAULT_RESPONSE (Register 0x5A)
• IIN_OC_FAULT_RESPONSE (Register 0x5C) The standard PMBus fault response registers are composed of eight bits: Bits[7:6] define the response type, Bits[5:3] define the retry settings, and Bits[2:0] contain the delay information. Bits[7:6] define the response type as follows:
• Bits[7:6] = 00 (ignore). When the corresponding fault flag is set, no action is taken and the power supply continues to operate normally.
• Bits[7:6] = 01 or 10 (shutdown and retry). When the cor- responding fault flag is set, the system shuts down and then retries for the number of times programmed in Bits[5:3]. The difference between the 01 and 10 options is that when Bits[7:6] = 01, a debounce (programmed in Bits[2:0]) is applied to the flag. Bits[7:6] = 11 (disable output). When the corresponding fault flag is set, the system does not enter a shutdown/soft start sequence. Instead, the output is disabled indefinitely until the flag is cleared. Care must be taken when selecting this option because it may cause the system to stall in an endless loop. Concurrent Faults When multiple faults occur at the same time, the state machine executes the response that has the highest priority. Flag priority is determined by the response of the faults as determined by Bits[7:6]. The higher the number in these two bits, the higher the priority. For example, if OVP is programmed to disable the output (Bits[7:6] = 11) and OCP is programmed to shut down and retry after a delay (Bits[7:6] = 01), and both faults occur at the same time, the OVP action is executed first. If the OVP con- dition is cleared and the OCP flag is still set, the programmed action for OCP is executed. If two or more faults occur at the same time and all the faults have the same response priority, the fault with the smallest retry setting takes priority. For example, if one fault has a retry setting programmed to 011 and the other has a retry setting of 001, the lower number of retries is executed.

in some cases, operate on a pulse-by-pulse basis. tion (see the Fast Overcurrent Protection (ILIM Pin) section).

• 01 (shut down and soft start). The power supply is shut down, and a soft start sequence is initiated after the delay that is programmed in the IIN_OC_FAULT_RESPONSE register (Register 0x5C, Bits[2:0]). 10 (shutdown and wait for PSON). After the number of switching cycles programmed in Bits[5:4], the power supply is shut down until the PSON signal is received. 11 (disable the PWM until the flag is cleared). After the number of switching cycles programmed in Bits[5:4], the PWM is disabled until the flag is cleared; no soft start is initiated. FAST OVP Flag Response (Register 0xFE01) The fast OVP flag responds to an overvoltage condition on the programmable comparator connected to the OVP pin. This comparator constantly monitors the output voltage and its operation (see the Fast Overvoltage Protection (OVP Pin) section). Four different actions can be programmed for this flag. 00 (ignore, do nothing). No action is taken.
• 01 (shut down and soft start). The power supply is shut down, and a soft start sequence is initiated after the delay programmed in the VOUT_OV_FAULT_RESPONSE register (Register 0x41, Bits[2:0]). 10 (immediate shutdown and wait for PSON). The power supply is shut down until the PSON signal is received. 11 (disable the PWM until the flag is cleared). The PWM is disabled until the flag is cleared; no soft start is done. OLP Flag Response (Register 0xFE02) The OLP flag responds to differences between the OVP and VFB pins. Open-loop protection detects a difference in voltage in excess of ~100 mV , which equates to approximately 6.6% of the full-scale range (see the Open-Loop Protection section). Four different actions can be programmed for this flag.
• 00 (ignore, do nothing). No action is taken.
• 01 (shut down and soft start). The power supply is shut down, and a soft start sequence is initiated after the delay programmed in the VOUT_OV_FAULT_RESPONSE register (Register 0x41, Bits[2:0]).
• 10 (immediate shutdown and wait for PSON). The power supply is shut down until the PSON signal is received. 11 (disable the PWM until the flag is cleared). The PWM is disabled until the flag is cleared; no soft start is done. VDD and VCORE OV Flag Response (Register 0xFE03 and Register 0xFE04) These two flags respond to an overvoltage condition on the VDD (3.3 V) and VCORE (2.5 V) rails. These rails must be properly decoupled and filtered to guarantee proper operation of the digital controller. The controller can be programmed to ignore the flags or to shut down and restart. A debounce time of 2.56 μs or 660 μs can be set. The controller can also be instructed to reload the contents of the EEPROM upon restart or to resume operation without reloading the EEPROM contents. Reloading the contents of the EEPROM to RAM prevents device malfunction if the RAM contents have been corrupted during the overvoltage condition. 09696-024 BLANKING AND DEBOUNCE TERMINATE PWM PULSE FAST OCPILIM FLAG SET, PROGRAMMED ACTIONS TIMEOUT

1 TO 8 TIMES

Figure 26. Fast OCP Flag

• Input voltage measurement (Register 0x88)
• Output voltage measurement (Register 0x8B)
• Input current measurement (Register 0x89)
• Input power measurement (Register 0x97)
• Temperature measurement (Register 0xFE86) FIRST ERROR FAULT The ADP1047/ADP1048 provide a FLAG_FAULT_ID register (Register 0xFE07) that records the first fault that causes a system shutdown. For example, if the overtemperature (OT) fault causes the system to shut down, the OT_FAULT flag (0011) is stored in the FLAG_ FAULT_ID register (Register 0xFE07, Bits[3:0]). In addition, the flag ID of the fault that occurred before the fault that caused the system shutdown is included in Bits[7:4] of Register 0xFE07. The contents of this register are stored until read by the user. The flag ID is also saved in EEPROM when the shutdown occurs. In this way, it is possible to determine the cause of a shutdown in case of system failure. OVERTEMPERATURE PROTECTION (OTP) If the temperature sensed at the RTD pin exceeds the program- mable fault threshold, the OTP flag is set, and the power supply can be programmed to shut down. A PTC or NTC thermistor can be used. To set the fault and warning thresholds for OTP , program Register 0xFE19 and Register 0xFE1A, respectively. To set the temperature hysteresis for the fault and warning thresholds, program Register 0xFE3F. The response to an OTP fault flag is programmable in Register 0x50. AC_OK AND PGOOD SIGNALS The ADP1047/ADP1048 have two digital status pins: AC_OK and PGOOD. Both signals represent an OR function for a pro- grammable list of internal flags. Users can blank some of these flags to tailor the AC_OK and PGOOD signals to their needs using Register 0xFE0B and Register 0xFE0A, respectively. When the signals on the AC_OK and PGOOD pins are set, the corresponding internal flag is also set. The programmable delay block acts like a debounce. That is, the signal must be active for at least the duration of the programmed delay before the flag is set. The debounce times for the AC_OK and PGOOD pins can be programmed separately in Register 0xFE05. 09696-025 REG 0xFE0A PROGRAMMABLE DELAY BLOCK PGOOD_FLAGS_LIST (PROGRAMMABLE LIST OF FLAGS) PGOOD REG 0xFE0B PROGRAMMABLE DELAY BLOCK AC_OK_FLAGS_LIST (PROGRAMMABLE LIST OF FLAGS) AC_OK

Figure 27. AC_OK and PGOOD Signals Table 13. Flags Available to Program the AC_OK and PGOOD Pins 1 To blank one or more flags so that the AC_OK or PGOOD pin ignores it, set the corresponding bit to 1 in Register 0xFE0A or Register 0xFE0B.

Data Sheet ADP1047/ADP1048 Rev. 0 | Page 33 of 84 POWER SUPPLY SYSTEM CALIBRATION AND TRIM The ADP1047/ADP1048 allow the entire power supply to be calibrated and trimmed digitally in the production environ- ment. The device can calibrate items including the output voltage, input voltage, input current, and input power, and it can trim for tolerance errors introduced by sense resistors, current transformers, and resistor dividers, as well as for its own internal circuitry. The part comes factory trimmed at 90% of the input range at a

3.3 V supply, but it can be re-trimmed by the user to compen-

sate for the errors introduced by external components. With the exception of the gain and offset trim registers for input power, the trim registers must be unlocked for write access. To unlock the trim registers, write to the TRIM_PASSWORD register (Register 0xD6). OUTPUT VOLTAGE (VFB) CALIBRATION AND TRIM The voltage sense inputs are optimized for sensing signals at 90% of the input range and cannot sense signals greater than 1.6 V . In a high voltage system, a resistor divider is required to reduce the high voltage signal to below 1.6 V . It is recommended that the high voltage signal be reduced to 1 V for best perfor- mance. The resistor divider can introduce errors, which must be trimmed out as follows: Turn on the power supply with no load attached. The output voltage is divided down by the feedback resistor divider to supply 1 V across the VFB and AGND pins. 2. Use a calibrated multimeter to perform the output voltage reading. Adjust the VFB ADC gain trim register (Register 0xFE41) until the power supply outputs the exact value in the READ_VOUT register (Register 0x8B). INPUT VOLTAGE (VAC) GAIN AND OFFSET TRIM The input voltage sense point on the power rail requires an external resistor divider to bring the signal within the operating input range of the V AC ADC (0 V to 1.6 V). The resistor divider can introduce errors, which must be trimmed out as follows: 1. Apply the maximum line voltage value to the input of the power supply. The V AC resistor divider divides this voltage down at the V AC pin. The V AC resistor divider is programmed in linear format using the VIN scale monitor register (Register 0xFE3B). 2. Adjust the V AC ADC gain trim register (Register 0xFE40) until the V AC value (Register 0x88, READ_VIN) equals the input voltage reading from a calibrated multimeter. This step trims for errors in the resistor divider network. For V AC offset trim, adjust the value in Register 0xFE53. CURRENT SENSE GAIN AND OFFSET TRIM The current sense can be calibrated digitally to remove any errors due to external components. Apply the maximum load to the output with the low line input voltage. 2. To match the input current reading at the maximum nominal input current, adjust the CS ADC gain trim register until the CS value (Register 0x89, READ_IIN) equals the measured result of the input current from calibrated equipment. If the 500 mV input range is used, adjust Register 0xFE42. If the 750 mV range is used, adjust Register 0xFE7E. For CS offset trim, adjust the values in Register 0xFE54 (500 mV input range) or Register 0xFE7F (750 mV input range). INPUT POWER GAIN AND OFFSET TRIM The input power trim has separate trim registers for high line and low line input. Apply the maximum load to the output with the low line input voltage. 2. Adjust the power metering gain trim for low line input register (Register 0xFE34) until the input power value in the READ_PIN register (Register 0x97) equals the measured result of the input power from calibrated equipment. Apply the maximum load to the output with the high line input voltage. 4. Adjust the power metering gain trim for high line input register (Register 0xFE8F) until the input power value in the READ_PIN register (Register 0x97) equals the measured result of the input power from the calibrated equipment. For input power offset trim, adjust the values in Register 0xFE33 (for low line input) and Register 0xFE8E (for high line input).

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 34 of 84 PMBus DIGITAL COMMUNICATION The PMBus slave allows a device to interface to a PMBus- compliant master device as specified by the PMBus Power System Management Protocol Specification (Revision 1.1, February 5, 2007). The PMBus slave is a 2-wire interface that can be used to communicate with other PMBus-compliant devices and is compatible in a multimaster, multislave bus configuration. The function of the PMBus slave is to decode the command sent from the master device and respond as requested. Communi- cation is established using an I2C-like 2-wire interface with a clock line (SCL) and data line (SDA). The PMBus slave is designed to externally move chunks of 8-bit data (bytes) while maintaining compliance with the PMBus protocol. The PMBus protocol is based on the SMBus Specification (Version 2.0, August 2000). The SMBus specification is, in turn, based on the Philips I2C Bus Specification (Version 2.1, January 2000). The PMBus incorporates the following features:

• Slave operation on multiple device systems
• 7-bit addressing
• 100 kHz and 400 kHz data rates
• General call address support
• Support for clock low extension
• Separate multiple byte receive and transmit FIFO
• Extensive fault monitoring OVERVIEW The PMBus slave module is a 2-wire interface that can be used to communicate with other PMBus-compliant devices. Its trans- fer protocol is based on the Philips I2C transfer mechanism. The ADP1047/ADP1048 are always configured as slave devices in the overall system. The ADP1047/ADP1048 communicate with the master device using one data pin (SDA) and one clock pin (SCL). Because the ADP1047/ADP1048 are slave devices, they cannot generate the clock signal. However, they are capable of clock- stretching the SCL line to put the master device in a wait state when they are not ready to respond to the master’s request. Communication is initiated when the master device sends a command to the PMBus slave device. Commands can be read or write commands, in which case, data is transferred between the devices in a byte wide format. Commands can also be send commands, in which case, the command is executed by the slave device upon receiving the stop bit. The stop bit is the last bit in a complete data transfer, as defined in the PMBus/I communication protocol. During communication, the master and slave devices send acknowledge (A) or no acknowledge ) bits as a method of handshaking between devices. See the PMBus specification for a more detailed description of the communication protocol. When communicating with the master device, it is possible for illegal or corrupted data to be received by the PMBus slave device. In this case, the PMBus slave device should respond to the invalid command or data, as defined by the PMBus specifi- cation, and indicate to the master device that an error or fault condition has occurred. This method of handshaking can be used as a first level of defense against programming of the slave device that can potentially damage the chip or system. The PMBus specification defines a set of generic PMBus commands that is recommended for a power management system. However, each PMBus device manufacturer can choose to implement and support certain commands as it deems fit for its system. In addition, the PMBus device manufacturer can choose to implement manufacturer-specific commands whose functions are not included in the generic PMBus command set. The list of standard PMBus and manufacturer-specific commands can be found in the Standard PMBus Commands Supported by the ADP1047/ADP1048 section and the Manufacturer-Specific PMBus Command section. PMBus ADDRESS Control of the ADP1047/ADP1048 is implemented via the I2C interface. The ADP1047/ADP1048 are connected to the bus as slave devices under the control of a master device. The PMBus address of the ADP1047/ADP1048 is set by connecting an external resistor from the ADD pin to ground. Table 14 lists the recommended resistor values and associated PMBus addresses. Eight different addresses can be used.

Table 14. PMBus Address Settings mended that 1% tolerance resistors be used on the ADD pin.

Figure 42. Block Read Protocol

• The receive buffer of the slave device is full and must be read before continuing. This prevents a data overflow condition.
• The slave device is not ready to send data that the master has requested. Note that the slave device can stretch the SCL line only during the low period. Also, whereas the I 2C specification allows indefinite stretching of the SCL line, the PMBus specification limits the maximum time that the SCL line can be stretched, or held low, to 25 ms, after which the device must release the communication lines and reset its state machine. GENERAL CALL SUPPORT The PMBus slave is capable of decoding and acknowledging a general call address. The PMBus device responds to both its own address and the general call address (0x00). The general call address enables all devices on the PMBus to be written to simultaneously. Note that all PMBus commands must start with the slave address with the R/W bit cleared (set to 0), followed by the command code. This is also true when using the general call address to communicate with the PMBus slave device. FAST MODE Fast mode (400 kHz) uses essentially the same mechanics as the standard mode of operation; the electrical specifications and timing are most affected. The PMBus slave is capable of communicating with a master device operating in standard mode (100 kHz) or fast mode. FAULT CONDITIONS The PMBus protocol provides a comprehensive set of fault conditions that must be monitored and reported. These fault conditions can be grouped into two major categories: commu- nication faults and monitoring faults. Communication faults are error conditions associated with the data transfer mechanism of the PMBus protocol. Monitoring faults are error conditions associated with the operation of the PMBus device, such as output overvoltage protection, and are specific to each PMBus device. These fault conditions are described in the Power Supply System and Fault Monitoring section. TIMEOUT CONDITION A timeout condition occurs if any single SCL clock pulse is held low for longer than the t TIMEOUT of 25 ms (min). Upon detecting the timeout condition, the PMBus slave device has 10 ms to abort the transfer, release the bus lines, and be ready to accept a new start condition. The device initiating the timeout is required to hold the SCL clock line low for at least t TIMEOUT MAX = 35 ms, guaranteeing that the slave device is given enough time to reset its communication protocol.

Data Sheet ADP1047/ADP1048 Rev. 0 | Page 37 of 84 DATA TRANSMISSION FAULTS Data transmission faults occur when two communicating devices violate the PMBus communication protocol, as specified in the PMBus specification. See the PMBus specification for more information about each fault condition. Corrupted Data, PEC (Item 10.8.1) Parity error checking. Not supported. Sending Too Few Bits (Item 10.8.2) Transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been sent. Not supported; any transmitted data is ignored. Reading Too Few Bits (Item 10.8.3) Transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been read. Not supported; any received data is ignored. Host Sends or Reads Too Few Bytes (Item 10.8.4) If a host ends a packet with a stop condition before the required bytes are sent/received, it is assumed that the host intended to stop the transfer. Therefore, the PMBus does not consider this to be an error and takes no action, except to flush any remain- ing bytes in the transmit FIFO. Host Sends Too Many Bytes (Item 10.8.5) If a host sends more bytes than are expected for the corres- ponding command, the PMBus slave considers this a data transmission fault and responds as follows:

• NACKs all unexpected bytes as they are received
• Flushes and ignores the received command and data
• Sets the CML bit in the STATUS_BYTE register Host Reads Too Many Bytes (Item 10.8.6) If a host reads more bytes than are expected for the corres- ponding command, the PMBus slave considers this a data transmission fault and responds as follows:
• Sends all 1s (0xFF) as long as the host continues to request data
• Sets the CML bit in the STATUS_BYTE register Device Busy (Item 10.8.7) The PMBus slave device is too busy to respond to a request from the master device. Not supported. DATA CONTENT FAULTS Data content faults occur when data transmission is successful, but the PMBus slave device cannot process the data that is received from the master device. Improperly Set Read Bit in the Address Byte (Item 10.9.1) All PMBus commands start with a slave address with the R/W bit cleared (set to 0), followed by the command code. If a host starts a PMBus transaction with R/W set in the address phase (equivalent to an I2C read), the PMBus slave considers this a data content fault and responds as follows:
• ACKs the address byte
• NACKs the command and data bytes
• Sends all 1s (0xFF) as long as the host continues to request data
• Sets the CML bit in the STATUS_BYTE register Invalid or Unsupported Command Code (Item 10.9.2) If an invalid or unsupported command code is sent to the PMBus slave, the code is considered to be a data content fault, and the PMBus slave responds as follows:
• NACKs the illegal/unsupported command byte and data bytes
• Flushes and ignores the received command and data
• Sets the CML bit in the STATUS_BYTE register Reserved Bits (Item 10.9.5) Accesses to reserved bits are not a fault. Writes to reserved bits are ignored, and reads from reserved bits return 0. Write to Read-Only Commands If a host performs a write to a read-only command, the PMBus slave considers this a data content fault and responds as follows: NACKs all unexpected data bytes as they are received
• Flushes and ignores the received command and data
• Sets the CML bit in the STATUS_BYTE register Note that this is the same error described in the Host Sends Too Many Bytes (Item 10.8.5) section. Read from Write-Only Commands If a host performs a read from a write-only command, the PMBus slave considers this a data content fault and responds as follows:
• Sends all 1s (0xFF) as long as the host continues to request data
• Sets the CML bit in the STATUS_BYTE register Note that this is the same error described in the Host Reads Too Many Bytes (Item 10.8.6) section.

into two major blocks: the INFO block and the main block. into 16 pages, each page containing 512 bytes. able for the read, write, and erase operations to the EEPROM. in the EEPROM through the EEPROM controller. operation to Page 0 or Page 1. how to unlock the EEPROM, see the Unlock EEPROM section. using the EEPROM_PAGE_ERASE command (Register 0xD4). Figure 43. Example Erase Command must first be erased (set high) for that byte to be writable. as that byte has not been written to a low previously. using the EEPROM_ADDR_OFFSET command (Register 0xD3). EEPROM, starting from the fifth byte of that page. Set number of return bytes = 3.

1. Read three bytes from Page 4.

1 AA DATA BYTE

bytes for any single transaction.

Data Sheet ADP1047/ADP1048 Rev. 0 | Page 39 of 84 WRITE OPERATION (BYTE WRITE AND BLOCK WRITE) Before performing a write to Page 2 through Page 15 of the main block, the user must first unlock the EEPROM (see the Unlock EEPROM section). Write to Page 0 and Page 1 Page 0 and Page 1 of the main block are reserved for storing the default settings and user settings, respectively. The user cannot perform a direct write operation to Page 0 or Page 1 using the EEPROM_DATA_xx commands. If the user writes to Page 0, Page 1 returns a no acknowledge. To program the register con- tents of Page 1 of the main block, it is recommended that the STORE_USER_ALL command be used (Command Code 0x15). See the Save Register Settings to the User Scratch Pad section. Write to Page 2 Through Page 15 The data in the EEPROM main block can be programmed (written to) one byte at a time or in multiple bytes in series using the EEPROM_DATA_xx commands (Command Code 0xB0 to Command Code 0xBF). Before executing this command, the user can program the offset from the page boundary where the first byte is written using the EEPROM_ADDR_OFFSET command (Register 0xD3). If the targeted page has not yet been erased, the user can erase the page as described in the Main Block Page Erase (Page 2 to Page 15) section. In the following example, four bytes are written to Page 9, starting from the 256 th byte of that page. 1. Set address offset = 256. AS PAAA 0x01 0x000xD3WSLAVE ADDRESS 09696-146 MASTER TO SLAVE SLAVE TO MASTER 2. Write four bytes to Page 9. ASA A BYTE COUNT = 40xB9WSLAVE ADDRESS 09696-147 MASTER TO SLAVE SLAVE TO MASTER PAA ...DATA BYTE 1 DATA BYTE 4 Note that the block write command can write a maximum of 256 bytes for any single transaction. EEPROM PASSWORD On power-up, the EEPROM is locked and protected from accidental writes or erases. Only reads from Page 2 to Page 15 are allowed when the EEPROM is locked. Before any data can be written (programmed) to the EEPROM, the EEPROM must be unlocked for write access. After it is unlocked, the EEPROM is opened for reading, writing, and erasing. On power-up, Page 0 and Page 1 are also protected from read access, and the EEPROM must first be unlocked to read these pages. Unlock EEPROM To unlock the EEPROM, perform two consecutive writes with the correct password (default = 0xFF) using the EEPROM_ PASSWORD command (Register 0xD5). The EEPROM_ UNLOCKED flag (Bit 6 of Register 0xFE81) is set to indicate that the EEPROM is unlocked for write access. Lock EEPROM To lock the EEPROM, write any byte other than the correct password using the EEPROM_PASSWORD command (Register 0xD5). The EEPROM unlock flag is cleared to indicate that the EEPROM is locked from write access. Change EEPROM Password T o change the EEPROM password, the EEPROM must first be unlocked. To change the EEPROM password, first write the correct password using the EEPROM_PASSWORD command (Register 0xD5). Immediately write the new password using the EEPROM_PASSWORD command. The password is now changed to the new password. DOWNLOADING EEPROM SETTINGS TO INTERNAL REGISTERS Download User Settings to Registers The user settings are stored in Page 1 of the EEPROM main block. These settings are downloaded from the EEPROM into the registers under the following conditions:

• On power-up. The user settings are automatically down- loaded into the internal registers, powering the part up in a state previously saved by the user. On execution of the RESTORE_USER_ALL command (Command Code 0x16). This command allows the user to force a download of the user settings from the EEPROM main block, Page 1, into the internal registers. Download Factory Settings to Registers The factory default settings are stored in Page 0 of the EEPROM main block. The factory settings can be downloaded from the EEPROM into the internal registers using the RESTORE_ DEFAULT_ALL command (Command Code 0x12). When this command is executed, the EEPROM password is also reset to the factory default setting of 0xFF.

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 40 of 84 SAVING REGISTER SETTINGS INTO EEPROM The register settings cannot be saved to the factory scratch pad located in Page 0 of the EEPROM main block. This is to prevent the user from accidentally overriding the factory trim settings and default register settings. Save Register Settings to the User Scratch Pad The register settings can be saved to the user scratch pad located in Page 1 of the EEPROM main block using the STORE_USER_ALL command (Command Code 0x15). Before this command can be executed, the EEPROM must first be unlocked for writing (see the Unlock EEPROM section). After the register settings are saved to the user scratch pad, any subsequent power cycle automatically downloads the latest stored user information from the EEPROM into the internal registers. Note that execution of the STORE_USER_ALL command automatically performs a page erase to Page 1 of the EEPROM main block, after which the registers are stored in EEPROM. Therefore, it is important to wait at least 35 ms for the operation to complete before executing the next PMBus command. EEPROM CRC CHECKSUM As a simple method of checking that the values downloaded from EEPROM and the internal registers are consistent, a CRC checksum is implemented.

• When the data from the internal registers is saved to the EEPROM (Page 1 of the main block), the total number of 1s from all the registers is counted and written into the EEPROM as the last byte of information. This is called the CRC checksum.
• When the data is downloaded from the EEPROM into the internal registers, a similar counter that sums all 1s from the values loaded into the registers is saved. This value is compared with the CRC checksum from the previous upload operation. If the values match, the download operation was successful. If the values differ, the EEPROM download operation failed, and the EEPROM_CRC fault flag is set (Register 0xFE81, Bit 5). To read the EEPROM CRC checksum value, execute the EEPROM_CRC_CHKSUM command (Register 0xD1). This command returns the CRC checksum accumulated in the counter during the download operation. Note that the CRC checksum is an 8-bit cyclical accumulator that wraps around to 0 when 255 is reached.

for the latest software and a user guide. Figure 44. ADP1047/ADP1048 GUI Main Window

implemented in registers, which share the same hexadecimal value as the PMBus command code. Table 15. Standard PMBus Commands

implemented in registers, which share the same hexadecimal value as the PMBus command code. Table 16. Manufacturer-Specific Commands

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 44 of 84 Command Code Command Name 0xFE8F Power metering gain trim for high line input 0xFE90 Current loop filter gain for low line input and light load 0xFE91 Current loop filter zero for low line input and light load 0xFE92 Current loop filter gain for high line input and light load 0xFE93 Current loop filter zero for high line input and light load Command Code Command Name 0xFE94 Smart VOUT power reading 0xFE95 IBAL configuration (ADP1048 only) 0xFE96 Debug Flag 0 0xFE97 Debug Flag 1 0xFE98 Debug Flag 2 0xFE99 Debug Flag 3 0xFE9A Debug Flag 4 0xFE9B Debug Flag 5

Table 17. Register 0x01—OPERATION 7 Enable R/W This bit determines the device response to the OPERATION command. 0 = immediate off (no sequencing). [5:4] Margin control R These bits set the output voltage margin level and are hardcoded to a value of 00. margined. These bits are hardcoded to a value of 01. Table 18. Register 0x02—ON_OFF_CONFIG 4 Power-up control R/W Set the device power-up response. 0 = device powers up when power is present.

3 Command

R/W Control how the device responds to the OPERATION command. 0 = ignore the OPERATION command. 1 = the OPERATION command must be set to 1 to enable the device (in addition to setting Bit 2). 2 Pin enable R/W Control how the device responds to the value of the control pin (PSON). 0 = ignore the control pin (PSON). 1 = the control pin must be asserted to enable the device (in addition to setting Bit 3).

1 Control pin

R/W Set the polarity of the control pin (PSON).

0 Power-down

transfer to the output as fast as possible). Code 0x03, send byte, no data. This command clears all fault bits in all registers simultaneously. Table 19. Register 0x10—WRITE_PROTECT 7 Write Protect 1 R/W Setting this bit disables writes to all commands except for WRITE_PROTECT. EEPROM_PAGE_ERASE, ON_OFF_CONFIG, and VOUT_COMMAND. Code 0x12, send byte, no data. This command downloads the factory default parameters from EEPROM into operating memory. Code 0x15, send byte, no data. This command copies the entire contents of operating memory into EEPROM (Page 1 of the main block).

Code 0x16, send byte, no data. This command downloads the stored user settings from EEPROM into operating memory. This register allows host systems to determine the capabilities of the PMBus device. Table 20. Register 0x19—CAPABILITY

7 Packet error

R Always reads as 0. Packet error checking (PEC) is not supported. 4 SMBALERT# R Always reads as 0. SMBALERT# pin and SMBus alert response protocol not supported. This register sets and reads the format (linear, VID, direct) and exponents for VOUT related commands. Table 21. Register 0x20—VOUT_MODE [7:5] Mode R Return the output voltage data format. This bit is hardcoded to use linear format. This register sets VOUT to the configured value. Table 22. Register 0x21—VOUT_COMMAND [15:12] RSVD R Reserved. Always reads as 0000. [11:0] Mantissa R/W Mantissa (Y[11:0]) used in VOUT linear mode format (X = Y × 2N). This register sets the K factor = V ADC/VOUT . Table 23. Register 0x29—VOUT_SCALE_LOOP [15:11] Exponent R/W Write the exponent (N) in twos complement format for K = Y × 2N. 10 RSVD R Always reads as 0. [9:0] Mantissa R/W Mantissa (Y[9:0]) used in K linear mode format (K = Y × 2N).

This register sets the Kr factor = VOUT/V ADC. Table 24. Register 0x2A—VOUT_SCALE_MONITOR [13:11] Exponent R/W Write the exponent (N) in twos complement format for Kr = Y × 2N. 10 RSVD R Always reads as 0. [9:0] Mantissa R/W Mantissa (Y[9:0]) used in Kr linear mode format (Kr = Y × 2N). This register sets the value of the input voltage to start power conversion. Table 25. Register 0x35—VIN_ON exponent register (Register 0xFE39, Bits[5:3]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N). exponent register (Register 0xFE39, Bits[5:3]). This register sets the value of the input voltage to stop power conversion. Table 26. Register 0x36—VIN_OFF exponent register (Register 0xFE39, Bits[5:3]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N). exponent register (Register 0xFE39, Bits[5:3]). This register sets the accurate overvoltage threshold measured at the PFC output that causes an overvoltage fault condition. Table 27. Register 0x40—VOUT_OV_FAULT_LIMIT the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). This register instructs the device on actions to take due to an output overvoltage fault condition. Table 28. Register 0x41—VOUT_OV_FAULT_RESPONSE [7:6] Response R/W These bits determine the device response to an output overvoltage fault condition. persists, retry the number of times specified by the retry setting (Bits[5:3]).

time between restart attempts is specified by Delay Time 2 (Bits[2:0]). [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. This register sets the accurate overvoltage threshold measured at the PFC output that causes an overvoltage warning condition. Table 29. Register 0x42—VOUT_OV_WARN_LIMIT the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage warning condition. Table 30. Register 0x43—VOUT_UV_WARN_LIMIT the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage fault condition. Table 31. Register 0x44—VOUT_UV_FAULT_LIMIT the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N).

This register instructs the device on actions to take due to an output undervoltage fault condition. Table 32. Register 0x45—VOUT_UV_FAULT_RESPONSE [7:6] Response R/W These bits determine the device response to an output undervoltage fault condition. persists, retry the number of times specified by the retry setting (Bits[5:3]). time between restart attempts is specified by Delay Time 2 (Bits[2:0]). [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. This register instructs the device on actions to take due to an overtemperature fault condition. Table 33. Register 0x50—OT_FAULT_RESPONSE [7:6] Response R/W These bits determine the device response to an overtemperature fault condition. persists, retry the number of times specified by the retry setting (Bits[5:3]).

time between restart attempts is specified by Delay Time 2 (Bits[2:0]). [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. This register sets the overvoltage threshold measured at the PFC input that causes an overvoltage fault condition. Table 34. Register 0x55—VIN_OV_FAULT_LIMIT exponent register (Register 0xFE39, Bits[5:3]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N). exponent register (Register 0xFE39, Bits[5:3]). This register instructs the device on actions to take due to an input overvoltage fault condition. Table 35. Register 0x56—VIN_OV_FAULT_RESPONSE [7:6] Response R/W These bits determine the device response to an input overvoltage fault condition. persists, retry the number of times specified by the retry setting (Bits[5:3]).

time between restart attempts is specified by Delay Time 2 (Bits[2:0]). [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. This register sets the undervoltage threshold measured at the PFC input that causes an undervoltage warning condition. Table 36. Register 0x58—VIN_UV_WARN_LIMIT exponent register (Register 0xFE39, Bits[5:3]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N). exponent register (Register 0xFE39, Bits[5:3]). This register sets the undervoltage threshold measured at the PFC input that causes an undervoltage fault condition. Table 37. Register 0x59—VIN_UV_FAULT_LIMIT exponent register (Register 0xFE39, Bits[5:3]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N). exponent register (Register 0xFE39, Bits[5:3]).

This register instructs the device on actions to take due to an input undervoltage fault condition. Table 38. Register 0x5A—VIN_UV_FAULT_RESPONSE [7:6] Response R/W These bits determine the device response to an input undervoltage fault condition. persists, retry the number of times specified by the retry setting (Bits[5:3]). time between restart attempts is specified by Delay Time 2 (Bits[2:0]). [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. This register sets the accurate overcurrent threshold measured at the PFC input that causes an overcurrent fault condition. Table 39. Register 0x5B—IIN_OC_FAULT_LIMIT exponent register (Register 0xFE39, Bits[10:6]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in current linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in current linear mode format (X = Y × 2N).

This register instructs the device on actions to take due to an input overcurrent fault condition. Table 40. Register 0x5C—IIN_OC_FAULT_RESPONSE [7:6] Response R/W These bits determine the device response to an input overcurrent fault condition. persists, retry the number of times specified by the retry setting (Bits[5:3]). time between restart attempts is specified by Delay Time 2 (Bits[2:0]). [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. This register sets the accurate overcurrent threshold measured at the PFC input that causes an overcurrent warning condition. Table 41. Register 0x5D—IIN_OC_WARN_LIMIT exponent register (Register 0xFE39, Bits[10:6]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in current linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in current linear mode format (X = Y × 2N).

This register sets the upper input power (W) threshold that causes an input overpower warning condition. Table 42. Register 0x6B—PIN_OP_WARN_LIMIT exponent register (Register 0xFE39, Bits[2:0]). [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in power linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in power linear mode format (X = Y × 2N). This register returns the lower byte of the STATUS_WORD register. A value of 1 in this register indicates that a fault has occurred. Table 43. Register 0x78—STATUS_BYTE 7 BUSY R 1 = device was busy and unable to respond. 6 PSON_OFF R 1 = device is not providing power to the output. 5 VOUT_OV R 1 = output overvoltage fault. 4 IOUT_OC R 1 = output overcurrent fault. 3 VIN_UV R 1 = input undervoltage fault. 2 TEMPERATURE R 1 = temperature fault or warning. 1 CML R 1 = communications, memory, or logic fault.

0 NONE_OF_THE_

R 1 = fault or warning not listed in Bits[7:1]. A value of 1 in this register indicates that a fault has occurred. Table 44. Register 0x79—STATUS_WORD 15 VOUT R 1 = output voltage fault or warning. 14 IOUT/POUT R 1 = output current or output power fault or warning. 13 INPUT R 1 = input voltage, input current, or input power fault or warning. 12 MFR R 1 = manufacturer-specific fault or warning. 11 POWER_GOOD# R 1 = POWER_GOOD is negated. 10 FANS R 1 = fan or airflow fault or warning. 9 OTHER R Always reads as 0. 8 UNKNOWN R 1 = fault or warning not listed in Bits[15:1]. 7 BUSY R 1 = device was busy and unable to respond. 6 PSON_OFF R 1 = device is not providing power to the output. 5 VOUT_OV R 1 = output overvoltage fault. 4 IOUT_OC R 1 = output overcurrent fault. 3 VIN_UV R 1 = input undervoltage fault. 2 TEMPERATURE R 1 = temperature fault or warning. 1 CML R 1 = communications, memory, or logic fault. R 1 = fault or warning not listed in Bits[7:1].

A value of 1 in this register indicates that a fault has occurred. Table 45. Register 0x7A—STATUS_VOUT 7 VOUT_OV_FAULT R 1 = output overvoltage fault. 6 VOUT_OV_WARN R 1 = output overvoltage warning. 5 VOUT_UV_WARN R 1 = output undervoltage warning. 4 VOUT_UV_FAULT R 1 = output undervoltage fault. A value of 1 in this register indicates that a fault has occurred. Table 46. Register 0x7C—STATUS_INPUT 7 VIN_OV_FAULT R 1 = input overvoltage fault. 5 VIN_UV_WARN R 1 = input undervoltage warning. 4 VIN_UV_FAULT R 1 = input undervoltage fault. 3 VIN_LOW R 1 = device is off due to insufficient input voltage; that is, input voltage is below the turn-off threshold. 2 IIN_OC_FAULT R 1 = input overcurrent fault. 1 IIN_OC_WARN R 1 = input overcurrent warning. 0 PIN_OP_WARN R 1 = input overpower warning. A value of 1 in this register indicates that a fault has occurred. Table 47. Register 0x7D—STATUS_TEMPERATURE 7 OT_FAULT R 1 = overtemperature fault. 6 OT_WARN R 1 = overtemperature warning. This register returns the input voltage (V) in VIN linear mode format (X = Y × 2N). Table 48. Register 0x88—READ_VIN exponent register (Register 0xFE39, Bits[5:3]). [10:8] High bits R Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N). exponent register (Register 0xFE39, Bits[5:3]). This register returns the input current (A) in current linear mode format (X = Y × 2N). Table 49. Register 0x89—READ_IIN exponent register (Register 0xFE39, Bits[10:6]). [10:8] High bits R Mantissa high bits (Y[10:8]) used in current linear mode format (X = Y × 2N). [7:0] Low byte R Mantissa low byte (Y[7:0]) used in current linear mode format (X = Y × 2N).

This register returns the output voltage (V) in VIN linear mode format (X = Y × 2N). Table 50. Register 0x8B—READ_VOUT VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). This register returns the input power (W) in power linear mode format (X = Y × 2N). Table 51. Register 0x97—READ_PIN exponent register (Register 0xFE39, Bits[2:0]). [10:8] High bits R Mantissa high bits (Y[10:8]) used in power linear mode format (X = Y × 2N). [7:0] Low byte R Mantissa low byte (Y[7:0]) used in power linear mode format (X = Y × 2N). Table 52. Register 0x98—PMBUS_REVISION [7:0] Revision R Return the revision of PMBus that the device is compliant with. Table 53. Register 0x99—MFR_ID [7:0] MFR_ID R Return the manufacturer’s ID. Table 54. Register 0x9A—MFR_MODEL [7:0] Model R Return the manufacturer’s model number. Table 55. Register 0x9B—MFR_REVISION [7:0] Revision R Return the manufacturer’s revision number. block; EEPROM_DATA_01 reads from and writes to Page 1 of the EEPROM main block, and so on.

Table 56. Register 0xD1—EEPROM_CRC_CHKSUM [7:0] CRC checksum R Return the CRC checksum value from the EEPROM download operation. Table 57. Register 0xD2—EEPROM_NUM_RD_BYTES R/W These bits set the number of read bytes returned when using the EEPROM_DATA_xx commands. Table 58. Register 0xD3—EEPROM_ADDR_OFFSET [15:0] Address offset R/W These bits set the address offset of the current EEPROM page. Table 59. Register 0xD4—EEPROM_PAGE_ERASE EEPROM must first be unlocked. Page 0 and Page 1 erase are allowed only in manufacturing test mode. Table 60. Register 0xD5—EEPROM_PASSWORD W Write the password to this register to unlock EEPROM and/or to change the EEPROM password. Table 61. Register 0xD6—TRIM_PASSWORD twice (default 0x00) to unlock the register; write any other value to exit. Code 0xF1, block read/write. This command reads the manufacturer’s data from the EEPROM.

This register instructs the device on actions to take due to a fast overcurrent protection condition. Table 62. Register 0xFE00—CS_FAST_OCP_RESPONSE [7:6] Response R/W These bits determine the device response to a fast overcurrent protection condition. 0 0 Ignore (still terminate the PWM pulse). soft start (use the soft start delay time specified in Register 0x5C, Bits[2:0]). pulse each time), then shut down and wait for the PSON signal to soft start. and wait for the flag to be cleared. output after a fast overcurrent condition is detected. This register instructs the device on actions to take due to a fast overvoltage fault condition. Table 63. Register 0xFE01—OVP_FAST_OVP_RESPONSE [7:6] Response R/W These bits determine the device response to a fast overvoltage condition. 0 0 Ignore (do nothing; PWM continues). 0 1 Shut down and soft start. 1 0 Shut down immediately and wait for the PSON signal. 1 1 Disable the PWM output until the unlatched flag is cleared. This register instructs the device on actions to take due to an open-loop fault condition. Table 64. Register 0xFE02—OLP_RESPONSE [7:6] Response R/W These bits determine the device response to an open-loop fault condition. 0 0 Ignore (do nothing; PWM continues). 0 1 Shut down and soft start. 1 0 Shut down immediately and wait for the PSON signal. 1 1 Disable the PWM output until the unlatched flag is cleared.

This register instructs the device on actions to take due to a VDD overvoltage fault condition. Table 65. Register 0xFE03—VDD3P3_RESPONSE

6 Save first flag ID

R/W 1 = save the first flag ID to EEPROM when the device shuts down. 0 = do not save the first flag ID to EEPROM when the device shuts down. [5:3] Retry wait time R/W These bits determine the retry wait time before the next soft start. Each LSB = 588 ms. 2 Reload EEPROM R/W 1 = reload the contents of EEPROM. 0 = do not reload the contents of EEPROM. 1 Debounce time R/W 1 = 2.56 μs. 0 Ignore VDD OV R/W 1 = ignore the VDD 3.3 V overvoltage fault. 0 = do not ignore the VDD 3.3 V overvoltage fault. This register instructs the device on actions to take due to a VCORE overvoltage fault condition. Table 66. Register 0xFE04—VCORE_RESPONSE R/W 1 = save the first flag ID to EEPROM when the device shuts down. 0 = do not save the first flag ID to EEPROM when the device shuts down. [5:3] Retry wait time R/W These bits determine the retry wait time before the next soft start. Each LSB = 588 ms. 2 Reload EEPROM R/W 1 = reload the contents of EEPROM. 0 = do not reload the contents of EEPROM. 1 Debounce time R/W 1 = 2.56 μs. 0 Ignore VCORE OV R/W 1 = ignore the VCORE overvoltage fault. 0 = do not ignore the VCORE overvoltage fault. This register sets the debounce times for the PGOOD and AC_OK pins. Table 67. Register 0xFE05—PGOOD_AC_OK_DEBOUNCE_SET R/W Debounce from low to high for the AC_OK pin. R/W Debounce from high to low for the AC_OK pin.

R/W Debounce from low to high for the PGOOD pin. R/W Debounce from high to low for the PGOOD pin. This register sets the delay time for PSON and PSOFF . Table 68. Register 0xFE06—PSON_SET [3:2] PSON delay R/W These bits specify the time from when the PSON signal is active to when soft start begins. [1:0] PSOFF delay R/W These bits specify the time from when the PSON signal is cleared to when the device is turned off. This register records the first fault ID that caused the system to shut down. Table 69. Register 0xFE07—FLAG_FAULT_ID [3:0] Fault flag ID R Return the flag fault ID value of the fault that caused the shutdown.

This register blanks the specified flags during soft start (1 = blank, 0 = don’t blank). Table 70. Register 0xFE08—SOFTSTART_FLAGS_BLANK1 7 BLANK_FAST_OVP R/W 1 = ignore fast OVP flag. 6 BLANK_OLP R/W 1 = ignore OLP flag. 5 BLANK_IIN_OC R/W 1 = ignore IIN_OC_FAULT flag. 4 BLANK_VIN_OFF R/W 1 = ignore VIN_OFF flag. 3 BLANK_VIN_OV R/W 1 = ignore VIN_OV flag. 2 BLANK_OT R/W 1 = ignore OT flag. 1 BLANK_VOUT_UV R/W 1 = ignore VOUT_UV flag. 0 BLANK_VOUT_OV R/W 1 = ignore VOUT_OV flag. This register blanks the specified flag during soft start (1 = blank, 0 = don’t blank). Table 71. Register 0xFE09—SOFTSTART_FLAGS_BLANK2 0 BLANK_FAST_OCP R/W 1 = ignore fast OCP flag. This register specifies the flags that are checked to determine the PGOOD pin voltage (1 = ignore flag, 0 = check flag). Table 72. Register 0xFE0A—PGOOD_FLAGS_LIST 7 VOUT_UV_FAULT R/W 1 = ignore VOUT_UV_FAULT flag. 6 VOUT_OV_WARN R/W 1 = ignore VOUT_OV_WARN flag. 5 FAST_OVP R/W 1 = ignore FAST_OVP flag. 4 OLP R/W 1 = ignore OLP flag. 3 FAST_OCP R/W 1 = ignore FAST_OCP flag. 2 IIN_OC_FAULT R/W 1 = ignore IIN_OC_FAULT flag. 1 OT_FAULT R/W 1 = ignore OT_FAULT flag. 0 FAST_LOOP R/W 1 = ignore FAST_LOOP flag. This register specifies the flags that are checked to determine the AC_OK pin voltage (1 = ignore flag, 0 = check flag). Table 73. Register 0xFE0B—AC_OK_FLAGS_LIST 7 VIN_UV_FAULT R/W 1 = ignore VIN_UV_FAULT flag. 6 VIN_UV_WARN R/W 1 = ignore VIN_UV_WARN flag. 5 IIN_OC_FAULT R/W 1 = ignore IIN_OC_FAULT flag. 4 IIN_OC_WARN R/W 1 = ignore IIN_OC_WARN flag. 3 FAST_OCP R/W 1 = ignore FAST_OCP flag. 2 AC_LINE_PERIOD R/W 1 = ignore AC_LINE_PERIOD flag. 1 BROWN_OUT R/W 1 = ignore BROWN_OUT flag. 0 INRUSH R/W 1 = ignore INRUSH flag.

Register 0xFE0C through Register 0xFE13 configure the rising and falling edges of the PWM outputs. Table 74. Register 0xFE0C—PWM Rising Edge Timing (PWM Pin) [7:0] t 1 R/W This register contains the eight MSBs of the 10-bit t1 time. Table 75. Register 0xFE0D—PWM Rising Edge Setting (PWM Pin) Register 0xFE0C, which contains the eight MSBs of the t1 time. 1 Modulate enable R/W 1 = PWM modulation acts on the t1 edge. 0 = no PWM modulation of the t1 edge. 0 t 1 sign R/W 1 = positive sign. Increase of PWM modulation moves t1 right. 0 = negative sign. Increase of PWM modulation moves t1 left. Table 76. Register 0xFE0E—PWM Falling Edge Timing (PWM Pin) [7:0] t 2 R/W This register contains the eight MSBs of the 10-bit t2 time. Table 77. Register 0xFE0F—PWM Falling Edge Setting (PWM Pin) Register 0xFE0E, which contains the eight MSBs of the t2 time. 1 Modulate enable R/W 1 = PWM modulation acts on the t2 edge. 0 = no PWM modulation of the t2 edge. 0 t 2 sign R/W 1 = positive sign. Increase of PWM modulation moves t2 right. 0 = negative sign. Increase of PWM modulation moves t2 left. Table 78. Register 0xFE10—PWM2 Rising Edge Timing (PWM2 Pin) [7:0] t 1 R/W This register contains the eight MSBs of the 10-bit t1 time. Table 79. Register 0xFE11—PWM2 Rising Edge Setting (PWM2 Pin) Register 0xFE10, which contains the eight MSBs of the t1 time. 1 Modulate enable R/W 1 = PWM modulation acts on the t1 edge. 0 = no PWM modulation of the t1 edge. 0 t 1 sign R/W 1 = positive sign. Increase of PWM modulation moves t1 right. 0 = negative sign. Increase of PWM modulation moves t1 left. Table 80. Register 0xFE12—PWM2 Falling Edge Timing (PWM2 Pin) [7:0] t 2 R/W This register contains the eight MSBs of the 10-bit t2 time.

Table 81. Register 0xFE13—PWM2 Falling Edge Setting (PWM2 Pin) bits of Register 0xFE12, which contains the eight MSBs of the t2 time. 1 Modulate enable R/W 1 = PWM modulation acts on the t2 edge. 0 = no PWM modulation of the t2 edge. 0 t 2 sign R/W 1 = positive sign. Increase of PWM modulation moves t2 right. 0 = negative sign. Increase of PWM modulation moves t2 left. Table 82. Register 0xFE14—PWM_SET 4 ADP1048 operation R/W Reserved for the ADP1048 only. 1 = bridgeless PFC operation. 0 = interleaved PFC operation. 3 PWM resolution R/W 1 = 5 ns. 2 PWM enable R/W 1 = disable the PWM output. 1 PWM2 enable R/W 1 = disable the PWM2 output. 0 Go button R/W The PWM settings are updated during the transition of this bit from low to high. Table 83. Register 0xFE15—PWM_LIMIT This register must be unlocked for write access; see Table 61. Table 84. Register 0xFE16—RTD ADC Offset Trim Setting (MSB) 1 Trim polarity R/W 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. reading. The LSBs are specified in Register 0xFE17. This register must be unlocked for write access; see Table 61. Table 85. Register 0xFE17—RTD ADC Offset Trim Setting (LSB) the RTD ADC reading. The MSB is specified in Register 0xFE16, Bit 0.

This register must be unlocked for write access; see Table 61. Table 86. Register 0xFE18—RTD ADC Gain Trim Setting 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] RTD ADC gain trim R/W This value sets the amount of gain trim that is applied to the RTD sensing gain. This register sets the overtemperature fault threshold. The debounce time of the overtemperature fault flag is 100 ms. Table 87. Register 0xFE19—OT_FAULT_LIMIT reading is lower than the threshold set by these bits, the overtemperature fault flag is set. This register sets the overtemperature warning threshold. The debounce time of the overtemperature warning flag is 100 ms. Table 88. Register 0xFE1A—OT_WARN_LIMIT reading is lower than the threshold set by these bits, the overtemperature warning flag is set.

Table 89. Register 0xFE1B—Switching Frequency Setting [5:0] Switching frequency R/W This register sets the switching frequency of the PWM outputs.

Table 90. Register 0xFE1C—Low Power Switching Frequency Setting threshold set in Register 0xFE32 and the smart switching frequency is enabled.

Table 91. Register 0xFE1D—Frequency Dithering Set [6:0] Dithering period R/W Sets the period for updating the switching frequency. Each LSB corresponds to 40 μs.

Table 92. Register 0xFE1E—Frequency Synchronization Set Table 93. Register 0xFE20—Voltage Loop Filter Gain R/W Determines the digital filter gain of the PFC voltage loop. Table 94. Register 0xFE21—Voltage Loop Filter Zero R/W Determines the position of the digital filter zero of the PFC voltage loop. Table 95. Register 0xFE22—Fast Voltage Loop Filter Gain R/W Determines the digital filter gain of the PFC fast voltage loop. Table 96. Register 0xFE23—Fast Voltage Loop Filter Zero R/W Determines the position of the digital filter zero of the PFC fast voltage loop. Table 97. Register 0xFE24—Fast Voltage Loop Enable

7 Enable fast loop

voltage is within the regulation band (Bits[6:5]).

1 Enable fast loop

R/W Enables the fast loop filter during soft start. 1 = fast loop filter is used during soft start. 0 = normal filter is used during soft start. 0 Enable fast loop R/W Enables the fast loop filter with a delay. The threshold is programmed in Bits[6:5]. 1 = enable fast loop filter. 0 = disable fast loop filter. This register sets the input voltage threshold for input ac line period measurement and zero-crossing detection. Table 98. Register 0xFE25—VAC_THRESHOLD_SET

7 Enable automatic

R/W 1 = enable automatic threshold. 0 = disable automatic threshold. [6:0] Threshold voltage R/W These bits set the threshold voltage to detect the ac line frequency and period if Bit 7 is set to 0. Table 99. Register 0xFE26—VAC_THRESHOLD_READ automatic threshold is enabled in Register 0xFE25, Bit 7. Table 100. Register 0xFE27—MIN_AC_PERIOD_SET Table 101. Register 0xFE28—MAX_AC_PERIOD_SET

Table 102. Register 0xFE29—Current Loop Filter Gain for Low Line Input Table 103. Register 0xFE2A—Current Loop Filter Zero for Low Line Input Table 104. Register 0xFE2B—Current Loop Filter Gain for High Line Input Table 105. Register 0xFE2C—Current Loop Filter Zero for High Line Input Table 106. Register 0xFE2D—Soft Start Set [5:3] Soft start delay time R/W These bits set the delay time between the inrush signal and the beginning of the soft start. [2:0] Soft start time R/W These bits set the soft start time.

Table 107. Register 0xFE2E—Inrush Set [4:3] Timer R/W These bits set the timer for the VIN_LOW flag measurement. [2:0] Inrush delay time R/W These bits set the inrush signal delay time after the BROWN_OUT flag goes low. Table 108. Register 0xFE2F—FAST_OVP_FAULT_RISE This threshold is programmable from 1 V to 1.5 V. Each LSB increments the threshold by 3.844 mV. A value of 0x00 corresponds to a 1 V threshold; a value of 0x3F corresponds to a 1.492 V threshold. Table 109. Register 0xFE30—FAST_OVP_FAULT_FALL This threshold is programmable from 1 V to 1.5 V. Each LSB increments the threshold by 3.844 mV. A value of 0x00 corresponds to a 1 V threshold; a value of 0x3F corresponds to a 1.492 V threshold. Table 110. Register 0xFE31—Fast OVP Debounce Time Setting [1:0] OVP debounce time R/W These bits set the fast OVP debounce time.

Table 111. Register 0xFE32—Low Power Mode Operation Threshold lower than this value, the PFC enters low power mode. Table 112. Register 0xFE33—Power Metering Offset Trim for Low Line Input 7 Offset trim polarity R/W 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. to 0.0625/128 of the full input power. Table 113. Register 0xFE34—Power Metering Gain Trim for Low Line Input 7 Gain trim polarity R/W 1 = negative gain trim is introduced. 0 = positive gain trim is introduced. to 0.0625/128 of the input power. Table 114. Register 0xFE35—High Line Limit R/W When the input voltage is higher than this value, the current loop filter for high line input is used. Table 115. Register 0xFE36—Low Line Limit [7:0] VAC low line threshold R/W When the input voltage is lower than this value, the current loop filter for low line input is used. This register must be unlocked for write access; see Table 61. Table 116. Register 0xFE37—ILIM_TRIM 4 Trim current direction R/W 1 = source trim current (ILIM + ILIM_TRIM). 0 = sink trim current (ILIM − ILIM_TRIM). [3:0] ILIM trim R/W These bits set the trim current. Each LSB corresponds to ILIM/64. Table 117. Register 0xFE38—Voltage Loop Output [7:0] Voltage loop output R Return the output of the voltage control loop.

This register reads and writes exponents (N) for PIN, VIN, and IIN. Table 118. Register 0xFE39—Exponent R/W Sets the exponent for the input current. R/W Sets the exponent for the input voltage. [2:0] Input power exponent R/W Sets the exponent for the input power. Table 119. Register 0xFE3A—Read Update Rate from one half ac line cycle are averaged over the programmed number of half ac line cycles. Table 120. Register 0xFE3B—VIN Scale Monitor [13:11] Exponent R/W Write the exponent (N) in twos complement format (KVIN = Y × 2N). [9:0] Mantissa R/W Mantissa (Y[9:0]) used in KVIN linear mode format (KVIN = Y × 2N). Table 121. Register 0xFE3C—IIN_GSENSE [15:11] Exponent R/W Write the exponent (N) in twos complement format (IIN_GSENSE = Y × 2N). [9:0] Mantissa R/W Mantissa (Y[9:0]) used in IIN linear mode format (IIN_GSENSE = Y × 2N).

Table 122. Register 0xFE3D—CS Fast OCP Blank time is exceeded, all PWM outputs are disabled for the remainder of the switching cycle. Table 123. Register 0xFE3E—CS Fast OCP Setting 1 CS_RANGE_SELECT R/W CS ADC input range. 0 SEL_RESVI_REF R/W This bit sets the reference current for the CS+ and CS− common-mode level shift. 1 = select the RES VI reference current (changing RRES changes this current). 0 = select the band gap generated reference current. Table 124. Register 0xFE3F—Temperature Hysteresis is reset when the RTD ADC value is higher than the temperature warning limit plus hysteresis.

This register must be unlocked for write access; see Table 61. Table 125. Register 0xFE40—VAC ADC Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] VAC ADC gain trim R/W This value calibrates the VAC voltage sense gain. This register must be unlocked for write access; see Table 61. Table 126. Register 0xFE41—VFB ADC Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] VFB ADC gain trim R/W This value calibrates the output voltage sense gain. This register must be unlocked for write access; see Table 61. Table 127. Register 0xFE42—CS ADC Gain Trim for 500 mV Range 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] CS ADC gain trim R/W This value calibrates the CS current sense gain. Table 128. Register 0xFE43—IBAL Gain (ADP1048 Only) 7 IBAL enable R/W 1 = enable current balancing. 0 = disable current balancing and reset the IBAL integrator. [6:0] IBAL gain R/W The gain can be set from 0 to 127. Table 129. Register 0xFE44—Smart VOUT Low Power Threshold (P1) is VOL1 for low line input and VOH1 for high line input. Table 130. Register 0xFE45—Smart VOUT High Power Threshold (P2) voltage is VOL2 for low line input and VOH2 for high line input.

Table 131. Register 0xFE46—Smart VOUT Low Line (VOL1) [10:0] VOL1 R/W These bits set the output voltage under low power mode operation with low line input. Table 132. Register 0xFE47—Smart VOUT Low Line (VOL2) [10:0] VOL2 R/W These bits set the output voltage under high power mode operation with low line input. Table 133. Register 0xFE48—Smart VOUT High Line (VOH1) [10:0] VOH1 R/W These bits set the output voltage under low power mode operation with high line input. Table 134. Register 0xFE49—Smart VOUT High Line (VOH2) [10:0] VOH2 R/W These bits set the output voltage under high power mode operation with high line input. Table 135. Register 0xFE4A—Smart VOUT Upper Limit (VOH) Table 136. Register 0xFE4B—Smart VOUT Super High Line R/W These bits set the input voltage value as a super high line limit. Table 137. Register 0xFE4C—SYNC Delay and the rising edge of PWM. Each LSB corresponds to 80 ns resolution.

Table 138. Register 0xFE4D—SMART_VOUT_SUPER_HIGH_LINE_HYS voltage minus the voltage hysteresis. Table 139. Register 0xFE4E—POWER_HYS mode if the input power is higher than the low power threshold plus the power hysteresis. Table 140. Register 0xFE4F—Advanced Feature Enable

6 Enable current loop

R/W 1 = current loop feedforward is enabled. 0 = current loop feedforward is disabled.

5 Enable light load

R/W 1 = light load current loop filter is enabled. 0 = light load current loop filter is disabled.

4 Enable phase

R/W 1 = phase shedding is enabled. 0 = phase shedding is disabled. This bit applies to the ADP1048 only.

3 Enable smart

R/W 1 = smart switching frequency is enabled. 0 = smart switching frequency is disabled.

2 Enable smart output

R/W 1 = smart output voltage is enabled. 0 = smart output voltage is disabled.

1 Enable PWM

R/W 1 = PWM frequency synchronization is enabled. 0 = PWM frequency synchronization is disabled.

0 Enable frequency

R/W 1 = frequency dithering is enabled. 0 = frequency dithering is disabled. Table 141. Register 0xFE50—VOUT_OV_FAULT_HYS lower than VOUT_OV_FAULT_LIMIT minus this hysteresis. Table 142. Register 0xFE51—VIN_UV_FAULT_HYS higher than VIN_UV_FAULT_LIMIT plus this hysteresis.

This register must be unlocked for write access; see Table 61. Table 143. Register 0xFE53—VAC ADC Offset Trim [7:0] VAC ADC offset trim R/W This register calibrates the VAC ADC offset (the offset is always subtracted from the ADC output). This register must be unlocked for write access; see Table 61. Table 144. Register 0xFE54—CS ADC Offset Trim for 500 mV Range This register must be unlocked for write access; see Table 61. Table 145. Register 0xFE7E—CS ADC Gain Trim for High (750 mV) Range 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] CS ADC gain trim R/W This register calibrates the CS current sense gain. This register must be unlocked for write access; see Table 61. Table 146. Register 0xFE7F—CS ADC Offset Trim for High (750 mV) Range Table 147. Register 0xFE80—Latched Flag 0 7 MAX_MODULATION R 1 = maximum modulation limit is reached. 6 MIN_MODULATION R 1 = minimum modulation limit is reached. 5 OLP R 1 = one of the two voltage dividers is probably disconnected or malfunctioning. 4 FAST_OVP R 1 = the threshold set for the comparator on the OVP pin has been crossed. 2 BROWN_OUT R 1 = VAC is lower than the value stored in VIN_ON (Register 0x35). 1 SOFT_START R 1 = system is in soft start sequence; fast loop filter is in use. 0 INRUSH R 1 = INRUSH control relay is off.

Table 148. Register 0xFE81—Latched Flag 1 6 EEPROM_UNLOCKED R 1 = EEPROM is unlocked and its contents can be written. 5 EEPROM_CRC R 1 = downloaded EEPROM contents are incorrect. (the address falls too close to the threshold between two addresses). 3 LOW_LINE R 1 = input voltage is higher than the high line threshold. 2 FAST_OCP R 1 = the threshold set for the comparator on the ILIM pin has been crossed. 1 SYNC_LOCK R 1 = external synchronization frequency is locked. the input voltage. A value of 1 means that the output of the AC_OK pin is low. Table 149. Register 0xFE82—Latched Flag 2 5 LOW_POWER R 1 = input power has dropped below the threshold for low power mode operation. 4 FAST_LOOP R 1 = fast loop compensation filter is in use. 3 VCORE_OV R 1 = an overvoltage condition is present on the VCORE rail. 2 VDD_3.3V_OV R 1 = an overvoltage condition is present on the VDD rail. 1 VDD_3.3V_UV R 1 = an undervoltage condition is present on the VDD rail. Table 150. Register 0xFE84—PWM Value [7:0] PWM value R Return the eight MSBs of the PWM value (10 bits). Table 151. Register 0xFE85—VAC_LINE_PERIOD [7:0] VAC line period R Return the measured period on the VAC pin signal. Each LSB corresponds to 163.84 μs. Table 152. Register 0xFE86—Read Temperature ADC [15:0] RTD temperature R Return the measured temperature in ADC 12-bit format. Table 153. Register 0xFE8E—Power Metering Offset Trim for High Line Input 7 Offset trim polarity R/W 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. to 0.0625/128 of the full input power.

Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input 7 Gain trim polarity R/W 1 = negative gain trim is introduced. 0 = positive gain trim is introduced. to 0.0625/128 of the input power. Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. Table 156. Register 0xFE91—Current Loop Filter Zero for Low Line Input and Light Load input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. Table 157. Register 0xFE92—Current Loop Filter Gain for High Line Input and Light Load input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. Table 158. Register 0xFE93—Current Loop Filter Zero for High Line Input and Light Load input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. Table 159. Register 0xFE94—Smart VOUT Power Reading [15:0] Power reading R Return the average power reading for smart output voltage (averaged over 16 full line cycles).

Table 160. Register 0xFE95—IBAL Configuration (ADP1048 Only) 7 IBAL disconnect R/W 1 = disconnect the output of the current balance block from the PWM outputs. 0 = connect the output of the current balance block to the PWM outputs. 6 IBAL at load transient R/W 0 = disable current balancing when the fast loop is triggered. 1 = enable current balancing when the fast loop is triggered. It is recommended that this bit be set to 0.

3 IBAL at low power

balancing block reaches the limit. It is recommended that this bit be set to 1. Table 161. Register 0xFE96—Debug Flag 0 7 OT_WARN R 1 = measured temperature is above the value of OT_WARN_LIMIT. 6 OT_FAULT R 1 = measured temperature is above the value of OT_FAULT_LIMIT. 5 TEMPERATURE R 1 = temperature fault or warning. 4 UNKNOWN R 1 = fault or warning not listed in Register 0x79, Bits[15:1]. 3 MFR_FAULT R 1 = manufacturer-specific fault or warning (Register 0xFE80, Register 0xFE81, Register 0xFE82). 2 PSON R 1 = PSON signal (hardware or software) is inactive. condition of the output voltage. A value of 1 means that the output of the PGOOD pin is low. the input voltage. A value of 1 means that the output of the AC_OK pin is low. Table 162. Register 0xFE97—Debug Flag 1 7 EEPROM_UNLOCKED R 1 = EEPROM is unlocked and its contents can be written. 6 EEPROM_CRC R 1 = downloaded EEPROM contents are incorrect. (the address falls too close to the threshold between two addresses). 4 FAST_LOOP R 1 = fast loop compensation filter is in use. 3 MAX_MODULATION R 1 = maximum modulation limit is reached. 2 MIN_MODULATION R 1 = minimum modulation limit is reached. 1 SOFT_START R 1 = system is in soft start sequence; fast loop filter is in use. 0 SYNC_LOCK R 1 = external synchronization frequency is locked. Table 163. Register 0xFE98—Debug Flag 2 7 VIN_UV R 1 = general input undervoltage fault (same as Register 0x7C, Bit 4). 6 VIN_LOW R 1 = VAC is lower than VIN_OFF (Register 0x36). This signal shuts down the power supply. 5 VIN_UV_FAULT R 1 = input voltage on VAC is smaller than the value in VIN_UV_FAULT_LIMIT (Register 0x59). 4 VIN_UV_WARN R 1 = input voltage on VAC is smaller than the value in VIN_UV_WARN_LIMIT (Register 0x58). 3 LOW_LINE R 1 = input voltage is higher than the high line threshold. 2 BROWN_OUT R 1 = VAC is lower than the value stored in VIN_ON (Register 0x35). 1 CML R 1 = communications, memory, or logic fault. 0 VDD_3.3V_OV R 1 = an overvoltage condition is present on the VDD rail.

Table 164. Register 0xFE99—Debug Flag 3 7 VIN_OV_FAULT R 1 = input voltage on VAC is larger than the value in VIN_OV_FAULT_LIMIT (Register 0x55). 6 VCORE_OV R 1 = an overvoltage condition is present on the VCORE rail. 5 PIN_OP_WARN R 1 = input overpower warning.

3 IIN_OC_WARN R 1 = input current measured on the CS ADC is larger than the value in IIN_OC_WARN_LIMIT

1 FAST_OCP R 1 = the threshold set for the comparator on the ILIM pin has been crossed. 0 INPUT R 1 = input voltage, input current, or input power fault or warning. Table 165. Register 0xFE9A—Debug Flag 4 7 OLP R 1 = one of the two voltage dividers is probably disconnected or malfunctioning. 6 FAST_OVP R 1 = the threshold set for the comparator on the OVP pin has been crossed. 5 VOUT_UV_FAULT R 1 = output voltage is below the VOUT_UV_FAULT_LIMIT (Register 0x44). 4 VOUT_UV_WARN R 1 = output voltage is below the VOUT_UV_WARN_LIMIT (Register 0x43). 3 VOUT_OV_WARN R 1 = output voltage is above the VOUT_OV_WARN_LIMIT (Register 0x42). 2 VOUT_OV_FAULT R 1 = output voltage is above the VOUT_OV_FAULT_LIMIT (Register 0x40). (Register 0x7A, Bit 7 and Register 0xFE80, Bit 4 (FAST_OVP)). 0 VOUT R 1 = any fault on output voltage (overvoltage, undervoltage, fast OVP , or accurate OVP). Table 166. Register 0xFE9B—Debug Flag 5 2 LOW_POWER R 1 = input power has dropped below the threshold for low power mode operation. 1 VDD_3.3V_UV R 1 = an undervoltage condition is present on the VDD rail. 0 INRUSH R 1 = INRUSH control relay is off.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 45. 24-Lead Shrink Small Outline Package [QSOP]

ADP1047/ADP1048 Data Sheet Rev. 0 | Page 84 of 84 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D09696-0-9/11(0)