ADP1043A

ADP1043A (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 72

Technical content

Digital Controller for Isolated Power Supply Applications Data Sheet ADP1043A Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Integrates all typical controller functions Digital control loop Remote and local voltage sense Primary and secondary side current sense PWM control Synchronous rectifier control Current sharing Integrated programmable loop filter I2C interface Extensive fault detection and protection Extensive programming Fast calibration EEPROM Standalone or microcontroller control

APPLICATIONS

Isolated dc-to-dc power supplies Redundant power supplies Parallel power supplies Server, storage, network, and communications infrastructure GENERAL DESCRIPTION The ADP1043A is a secondary side power supply controller IC designed to provide all the functions that are typically needed in an ac-to-dc or isolated dc-to-dc control application. The ADP1043A is optimized for minimal component count, maximum flexibility, and minimum design time. Features include remote voltage sense, local voltage sense, primary and secondary side current sense, pulse-width modulation (PWM) generation, and hot-swap sense and control. The control loop is digital with an integrated programmable digital filter. Protection features include current limiting, ac sense, undervoltage lockout (UVLO), and overvoltage protection (OVP). The built-in EEPROM provides extensive programming of the integrated loop filter, PWM signal timing, inrush current, and soft start timing and sequencing. Reliability is improved through a built-in checksum and redundancy of critical circuits. A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features. The industry-standard I 2C bus provides access to the many moni- toring and system test functions. The ADP1043A is available in a 32-lead LFCSP and operates from a single 3.3 V supply. TYPICAL APPLICATION CIRCUIT RES RTDADD VCORE FLAGIN PSON PGOOD2 PGOOD1 SDA SCL VDD DGND AGND OUTA OUTB OUTC OUTD OUTAUX CS1 SR1 SR2 ACSNS PGND VS1 GATE VS3+ VS3– SHAREo SHAREi DRIVER ADuM1410DRIVER VS2 DRIVER PFC AC INPUT LOAD MICROCONTROLLER CS2– CS2+ VDD 08501-001 Figure 1.

Rev. A | Page 2 of 72 TABLE OF CONTENTS PWM and Sync Rect Outputs (OUTA, OUTB, OUTC,

Rev. A | Page 3 of 72

REVISION HISTORY

5/2017—Rev. 0 to Rev. A 10/2009—Revision 0: Initial Version

Rev. A | Page 4 of 72 The ADP1043A is a secondary side controller for switch mode power supplies (SMPS). It is designed for use in isolated redun- dant applications. The ADP1043A integrates the typical functions that are needed to control a power supply. These include

• Output voltage sense and feedback
• Digital loop filter compensation
• PWM generation
• Current sharing
• Current, voltage, and temperature sense
• OrFET control
• Housekeeping and I2C interface
• Calibration and trimming The main function of controlling the output voltage is performed using the feedback ADCs, the digital loop filter, and the PWM block. The feedback ADCs use a multipath approach (patent pending). The ADP1043A combines a high speed, low resolution (fast and coarse) ADC and a low speed, high resolution (slow and accurate) ADC. Loop compensation is implemented using the digital filter. This PID (proportional, integral, derivative) filter is implemented in the digital domain to allow easy programming of filter characteristics, which is of great value in customizing and debugging designs. The PWM block generates up to seven programmable PWM outputs for control of FET drivers and synchronous rectification FET drivers. This programmability allows many traditional and unique switching topologies to be realized. A current share bus interface provides for parallel power supplies. The part also has hot-swap OrFET sense and control for N + 1 redundant power supplies. Conventional power supply housekeeping features, such as remote and local voltage sense and primary and secondary side current sense, are included. An extensive set of protections is offered, including overvoltage protection (OVP), overcurrent protection (OCP), overtemperature protection (OTP), undervoltage protec- tion (UVP), ground continuity monitoring, and ac sense. All these features are programmable through the I 2C bus inter- face. This bus interface is also used to calibrate the power supply. Other information, such as input current, output current, and fault flags, is also available through the I 2C bus interface. The internal EEPROM can store all programmed values and allows standalone control without a microcontroller. A free, downloadable GUI is available that provides all the necessary software to program the ADP1043A. For more information about the GUI, contact Analog Devices, Inc., for the latest software and a user guide. The ADP1043A operates from a single 3.3 V supply and is specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM 08501-002 RES SHAREo VS3– VS3+ PGOOD1 VDD GATE VS1 ACSNS PGND OUTA OUTB SR1 SR2 OUTC OUTD CS1 PSON SCL SDA CS2– CS2+ VS2 VCORE AGND OUTAUX PGOOD2 SHAREi FLAGIN DGND RTDADD ADC ADC ADC ADC UVLO PWM ENGINE VREF LDO ADC ADC 8kB EEPROM DIGITAL CORE I2C INTERFACE PWM OSC Figure 2.

Rev. A | Page 5 of 72 SPECIFICATIONS VDD = 3.3 V , TA = −40°C to +85°C, unless otherwise noted. FSR = full-scale range. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY VDD VDD 3.1 3.3 3.6 V IDD IDD Normal operation (PSON is high) 20 mA Power supply off (PSON is low) 15 mA During EEPROM programming (40 ms) IDD + 8 mA POWER-ON RESET Power-On Reset VDD rising 3.05 V UVLO VDD falling 2.75 2.85 2.95 V UVLO Hysteresis 35 mV OVLO 3.7 3.9 4.1 V VCORE PIN Output Voltage TA = 25°C 2.3 2.5 2.7 V OSCILLATOR AND PLL PLL Frequency RES = 49.9 kΩ 190 200 210 MHz OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2 PINS Output Low Voltage VOL Source current = 10 mA 0.4 V Output High Voltage VOH Source current = 10 mA VDD − 0.4 V Rise Time CLOAD = 50 pF 3.5 ns Fall Time CLOAD = 50 pF 1.5 ns AC SENSE PWM and resonant mode Input Voltage Threshold 0.3 0.45 0.65 V Propagation Delay From ACSNS threshold to SR start; resonant mode only 160 ns VS1, VS2, VS3 LOW SPEED ADC Input Voltage Range VIN Differential voltage from VS1, VS2 to PGND, and from VS3+ to VS3− 0 1 1.55 V Sampling Frequency fSAMP 100 Hz Voltage Sense Measurement Accuracy From 0% to 100% of input voltage range −10 +10 % FSR −155 +155 mV From 10% to 90% of input voltage range −2.5 +2.5 % FSR −38.75 +38.75 mV From 900 mV to 1.1 V −1.5 +1.5 % FSR −23.25 +23.25 mV Voltage Sense Measurement Resolution

12 Bits

Voltage Differential from VS3− to PGND −200 +200 mV VS1 OVP Comparator Speed Register 0x2C[2] = 0 300 μs VS1 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS1 2.5 % VS2 and VS3 OVP Comparator Speed Register 0x2C[2] = 0 300 μs VS2 and VS3 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS2 and VS3 2.5 % VS1 HIGH SPEED ADC Sampling Frequency fSAMP 400 kHz Resolution 6 Bits Dynamic Range ±18 mV

Rev. A | Page 6 of 72 Parameter Symbol Test Conditions/Comments Min Typ Max Unit CURRENT SENSE 1 (CS1 PIN) Input Voltage Range VIN 0 1 1.38 V Sampling Frequency fSAMP 100 Hz Current Sense Measurement Accuracy From 10% to 90% of input voltage range −3.0 +3.0 % FSR −41.4 +41.4 mV From 0% to 100% of input voltage range −10 +10 % FSR −138 +138 mV Current Sense Measurement Resolution CS1 Fast OCP Threshold 1.1 1.2 1.3 V CS1 Fast OCP Speed 80 100 ns CS1 Accurate OCP DC Accuracy From 10% to 90% of input voltage range −3.0 +3.0 % FSR −41.4 +41.4 mV CS1 Accurate OCP Speed 10 ms Leakage Current 4.0 μA CURRENT SENSE 2 (CS2+, CS2− PINS) Input Voltage Range VIN Differential voltage from CS2+ to CS2− −100 +225 mV ADC Input Voltage Range LSB = 61.04 μV 0 225 mV Sampling Frequency fSAMP 100 Hz Current Sense Measurement Accuracy From 0 mV to 200 mV −4 +4 mV From 200 mV to 225 mV −15 +15 mV −7.5 +7.5 % FSR Current Sense Measurement Resolution CS2 Accurate OCP Accuracy From 0 mV to 200 mV −4 +4 mV From 200 mV to 225 mV −15 +15 mV −7.5 +7.5 % FSR CS2 Accurate OCP Speed 10 ms Current Sink (High Side) 100 μA Current Source (Low Side) 100 μA Common-Mode Voltage at the CS2+ and CS2− Pins To achieve CS2 measurement accuracy 0.8 1 1.3 V GATE PIN (OPEN DRAIN) Output Low Voltage VOL 0.4 V OrFET PROTECTION (CS2+, CS2−) Low-side current sensing only Accurate OrFET Threshold Accuracy −1.2 0 +1 mV Accurate OrFET Speed 10 ms Fast OrFET Accuracy −25 mV setting −40 −25 −10 mV −50 mV setting −70 −50 −30 mV −75 mV setting −100 −75 −50 mV −100 mV setting −125 −100 −75 mV Fast OrFET Speed Debounce = 40 ns 110 150 ns RTD PIN Input Voltage Range VIN 0 1 1.55 V Current Source RTD resistor = 100 kΩ 9.5 10.8 12 μA RTD ADC Measurement Accuracy From 2% to 20% of input voltage range −1 +1 % FSR From 32 mV to 320 mV −15.5 +15.5 mV From 0% to 100% of input voltage range −10 +10 % FSR From 0 V to 1.55 V −155 +155 mV

Rev. A | Page 7 of 72 Parameter Symbol Test Conditions/Comments Min Typ Max Unit OTP Threshold Accuracy When RTD = 10 kΩ −0.5 +0.5 % FSR −7.75 +7.75 mV When RTD = 100 kΩ −5 +5 % FSR −77.5 +77.5 mV OTP Speed 10 ms OTP Threshold Hysteresis When RTD = 10 kΩ 16 mV PGOOD1, PGOOD2, SHAREo PINS (OPEN DRAIN) Output Low Voltage VOL 0.4 V PSON, FLAGIN, SHAREi PINS (DIGITAL INPUTS) Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.8 V SDA/SCL PINS VDD = 3.3 V Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.8 V Output Low Voltage VOL 0.4 V Leakage Current −5 +5 µA SERIAL BUS TIMING Clock Frequency 100 400 kHz Glitch Immunity tSW 50 ns Bus-Free Time tBUF 4.7 µs Start Setup Time tSU;STA 4.7 µs Start Hold Time tHD;STA 4 µs SCL Low Time tLOW 4.7 µs SCL High Time tHIGH 4 µs SCL, SDA Rise Time tR 1000 ns SCL, SDA Fall Time tF 300 ns Data Setup Time tSU;DAT 250 ns Data Hold Time tHD;DAT 300 ns EEPROM RELIABILITY Endurance1 10,000 Cycles Data Retention2 TJ = 85°C 20 Years 1 Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C. 2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance topic in detail (see www.analog.com).

24 SHAREi

23 SHAREo

22 PGOOD1

21 PGOOD2

20 FLAGIN

19 PSON

18 SDA

17 SCL

1. THE ADP1043A HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE

THAT THE PAD BE SOLDERED TO THE PCB GROUND PLANE. Figure 3. Pin Configuration Table 4. Pin Function Descriptions or better to allow for trimming. 2 AGND Analog Ground. This pin is the ground for the analog circuitry of the ADP1043A. Star connect to DGND. better to allow for trimming. this pin. When using low-side current sensing, place a 10 kΩ resistor between the sense resistor and this pin. used to connect this circuit. 5 CS2+ Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. be used to connect this circuit. 6 ACSNS AC Sense Input. This input is connected upstream of the main inductor through a resistor divider network. The nominal voltage for this circuit is 0.45 V. This signal is referred to PGND. 0.5% or better to allow for trimming. when not in use. This signal is referred to AGND. when not in use. This signal is referred to AGND. 11 OUTA PWM Output for Primary Side Switch. This pin can be di sabled when not in use. This signal is referred to AGND. 12 OUTB PWM Output for Primary Side Switch. This pin can be di sabled when not in use. This signal is referred to AGND. 13 OUTC PWM Output for Primary Side Switch. This pin can be di sabled when not in use. This signal is referred to AGND. 14 OUTD PWM Output for Primary Side Switch. This pin can be di sabled when not in use. This signal is referred to AGND. 15 OUTAUX Auxiliary PWM Output. This pin can be disabled when not in use. This signal is referred to AGND. 16 GATE OrFET Gate Drive Output (Open Drain). This signal is referred to AGND. 17 SCL I 2C Serial Clock Input. This signal is referred to AGND. 18 SDA I 2C Serial Data Input and Output (Open Drain). This signal is referred to AGND.

Rev. A | Page 10 of 72 Pin No. Mnemonic Description 19 PSON Power Supply On Input. This signal is referred to DGND. This is the hardware PSON control signal. It is recom- mended that a 1 nF capacitor be included from the PSON pin to DGND for noise debounce and decoupling. 20 FLAGIN Flag Input. An external signal can be input at this pin to generate a flag condition. 21 PGOOD2 Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD2 flag. This pin is set if any flag is set. 22 PGOOD1 Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD1 flag. This pin is set if any of the following are out of range: power supply, CS1 fast OCP , CS1 accurate OCP , CS2 accurate OCP , UVP , local OVP , or load OVP. 23 SHAREo Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a 2.2 kΩ resistor. When configured as a digital share bus, this pin is a digital output. This signal is referred to AGND. 24 SHAREi Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referred to AGND. 25 DGND Digital Ground. This pin is the ground for the digital circuitry of the ADP1043A. Star connect to AGND. 26 VCORE Output of 2.5 V Regulator. Connect a 100 nF capacitor from this pin to DGND. 28 RTD Thermistor Input. A 100 kΩ thermistor is placed from this pin to AGND. This signal is referred to AGND. 29 ADD Address Select Input. Connect a resistor from ADD to AGND. This signal is referred to AGND. 30 RES Resistor Input. This pin sets up the internal voltage reference for the ADP1043A. Connect a 49.9 kΩ resistor (±0.1%) from RES to AGND. This signal is referred to AGND. 31 VS3− Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. 32 VS3+ Noninverting Remote Voltage Sense Input. This signal is referred to VS3−. Use 0.1% resistors as the resistor divider to connect this circuit. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. Exposed Pad EP The ADP1043A has an exposed thermal pad on the underside of the package. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the PCB ground plane.

monitoring, control, and protection of the power supply output. The voltage information is available through the I2C interface. Supply Calibration and Trim section for more information). of the 16 readings taken during the 1.6 MHz time frame. to the CS1 and CS2 current readings. can switch its low speed regulating point from VS3 to VS1.

12 BITS 12 BITS 12 BITS

6 BITS

Figure 13. Voltage Sense Configuration ADCs goes to the digital filter. rate is 200 kHz, there is 0.6 mV (two LSBs) of quantization noise. because the ADP1043A VS2 ADC input range is 0 V to 1.55 V . because the ADP1043A VS3 ADC input range is 0 V to 1.55 V . output of the VS3 ADC goes to the digital filter. of each ADC is readable through the appropriate value register.

criteria for the power supply. a = filter_pole_register_value/256. b = filter_zero_register_value/256. c = high_frequency_gain_register_value. d = low_frequency_gain_register_value. where fSW is the switching frequency. fC is the crossover frequency. fSW is the switching frequency. At one tenth of the switching frequency, the phase delay is 18°. The GUI incorporates this phase delay into its calculations. current threshold (programmed through Register 0x3B). start filter gain setting (Register 0x5F[1:0]). full-bridge, phase shift topology with synchronous rectification. Figure 14. PWM Pin Assignment recommended that PWM outputs be disabled when not in use. used as a clock reference signal.

the voltage transient caused by a load step. every time that the SR signals are enabled. enough to prevent damage to the FETs that they are controlling. times are programmed using Register 0x69 to Register 0x6F. any PWM. These limits are a percentage of the switching period. pulse skipping can be enabled. period. The modulation high limit is set to (nominal + 50%). evaluating this feature of the ADP1043A (see Figure 15). Figure 15. Setting Modulation Limits (Modulation Range Shown by Arrows) out of the power supply and that the unit can be hot-swapped. is not guaranteed for operation with high-side current sensing. required to turn the OrFET on or off.

• Fault flag (any fault flag can be programmed to turn off the OrFET)
• Fast OrFET control circuit
• Accurate OrFET control circuit Fast OrFET control looks at the reverse voltage across CS2+ and CS2− and is implemented using an analog comparator (see Figure 16). If the voltage difference between CS2+ and CS2− is greater than the fast OrFET threshold programmed in Register 0x30, the OrFET is turned off.

rate, but it is slower than the fast OrFET circuit. −0.5%, 0%, 1%, or 2% of the nominal output voltage (12 V).

• When 12 V < VOUT < OVP , use the accurate OrFET control circuit to turn off the OrFET.
• When VOUT > OVP , use load OVP to turn off the OrFET. In a 12 V application, while in light load mode
• When 12 V < VOUT < OVP , use ACSNS to turn off the OrFET.
• When VOUT > OVP , use load OVP to turn off the OrFET. In a 12 V application, when an internal short circuit occurs, follow this procedure: 1. Use fast OrFET to turn off the OrFET. 2. Use CS1 OCP or VS1 UVP to shut down the unit and restart it. 10kΩ 10kΩ RSENSE 11kΩ 1kΩ OrFET ENABLE THRESHOLD REG 0x30[5:4] OrFET ENABLE OrFET DISABLE FAST OrFET DEBOUNCE REG 0x30[1] ACCURATE OrFET THRESHOLD REG 0x30[7:6] FAST OrFET COMPARATOR DIFFERENTIAL TO SINGLE- ENDED DIFFERENTIAL TO SINGLE- ENDED FAST OrFET THRESHOLD REG 0x30[3:2] FAST OrFET BYPASS REG 0x30[0] CS2 ADC S R Q CS2 VALUE REGISTER CS2– VS1 VS2CS2+ 100µA 100µA REG 0x18[15:4] DRIVER GATE 12V 11kΩ 1kΩ VOUT ACCURATE OrFET DISABLE FLAG FLAGS 08501-016

Figure 16. OrFET Control Circuit Internal Detailed Diagram

Rev. A | Page 18 of 72 VDD When VDD is applied, a certain time elapses before the part is capable of regulating the power supply. When the VDD rises above the power-on reset and UVLO levels, it takes approxi- mately 20 μs for VCORE to reach its operational point of 2.5 V. The EEPROM contents are then downloaded to the registers. The download takes an additional 25 μs (approximately). After the EEPROM download, the ADP1043A is ready for operation. If the ADP1043A is programmed to power up at this time, the soft start ramp begins. VDD/VCORE OVLO The ADP1043A has built-in overvoltage protection (OVP) on its supply rails. When the VDD or VCORE voltage rises above the OVLO threshold, the response can be programmed. This circuit can be set to be ignored, but it is recommended that the user not program the OVP circuit to be ignored. POWER GOOD The ADP1043A has two power-good pins. The PGOOD1 pin and fault flag are set when any of the following conditions are out of range: power supply, CS1 fast OCP , CS1 accurate O C P, CS2 accurate OCP, UVP , local O V P, o r load O V P. The PGOOD2 pin and fault flag are set when any flag is set: power supply, OrFET, CS1 fast OCP , CS1 accurate OCP , CS2 accurate O C P, voltage continuity, U V P, accurate OrFET disable, ACSNS, external flag (FLAGIN), VCORE OV , VDD O V, local O V P, load O V P, OTP , CRC fault, and EEPROM unlocked. If Register 0x2D[3] is set, PGOOD2 looks only at the flags that are not programmed to be ignored. The PGOOD2 pin can also be used as an interrupt pin to notify a host controller that a flag has been set. The polarity of the PGOOD1 and PGOOD2 pins is configured as active low.

soft start routine. All other fault flags are ignored during soft start.

1. The ADP1043A waits for Time t1 before it begins soft start.

The length of t1 is set in Register 0x2C, Bits[4:3].

1. The soft start begins to ramp up the power supply voltage
2. The ADP1043A keeps the OrFET gate signal turned off.
3. The ADP1043A begins to regulate voltage from
4. After the power supply voltage increases above the VS1 UVP
5. After the UVP flag is reset and if all other PGOOD1 fault

Figure 21. Soft Start Timing Diagram

current sharing scheme has no such issues. current information for current sharing. current contribution to the load. and setup conditions, see the product page for the ADP1043A. providing (the higher the current, the larger the digital word). configuration of the digital share bus. Figure 22. Digital Current Share Configuration digital share bus, it waits to begin sharing until the next frame. next start bit. The digital share bus frame is shown in Figure 24. Figure 23. Analog Current Share Configuration

2 STOP BITS

Figure 24. Digital Current Share Frame Timing Diagram

Figure 25 shows the possible signals on the share bus. Figure 25. Share Bus High, Low, and Idle Bits The bus is idle when it is high during the whole period of tBIT. with the digital words of all the other supplies on the bus. the value on the bus, it means that this supply must be a slave. because either of them could be the master. supply must be a slave and it stops communicating. determine whether each unit is the master or a slave. The digital share bus can be configured in various ways. between the remote voltage sense node and the load.

2293 DEC

143 DEC

Figure 26. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus

perature. The limits for the fault conditions are programmable. limits are described in the Fault Registers section. reset. For more information, see Register 0x08 to Register 0x0D. interface. See the Value Registers section for more details. The VS1, VS2, and VS3 ADCs have an input range of 1.55 V. a resistor divider network to provide 1 V at the sense pin. Figure 27. CS1 ADC Frequency Response where fSW is the switching frequency of the power supply.

by programming Register 0x23, Bits[7:6]. 12 bits, which means that the LSB size is 250 mV/4096 = 61.04 μV . The user is limited to an input range of 215 m V. FS is the full-scale voltage drop (37.5 m V, 75 m V, o r 150 mV). RSENSE is the sense resistor value. numbers and discards the eight LSBs. to the full-scale range of the signal that it is measuring. are latched, meaning that they are stored until read by the user. The contents are also reset by a PSON signal. be programmed in the same way as the internal flags. ADP1043A monitors the voltage on the RTD pin. Figure 28. RTD Pin Internal Details match the specific NTC being used. to the OTP flag is programmable.

OCP (see Figure 29). CS1 fast OCP is an analog comparator. switching cycle. This function can be bypassed if not needed. decision is 10 ms. The response to the flag is programmable. 10 ms. The response to the flag is programmable. Figure 29. CS1 OCP Detailed Internal Schematic

The ACSNS circuit performs multiple monitoring functions. not trip during the 5 μs interval, the ACSNS flag is set. topology. This means that a dc blocking capacitor is not necessary. for the feature to operate correctly. dently set to modulate due to the volt-second balance circuit. same direction as the OUTD falling edge (t8). decreased and OUTD is increased. Figure 31. Load Line Settings

Rev. A | Page 27 of 72 POWER SUPPLY CALIBRATION AND TRIM The ADP1043A allows the entire power supply to be calibrated and trimmed digitally in the production environment. It can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors and resistor dividers, as well as its own internal circuitry. The part comes factory trimmed, but it can be retrimmed by the user to compensate for the errors introduced by external components. The ADP1043A allows the user enough trim capability to trim for external components with a tolerance of 0.5% or better. If the ADP1043A is not trimmed in the production environment, it is recommended that components with a 0.1% tolerance be used for the inputs to CS1, CS2, VS1, VS2, VS3+, and VS3− to meet data sheet specifications. CS1 TRIM Using a DC Signal A known voltage (Vx) is applied at the CS1 pin. The CS1 ADC should output a digital code equal to Vx/337 μV. T h e C S 1 gain trim register (Register 0x21) is adjusted until the CS1 ADC value in Register 0x13 reads the correct digital code. Using an AC Signal A known current (Ix) is applied to the PSU input. This current passes through a current transformer, a diode rectifier, and an external resistor (R CS1) to convert the current information to a voltage (Vx). This voltage is fed into the CS1 pin. The voltage (Vx) is calculated as follows: Vx = Ix × (n2/n1) × RCS1 where n2/n1 is the turns ratio of the current transformer. The CS1 ADC should output a digital code equal to Vx/337 μV. The CS1 gain trim register (Register 0x21) is adjusted until the CS1 ADC value in Register 0x13 reads the correct digital code. As described in the CS1 Pin section, the CS1 ADC has a frequency response. To achieve more accurate trimming, the following multiplication factor (M) should be used: where fSW is the switching frequency of the power supply. CS2 TRIM The CS2 trim must compensate for offset and gain errors. The offset error requires both an analog trim and a digital trim. The CS2 ADC range does not begin at 0 V but instead begins at −25 mV to allow it to perform reverse current protection for the OrFET circuit. Therefore, with −25 mV at the CS2 input, the ADC code should read 0. With 0 mV at the CS2 input, the ADC code should read 100 decimal. For this reason, the analog offset trim is performed until the CS2 reading equals 100 decimal (not 0). For this reason, also, the digital trim is required. CS2 Offset Trim It is important to perform the CS2 offset trim as described in the following steps. 1. Set the nominal full-scale sense resistor voltage drop in Register 0x23, Bits[7:6]. 2. Set high-side or low-side current sensing in Register 0x24, Bit 7. 3. Offset errors can be introduced by the external bias resistors and the internal current sources. Apply no-load current across the sense resistor. Adjust the CS2 offset trim value (Register 0x24, Bits[6:0]) until the CS2 value in Register 0x18 reads as close to 100 decimal as possible. 4. Adjust the CS2 digital trim register (Register 0x25) until the CS2 value in Register 0x18 reads 0. The offset trim is now completed, and the ADC code reads 0 if there is no-load current across the sense resistor. CS2 Gain Trim After performing the offset trim, perform the gain trim to remove any mismatch that is introduced by the sense resistor tolerance. The ADP1043A can trim for sense resistors with a tolerance of 1% or better. 1. Apply a known current (IOUT) across the sense resistor. 2. Adjust the CS2 gain trim value (Register 0x23, Bits[5:0]) until the CS2 value in Register 0x18 reads the value calculated by the following formula: CS2 Value = IOUT × 2457 × (RSENSE/FS) where: FS is the full-scale voltage drop. RSENSE is the sense resistor value. For example, if IOUT = 4.64 A, RSENSE = 20 mΩ, and FS = 150 mV, then CS2 Value = (4.64 A × 2457) × (20 mΩ/150 mV) CS2 Value = 1520 decimal The CS2 circuit is now trimmed. After the current sense trim is performed, the OCP limits and settings should be configured. VOLTAGE CALIBRATION AND TRIM The voltage sense inputs are optimized for sensing signals at 1 V and cannot sense a signal greater than 1.5 V . In a 12 V system, a 12:1 resistor divider is required to reduce the 12 V signal to below 1.5 V . It is recommended that the output voltage of the power supply be reduced to 1 V for best performance. The resistor divider can introduce errors, which need to be trimmed. The ADP1043A has enough trim range to trim out errors introduced by resistors with 0.5% tolerance or better. The ADCs output a digital word of 2643 decimal (0xA53) when there is exactly 1 V at their inputs.

Rev. A | Page 28 of 72 OUTPUT VOLTAGE SETTING (VS3+, VS3− TRIM) The VS3 input requires a gain trim. Enable the power supply with no-load current. The power supply output voltage is divided down by the VS3 resistor divider to give 1 V at the VS3+ and VS3− input pins. The VS3 trim register (Register 0x3A) is altered until the VS3 value in Register 0x17 reads 2643 decimal (0xA53). This step should be done before any other trim routines. VS1 TRIM The VS1 input requires a gain trim. Enable the power supply with no-load current. The VS1 voltage is divided down by the VS1 resistor divider to give 1 V at the VS1 pin. The VS1 trim register (Register 0x38) is altered until the VS1 value in Register 0x15 reads 2643 decimal (0xA53). VS2 TRIM The VS2 input requires a gain trim. Enable the power supply with no-load current. The VS2 voltage is divided down by the VS2 resistor divider to give 1 V at the VS2 pin. The VS2 trim register (Register 0x39) is altered until the VS2 value in Register 0x16 reads 2643 decimal (0xA53). RTD/OTP TRIM A 100 kΩ NTC thermistor should be used with the ADP1043A. In a PSU trim, the following procedure should be used: 1. Heat the thermistor or PSU to a known temperature that will result in an OTP threshold. 2. Adjust the temperature gain trim register (Register 0x2B) to give the correct temperature reading (Register 0x1A) at this temperature. 3. Adjust the OTP threshold register (Register 0x2F) until the OTP flag is set. This procedure achieves the most accurate OTP , because it takes into account the part-to-part variations of the ADP1043A and the thermistor being used. LAYOUT GUIDELINES This section explains best practices that should be followed to ensure optimal performance of the ADP1043A. In general, all components should be placed as close to the ADP1043A as possible. Several inputs to the ADP1043A are sensitive. Therefore, take extra care when handling and soldering the part. Along with correct cleaning of the IC after soldering, a short curing process (1 hour at 150°C) is recommended. Analog Devices also recom- mends encapsulating the IC in protective resin after this curing to ensure that any impurities cannot contaminate the IC. CS2 + and CS2− The routing of the traces from the sense resistor to the ADP1043A should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. VS3+ and VS3− The routing of the traces from the remote voltage sense point to the ADP1043A should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. VDD Place decoupling capacitors as close to the part as possible. A 100 nF capacitor from VDD to AGND is recommended. SDA and SCL The routing of the traces should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. CS1 Run the traces from the current sense transformer to the ADP1043A in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. Exposed Pad The exposed pad underneath the ADP1043A should be soldered to the PCB ground plane. VCORE Place the 100 nF capacitor as close to the part as possible. RES Place the 49.9 kΩ resistor as close to the part as possible. RTD Route a single trace to the ADP1043A from the thermistor. Place the thermistor close to the hottest part of the power supply. AGND Create an AGND ground plane and make a single point (star) connection to the power supply system ground.

Control of the ADP1043A is carried out via the I2C interface. under the control of a master device. recommended resistor values and the associated I2C addresses. mended that 1% tolerance resistors be used on the ADD pin. address can be used for write commands only. Table 5. Recommended Resistor Values for I2C Addresses I2C interface is reset and waits for another start condition. Figure 33, and Figure 34, and are described in this section.

1. The master initiates a data transfer by establishing a start

data line, SDA, while the serial clock line, SCL, remains high.

1. The peripheral whose address corresponds to the

reads from the slave device.

1. Data is sent over the serial bus in sequences of nine clock
2. If the operation is a write operation, the first data byte after
3. Because data can flow in only one direction, as defined by

address from which data is to be read.

1. When all data bytes have been read or written, stop

stop condition to begin a new operation.

bytes, and the main block contains 8k 8-bit bytes. time by writing 0x01 to Register 0x7B. Figure 35. EEPROM Page Diagram the Analog Devices software GUI also performs this task. point to the page, row, and column of the byte to be accessed. ADP1043A at I2C Address 0x57. Table 6. EEPROM Registers

Rev. A | Page 32 of 72 EEPROM Password Lock The EEPROM password prevents the EEPROM contents from being changed accidentally or purposely by an unwanted source. The password ensures that critical specifications such as OVP and OCP cannot be changed. The EEPROM is always locked. When the EEPROM downloads its contents to the registers, the password is also downloaded. If the user writes the same password to Register 0x5E twice, the EEPROM is unlocked and can be updated. While the EEPROM is unlocked, it is possible to change the password by writing a new value to Register 0x5E. After this value is updated, the EEPROM contains the new password. The factory default password is 0x00. To update the EEPROM password, the user must write to Register 0x7B. Writing 0x00 to this register updates the EEPROM. The user must wait at least 50 ms after this write command before attempting any further communication with the ADP1043A. Note that the EEPROM should not be written to for the first 500 ms after VDD has been applied. EEPROM Password Change To change the EEPROM password, follow these steps: 1. Write the old password to Register 0x5E (password lock register). 2. Write the new password to Register 0x5E (password lock register) for the first time. 3. Write the new password to Register 0x5E (password lock register) for the second time. 4. Write the new password to Register 0x5E (password lock register) for the third time. 5. Write 0x00 to Register 0x7B. 6. Wait 50 ms. 7. To lock the EEPROM, write any value other than the password value into Register 0x5E. Cyclic Redundancy Check (CRC) The ADP1043A performs a check to ensure that the EEPROM contents are correctly downloaded to registers at startup. It compares the total number of 1s downloaded with the total number of 1s that were last written to the EEPROM. If there is a discrepancy, the CRC fault flag is set in Register 0x03, Bit 1. This flag is used to ensure that the correct data is downloaded from the EEPROM to the registers at startup. SOFTWARE GUI A free software GUI is available for programming and configu- ring the ADP1043A. The GUI is designed to be intuitive to power supply designers and dramatically reduces power supply design and development time. The software includes filter design and power supply PWM topology windows. The GUI is also an information center, displaying the status of all readings, monitoring, and flags on the ADP1043A. For more information about the GUI, contact Analog Devices for the latest software and a user guide. Evaluation boards are also available by contacting Analog Devices. To download the latest GUI, click on the About button at the top of the GUI Main screen. Click on the link to check for GUI updates.

Table 7. Register List

Rev. A | Page 34 of 72 Address Name Digital Filter Programming Registers 0x5F Soft start digital filter LF gain setting 0x60 Normal mode digital filter LF gain setting 0x61 Normal mode digital filter zero setting 0x62 Normal mode digital filter pole setting 0x63 Normal mode digital filter HF gain setting 0x64 Light load mode digital filter LF gain setting 0x65 Light load mode digital filter zero setting 0x66 Light load mode digital filter pole setting 0x67 Light load mode digital filter HF gain setting Adaptive Dead Time Registers 0x68 Dead time threshold 0x69 Dead Time 1 0x6A Dead Time 2 0x6B Dead Time 3 0x6C Dead Time 4 0x6D Dead Time 5 0x6E Dead Time 6 0x6F Dead Time 7 EEPROM Registers 0x7B EEPROM restore factory default register settings 0x7C EEPROM X address 0x7D EEPROM Y address 0x7E EEPROM register

fault register be read again after the faults disappear to ensure that the register is reset. Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation) stays high until the power supply is restarted. O C P, U V P, local O V P, o r load O V P. SR1 and SR2 are disabled by the user. The load current has fallen below the threshold in Register 0x3B. A flag that was configured to disable the sync rects has been set. 1.2 V threshold on the CS1 pin. Fast OCP is a comparator. Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)

7 Voltage

5 Accurate OrFET

toggle is required to restart the power supply. Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)

4 Constant current R Power supply is operating in constant current mode (constant

Table 11. Register 0x03—Fault Register 4 and Register 0x07—Latched Fault Register 4 (1 = Fault, 0 = Normal Operation) comparator has not tripped for one switching cycle. Table 12. Register 0x08 to Register 0x0D—Fault Configuration Registers Register 0x08 to Register 0x0D allow the user to program the response when each flag is set. Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions 7 Timing R/W This bit specifies when the flag is set. 6 Resolve issue R/W This bit specifies when the part is reenabled after the fault that triggered the flag has been resolved. 0 = reenable after the power supply reenable time set in Register 0x0E[1:0]. 1 = remain disabled; power supply must be restarted to reenable. [5:4] Action R/W These bits specify the action that the part takes in response to the flag. 2 Resolve issue R/W Same as Bit 6. [1:0] Action R/W Same as Bits[5:4].

Table 14. Register 0x0E—Flag Configuration Register

7 VDD OV/VCORE OV

R/W Setting this bit means that the VDD OV and VCORE OV flags are ignored.

6 VDD OV/VCORE OV

download the EEPROM contents again before restarting.

5 VDD OV/VCORE OV

this bit to 0 means that there is a 2 μs debounce before the part shuts down. R/W When an accurate OCP flag is set, there is a delay before the corresponding action is performed. This delay is programmed using these bits. R/W These bits specify the time delay before restarting the power supply after a shutdown. SR1, SR2, and OrFET are reenabled immediately. Table 15. Register 0x0F—Soft Start Blank Fault Flags Register 6 Blank OTP R/W Setting this bit means that the OTP flag is ignored until the end of the soft start ramp time. 5 Blank FLAGIN R/W Setting this bit means that the FLAGIN flag is ignored until the end of the soft start ramp time. 4 Blank local OVP R/W Setting this bit means that the local OVP flag is ignored until the end of the soft start ramp time. 3 Blank load OVP R/W Setting this bit means that the load OVP flag is ignored until the end of the soft start ramp time. 0 Blank CS1 fast OCP R/W Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time.

Table 16. Register 0x10—First Flag ID [3:0] First flag ID R These bits record the flag that was set first. Restarting the power supply resets this register. Reading this register also resets the register. Table 17. Register 0x12—VS1/PWM Value (Input Voltage) the input voltage information, this register must be read using two consecutive read operations. VS1 pin. This reading does not take into account an external turns ratio on the main transformer. Table 18. Register 0x13—CS1 Value (Input Current) resolution, which results in an LSB size of 337 μV. At 0 V input, the value in this register is 0 (0x000). At 1.3 V input, the value in this register is 3856 (0xF10). The nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2968 (0xB98). Table 19. Register 0x14—CS1 × (VS1/PWM) Value (Input Power) the second read return the eight LSBs of the input power information.

Table 20. Register 0x15—VS1 Voltage Value nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Table 21. Register 0x16—VS2 Voltage Value nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Table 22. Register 0x17—VS3 Voltage Value (Output Voltage) value in this register is 2643 (0xA53). Table 23. Register 0x18—CS2 Value (Output Current) Bits[7:6] of Register 0x23 changes this LSB step size. If the nominal voltage range is from 75 mV to 150 mV, the LSB step size is 61.04 μV. At a 30 mV input signal on CS2, the value in this register is 30 mV/61.04 μV = 491 (0x1EB). If the nominal voltage range is from 37.5 mV to 75 mV, the LSB step size is 30.52 μV. At a 30 mV input signal on CS2, the value in this register is 30 mV/30.52 μV = 982 (0x3D6). If the nominal voltage range is from 0 mV to 37.5 mV, the LSB step size is 15.26 μV. At a 30 mV input signal on CS2, the value in this register is 30 mV/15.26 μV = 1966 (0x7AE).

Table 24. Register 0x19—CS2 × VS3 Value (Output Power) section for the formulas needed to convert this digital reading into power information. Table 25. Register 0x1A—RTD Temperature Value is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Table 26. Register 0x1D—Share Bus Value master, this register outputs 0. Table 27. Register 0x1E—Modulation Value modulation from 0% to 100% that is being placed on the modulating edges. Table 28. Register 0x1F—Line Impedance Value [7:0] Line impedance value R This register contains the 8-bit line impedance information. This value is (VS2 − VS3)/CS2.

Table 29. Register 0x21—CS1 Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 30. Register 0x22—CS1 Accurate OCP Limit using OUTAUX, the time is synchronized with the rising edge of OUTAUX. The range is programmable from 0% to 138% of the nominal voltage on the CS1 pin. Setting these bits to 0 gives an OCP limit of 0% of the nominal voltage on the CS1 pin. Setting these bits to 10 gives an OCP limit of 44.5% of the nominal voltage on the CS1 pin. Setting these bits to 31 gives an OCP limit of 138% of the nominal voltage on the CS1 pin. Table 31. Register 0x23—CS2 Gain Trim the CS2 Offset Trim section. These bits set the LSB step size of the CS2 ADC. 5 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. the sense resistor. This is Step 2 in the CS2 Gain Trim section.

Table 32. Register 0x24—CS2 Analog Offset Trim sensing is used. This is Step 2 in the CS2 Offset Trim section. 6 Offset polarity R/W 1 = negative offset is introduced. 0 = positive offset is introduced. for errors in the resistor divider network. This is Step 3 in the CS2 Offset Trim section. Table 33. Register 0x25—CS2 Digital Trim that is read in Register 0x18. This is Step 4 in the CS2 Offset Trim section. Table 34. Register 0x26—CS2 Accurate OCP Limit register, the CS2 accurate OCP flag is set. The maximum setting of this register is 254 (0xFE). Setting this register to 255 (0xFF) is not allowed. Table 35. Register 0x27—CS1 Fast OCP Setting this happens, all PWM outputs are disabled for the remainder of the switching cycle. information, see the Volt-Second Balance section. 4 CS1 fast OCP bypass R/W Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin.

3 Constant current

R/W When this bit is set, constant current mode is enabled 10% below the CS2 accurate OCP limit. 1 = constant current mode enabled. 0 = constant current mode disabled.

2 VS balance leading

by the volt-second balance circuit. of consecutive switching cycles for the comparator before the CS1 fast OCP flag is set.

Table 36. Register 0x28—Volt-Second Balance Gain Setting [7:2] Reserved R/W Reserved.

1. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.

When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance. Table 37. Register 0x29—Share Bus Bandwidth [7:5] Reserved R/W Reserved. 3 Current share select R/W 1 = CS1 reading used for current share. 0 = CS2 reading used for current share. the lowest possible bandwidth, and the value 111 is the highest possible bandwidth. Table 38. Register 0x2A—Share Bus Setting higher the setting, the larger the distance that satisfies the current sharing criteria. Table 39. Register 0x2B—Temperature Gain Trim [7:5] Reserved R/W Set these bits to 000 for normal operation. 4 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced.

Table 40. Register 0x2C—PSON/Soft Start Setting [7:6] PS_ON setting R/W These bits determine which signal is used by the ADP1043A as the PS_ON control. 0 0 The ADP1043A is always on. 0 1 Hardware PSON pin is used to enable or disable the power supply. 1 0 Software PS_ON bit (Bit 5) is used to enable or disable the power supply. 5 PS_ON R/W Software PS_ON bit. [4:3] PS_ON delay R/W These bits set the time from when the PS_ON control signal is set to when the soft start begins. 2 Soft stop enable R/W If the soft stop feature is enabled, a soft stop occurs even if a fault flag causes a shutdown event. consider this factor before enabling the soft stop feature. 1 = soft stop time is the same as the soft start time. 0 = no active discharge time. The ADP1043A shuts down the PWM outputs immediately. supply to reach its nominal value. Table 41. Register 0x2D—Pin Polarity Setting O V P. When PSON is disabled, there is a debounce before PGOOD1 is disabled. 3 PGOOD2 flags R/W 0 = any flag can set the PGOOD2 pin. 1 = any flag that has not been configured to be ignored can set the PGOOD2 pin. 2 FLAGIN polarity R/W This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = on). 1 GATE polarity R/W This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = on). 0 PSON polarity R/W This bit sets the polarity of the PSON input pin: 1 = inverted (low = on).

Table 42. Register 0x2E—Modulation Limit percentage of the switching period. modulation low limit, pulse skipping is enabled. Table 43. Register 0x2F—OTP Threshold

Table 44. Register 0x30—OrFET flag is set. The CS2+ and CS2− input pins are used to control this function. VS1 and VS2 input pins are used to control the OrFET enable function.

1 Fast OrFET

R/W These bits determine the debounce on the fast OrFET control before it disables the OrFET. control, the response to the accurate OrFET disable flag should be set to ignore. Table 45. Register 0x31—VS3 Voltage Setting (Remote Voltage) [7:0] VS3 voltage setting R/W This register is used to set the output voltage (voltage differential at the VS3+ and VS3− pins). Programmable from 0% to 155% of nominal voltage. Each LSB corresponds to a 0.6% increase. voltage. This is the default value and is stored in this register when shipped from the factory. into the state machine, the user must set the GO bit (Register 0x5D[0]). Table 46. Register 0x32—VS1 Overvoltage Limit (OVP) Setting these bits to 0 gives an OVP limit of 107.7% of the nominal VS1 voltage. Setting these bits to 10 gives an OVP limit of 120% of the nominal VS1 voltage. Setting these bits to 20 gives an OVP limit of 132% of the nominal VS1 voltage. Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS1 voltage.

voltage must be greater than the OVP threshold for both cycles. Table 47. Register 0x33—VS2 and VS3 Overvoltage Limit (OVP) Setting these bits to 0 gives an OVP limit of 107.7% of the nominal VS2/VS3 voltage. Setting these bits to 10 gives an OVP limit of 120% of the nominal VS2/VS3 voltage. Setting these bits to 20 gives an OVP limit of 132% of the nominal VS2/VS3 voltage. Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS2/VS3 voltage. voltage must be greater than the OVP threshold for both cycles. Table 48. Register 0x34—VS1 Undervoltage Limit (UVP)

7 End of cycle

1: All other PWM outputs are shut down at the end of the switching cycle. 0: All other PWM outputs are immediately shut down. Setting these bits to 0 gives a UVP limit of 0% of the nominal VS1 voltage. Setting these bits to 66 (0x42) gives a UVP limit of 80% of the nominal VS1 voltage. Setting these bits to 82 (0x52) gives a UVP limit of 100% of the nominal VS1 voltage. Setting these bits to 127 (0x7F) gives a UVP limit of 155% of the nominal VS1 voltage.

Table 49. Register 0x35—Line Impedance Limit this value, the line impedance flag is set (Register 0x02, Bit 2). Table 50. Register 0x36—Load Line Impedance [7:4] Reserved R/W Reserved. 3 Enable R/W Set this bit to enable the load line. [2:0] Load line R/W This value specifies how much the output voltage decreases from nominal at full load. Table 51. Register 0x38—VS1 Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. register is trimmed until the VS1 voltage value register (Register 0x15) reads 2643 (0xA53). Table 52. Register 0x39—VS2 Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. register is trimmed until the VS2 voltage value register (Register 0x16) reads 2643 (0xA53). Table 53. Register 0x3A—VS3 Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. this register is trimmed until the VS3 voltage value register (Register 0x17) reads 2643 (0xA53). The VS3 trim must be performed before the load OVP and load UVP trims are performed.

Table 54. Register 0x3B—Light Load Mode Disable Setting normal mode filter registers are used. This value is programmable from 0 mV to 46 mV of the CS2 ADC. the CS2 pins, as well as the percentage of load current for the different nominal CS2 settings. Table 55. Register 0x3C—Silicon Revision ID manufacturer for test purposes and should not be read from in normal operation. Table 56. Register 0x3D—Manufacturer ID (Power-On Default: 0x41) represent the Analog Devices ID code. Table 57. Register 0x3E—Device ID (Power-On Default: 0x43)

Table 59. Register 0x40—PWM Switching Frequency Setting [7:6] Reserved R/W Reserved. [5:0] Switching frequency R/W This register sets the switching frequency of all the PWM pins other than the OUTAUX pin.

Rev. A | Page 52 of 72 Bits Name R/W Description [5:0] Switching frequency R/W Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz) 0 0 1 0 1 0 71.0 0 0 1 0 1 1 74.4 0 0 1 1 0 0 78.1 0 0 1 1 0 1 82.2 0 0 1 1 1 0 86.8 0 0 1 1 1 1 91.9 0 1 0 0 0 0 97.6 0 1 0 0 0 1 100.8 0 1 0 0 1 0 104.1 0 1 0 0 1 1 107.7 0 1 0 1 0 0 111.6 0 1 0 1 0 1 115.7 0 1 0 1 1 0 120.2 0 1 0 1 1 1 125.0 0 1 1 0 0 0 130.2 0 1 1 0 0 1 135.8 0 1 1 0 1 0 142.0 0 1 1 0 1 1 148.8 0 1 1 1 0 0 156.2 0 1 1 1 0 1 164.5 0 1 1 1 1 0 173.6 0 1 1 1 1 1 183.8 1 0 0 0 0 0 195.3 1 0 0 0 0 1 201.6 1 0 0 0 1 0 208.3 1 0 0 0 1 1 215.5 1 0 0 1 0 0 223.2 1 0 0 1 0 1 231.5 1 0 0 1 1 0 240.4 1 0 0 1 1 1 250 1 0 1 0 0 0 260 1 0 1 0 0 1 271 1 0 1 0 1 0 284 1 0 1 0 1 1 297 1 0 1 1 0 0 312 1 0 1 1 0 1 328 1 0 1 1 1 0 347 1 0 1 1 1 1 367 1 1 0 0 0 0 390 1 1 0 0 0 1 416 1 1 0 0 1 0 446 1 1 0 0 1 1 480 1 1 0 1 0 0 521 1 1 0 1 0 1 568 1 1 0 1 1 0 625 1 1 1 1 1 1 Resonant mode

Table 60. Register 0x41—OUTA Rising Edge Timing (OUTA Pin) corresponds to 5 ns resolution. Table 61. Register 0x42—OUTA Rising Edge Setting (OUTA Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t1 edge. 0 = no PWM modulation of the t1 edge. 2 t1 sign R/W 1 = negative sign. Increase of PWM modulation moves t1 right. 0 = positive sign. Increase of PWM modulation moves t1 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 62. Register 0x43—OUTA Falling Edge Timing (OUTA Pin) corresponds to 5 ns resolution. Table 63. Register 0x44—OUTA Falling Edge Setting (OUTA Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t2 edge. 0 = no PWM modulation of the t2 edge. 2 t2 sign R/W 1 = negative sign. Increase of PWM modulation moves t2 right. 0 = positive sign. Increase of PWM modulation moves t2 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 64. Register 0x45—OUTB Rising Edge Timing (OUTB Pin) corresponds to 5 ns resolution. Table 65. Register 0x46—OUTB Rising Edge Setting (OUTB Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t3 edge. 0 = no PWM modulation of the t3 edge. 2 t3 sign R/W 1 = negative sign. Increase of PWM modulation moves t3 right. 0 = positive sign. Increase of PWM modulation moves t3 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation.

Table 66. Register 0x47—OUTB Falling Edge Timing (OUTB Pin) corresponds to 5 ns resolution. Table 67. Register 0x48—OUTB Falling Edge Setting (OUTB Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t4 edge. 0 = no PWM modulation of the t4 edge. 2 t4 sign R/W 1 = negative sign. Increase of PWM modulation moves t4 right. 0 = positive sign. Increase of PWM modulation moves t4 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 68. Register 0x49—OUTC Rising Edge Timing (OUTC Pin) corresponds to 5 ns resolution. Table 69. Register 0x4A—OUTC Rising Edge Setting (OUTC Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t5 edge. 0 = no PWM modulation of the t5 edge. 2 t5 sign R/W 1 = negative sign. Increase of PWM modulation moves t5 right. 0 = positive sign. Increase of PWM modulation moves t5 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 70. Register 0x4B—OUTC Falling Edge Timing (OUTC Pin) corresponds to 5 ns resolution. Table 71. Register 0x4C—OUTC Falling Edge Setting (OUTC Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t6 edge. 0 = no PWM modulation of the t6 edge. 2 t6 sign R/W 1 = negative sign. Increase of PWM modulation moves t6 right. 0 = positive sign. Increase of PWM modulation moves t6 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation.

Table 72. Register 0x4D—OUTD Rising Edge Timing (OUTD Pin) Table 73. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t7 edge. 0 = no PWM modulation of the t7 edge. 2 t7 sign R/W 1 = negative sign. Increase of PWM modulation moves t7 right. 0 = positive sign. Increase of PWM modulation moves t7 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 74. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin) corresponds to 5 ns resolution. Table 75. Register 0x50—OUTD Falling Edge Setting (OUTD Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t8 edge. 0 = no PWM modulation of the t8 edge. 2 t8 sign R/W 1 = negative sign. Increase of PWM modulation moves t8 right. 0 = positive sign. Increase of PWM modulation moves t8 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 76. Register 0x51—SR1 Rising Edge Timing (SR1 Pin) corresponds to 5 ns resolution. Table 77. Register 0x52—SR1 Rising Edge Setting (SR1 Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t9 edge. 0 = no PWM modulation of the t9 edge. 2 t9 sign R/W 1 = negative sign. Increase of PWM modulation moves t9 right. 0 = positive sign. Increase of PWM modulation moves t9 left.

1 VS balance with SR1

bit is set, the volt-second balance modulation is applied to the rising edge of SR1 and SR2. 0 Reserved R/W Reserved. This bit should be set to 0 for normal operation.

Table 78. Register 0x53—SR1 Falling Edge Timing (SR1 Pin) corresponds to 5 ns resolution. Table 79. Register 0x54—SR1 Falling Edge Setting (SR1 Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t10 edge. 0 = no PWM modulation of the t10 edge. 2 t10 sign R/W 1 = negative sign. Increase of PWM modulation moves t10 right. 0 = positive sign. Increase of PWM modulation moves t10 left. 1 SR soft start setting R/W 1 = SR signals perform a soft start every time that they are enabled. 0 = SR signals perform a soft start only the first time that they are enabled. 0 SR soft start enable R/W Setting this bit enables the soft start function for the SR signals. Table 80. Register 0x55—SR2 Rising Edge Timing (SR2 Pin) corresponds to 5 ns resolution. Table 81. Register 0x56—SR2 Rising Edge Setting (SR2 Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t11 edge. 0 = no PWM modulation of the t11 edge. 2 t11 sign R/W 1 = negative sign. Increase of PWM modulation moves t11 right. 0 = positive sign. Increase of PWM modulation moves t11 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation. Table 82. Register 0x57—SR2 Falling Edge Timing (SR2 Pin) corresponds to 5 ns resolution. Table 83. Register 0x58—SR2 Falling Edge Setting (SR2 Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t12 edge. 0 = no PWM modulation of the t12 edge. 2 t12 sign R/W 1 = negative sign. Increase of PWM modulation moves t12 right. 0 = positive sign. Increase of PWM modulation moves t12 left. [1:0] Reserved R/W Reserved. These bits should be set to 00 for normal operation.

Table 84. Register 0x59—OUTAUX Rising Edge Timing (OUTAUX Pin) Table 85. Register 0x5A—OUTAUX Rising Edge Setting (OUTAUX Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t13 edge. 0 = no PWM modulation of the t13 edge. 2 t13 sign R/W 1 = negative sign. Increase of PWM modulation moves t13 right. 0 = positive sign. Increase of PWM modulation moves t13 left. [1:0] Reserved R/W Reserved. Set these bits to 00 for normal operation. Table 86. Register 0x5B—OUTAUX Falling Edge Timing (OUTAUX Pin) Table 87. Register 0x5C—OUTAUX Falling Edge Setting (OUTAUX Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t14 edge. 0 = no PWM modulation of the t14 edge. 2 t14 sign R/W 1 = negative sign. Increase of PWM modulation moves t14 right. 0 = positive sign. Increase of PWM modulation moves t14 left.

1 Regulate with

signal is synchronized with OUTAUX. 0 Reserved R/W Reserved. Set this bit to 0 for normal operation. Table 88. Register 0x5D—OUTx and SRx Pin Disable Setting 7 OUTAUX disable R/W Setting this bit disables the OUTAUX output. 6 SR2 disable R/W Setting this bit disables the SR2 output. 5 SR1 disable R/W Setting this bit disables the SR1 output. 4 OUTD disable R/W Setting this bit disables the OUTD output. 3 OUTC disable R/W Setting this bit disables the OUTC output. 2 OUTB disable R/W Setting this bit disables the OUTB output. 1 OUTA disable R/W Setting this bit disables the OUTA output. timing from being temporarily incorrect, if changing PWM timing while the power supply is on. This bit also latches in any changes made to Register 0x31 (VS3 voltage setting).

Table 89. Register 0x5E—Password Lock EEPROM again, the user must write any value other than the password value into this register. Figure 37. Digital Filter Programmability Table 90. Register 0x5F—Soft Start Digital Filter LF Gain Setting [7:2] Reserved R/W Reserved. [1:0] Soft start filter gain R/W These bits set the gain of the low-pass digital filter that is used during soft start. Table 91. Register 0x60—Normal Mode Digital Filter LF Gain Setting 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37. Table 92. Register 0x61—Normal Mode Digital Filter Zero Setting [7:0] Zero setting R/W This register determines the position of the final 0. See Figure 37. Table 93. Register 0x62—Normal Mode Digital Filter Pole Setting [7:0] Pole location R/W This register determines the position of the final pole. See Figure 37.

Table 94. Register 0x63—Normal Mode Digital Filter HF Gain Setting 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37. Table 95. Register 0x64—Light Load Mode Digital Filter LF Gain Setting 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37. Table 96. Register 0x65—Light Load Mode Digital Filter Zero Setting [7:0] Zero setting R/W This register determines the position of the final 0. See Figure 37. Table 97. Register 0x66—Light Load Mode Digital Filter Pole Setting [7:0] Pole location R/W This register determines the position of the final pole. See Figure 37. Table 98. Register 0x67—Light Load Mode Digital Filter HF Gain Setting 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37.

Table 99. Register 0x68—Dead Time Threshold [7:3] Reserved R/W Reserved. Register 0x69 to Register 0x6F are introduced. Table 100. Register 0x69—Dead Time 1 7 t1 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t1 offset R/W This value determines the t1 offset from the nominal timing. 3 t2 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t2 offset R/W This value determines the t2 offset from the nominal timing.

Table 101. Register 0x6A—Dead Time 2 7 t3 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t3 offset R/W This value determines the t3 offset from the nominal timing. 3 t4 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t4 offset R/W This value determines the t4 offset from the nominal timing. Table 102. Register 0x6B—Dead Time 3 7 t5 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t5 offset R/W This value determines the t5 offset from the nominal timing. 3 t6 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t6 offset R/W This value determines the t6 offset from the nominal timing.

Table 103. Register 0x6C—Dead Time 4 7 t7 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t7 offset R/W This value determines the t7 offset from the nominal timing. 3 t8 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t8 offset R/W This value determines the t8 offset from the nominal timing. Table 104. Register 0x6D—Dead Time 5 7 t9 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t9 offset R/W This value determines the t9 offset from the nominal timing. 3 t10 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t10 offset R/W This value determines the t10 offset from the nominal timing.

Table 105. Register 0x6E—Dead Time 6 7 t11 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t11 offset R/W This value determines the t11 offset from the nominal timing. 3 t12 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t12 offset R/W This value determines the t12 offset from the nominal timing. Table 106. Register 0x6F—Dead Time 7 7 t13 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t13 offset R/W This value determines the t13 offset from the nominal timing. 3 t14 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t14 offset R/W This value determines the t14 offset from the nominal timing.

Table 107. Register 0x7B—EEPROM Restore Factory Default Register Settings 0x00: Upload registers to Page 0 of the main block (user settings). 0x01: Download factory settings (factory block) to the registers. For more information, see the EEPROM section. Table 108. Register 0x7C—EEPROM X Address tion, see the EEPROM section. Table 109. Register 0x7D—EEPROM Y Address [7:6] Reserved R/W Reserved. Table 110. Register 0x7E—EEPROM Register information, see the EEPROM section.

Rev. A | Page 66 of 72 ADJUSTING THE TIMING OF THE PWM OUTPUTS To accurately adjust the timing of the PWM outputs, the follow- ing registers can be used to set the dead time and delays of the PWM outputs: Register 0x41, Register 0x43, Register 0x45, Register 0x47, Register 0x49, Register 0x4B, Register 0x4D, Register 0x4F , Register 0x51, Register 0x53, Register 0x55, and Register 0x57. The resolution for adjusting the dead time is 5 ns. Refer to the Resonant Mode Register Descriptions section for more detailed information. The software GUI for the ADP1043A can be used to set the frequency limit registers, as well as all other settings related to the resonant mode of operation. FREQUENCY LIMIT SETTING The minimum frequency is set by Register 0x42 and by the first four bits of Register 0x44. For example, Register 0x42 is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal). The maximum switching cycle is (160 × 16 + 15) × 5 ns = 12.875 μs The lowest switching frequency limit is 1/12.875 μs = 77.7 kHz The maximum frequency is set by Register 0x46 and by Bits[7:4] of Register 0x48. For example, Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal). The minimum switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs The highest switching frequency limit is 1/1.325 μs = 755 kHz FEEDBACK CONTROL IN RESONANT MODE In contrast to a traditional fixed frequency PWM converter, the output voltage of a resonant converter is regulated by changing the switching frequency. When the ADP1043A is operated in resonant mode, the switching frequency decreases when the sensed voltage is lower than the reference voltage. This makes the ADP1043A capable of controlling a resonant converter in zero-voltage switching (ZVS) mode. Although the switching frequency is variable, the feedback voltage sampling frequency is fixed at 400 kHz. The parameters of the feedback filter are based on this frequency. The method for calculating the filter parameters (gains, zeros, and poles) is the same as that for the fixed frequency PWM mode (see the Digital Filter section). SOFT START IN RESONANT MODE During soft start, the reference voltage of the ADP1043A ramps up. With the feedback loop closed, the switching frequency is reduced from the highest limit to a regulation value. The soft start timing settings and the filter settings are the same as those for the fixed frequency PWM mode (see the Soft Start section). LIGHT LOAD OPERATION (BURST MODE) To control the converter at very light load, the ADP1043A can operate in burst mode. Burst mode can be enabled or disabled using Bits[7:6] of Register 0x4A. When the desired switching frequency is higher than the burst mode threshold, the part enters burst mode. The threshold is determined by the maximum frequency and the burst mode offset setting. The threshold value used to enter burst mode is determined as follows: Threshold value for burst mode = ((Register 0x46 × 16) + Register 0x48[7:4]) + (Register 0x4A[5:0] × 2) The threshold value used to exit burst mode is determined by the entrance value plus 0x10. For example, Register 0x46 is set to 0x10 (16 decimal), Bits[7:4] of Register 0x48 are set to 0, and Bits[5:0] of Register 0x4A are set to 0x8 (8 decimal). The minimum switching cycle is (16 × 16 + 0) × 5 ns = 1.28 μs The highest switching frequency limit is 1/1.28 μs = 781 kHz The threshold to enter burst mode is When the desired switching frequency is higher than 1/1.36 μs = 735 kHz, the PWM outputs are shut down and the part enters burst mode. The threshold to exit burst mode is Therefore, when the desired switching frequency becomes lower than 1/1.44 μs = 694 kHz, the PWM signals are reenabled, and the part exits burst mode. OUTAUX IN RESONANT MODE In resonant mode, the OUTAUX pin cannot be used as a control signal. However, OUTAUX can be used as a fixed frequency PWM signal with a fixed duty cycle. PROTECTIONS IN RESONANT MODE All of the flags and protections that are available in resonant mode behave in the same manner as in fixed frequency PWM mode.

Table 111. Register 0x40—PWM Switching Frequency Setting in Resonant Mode [7:6] Reserved R/W Reserved. enable resonant mode, set these bits to 0x3F (11 1111). Table 112. Register 0x41—OUTA Rising Edge Dead Time in Resonant Mode switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Table 113. Register 0x42—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode) frequency limit is 1/12.875 μs = 77.7 kHz. Table 114. Register 0x43—OUTA Falling Edge Dead Time in Resonant Mode to 0xFF, the falling edge of OUTA is leading tB. Table 115. Register 0x44—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode) [3:0] Reserved R/W Reserved.

Table 116. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Table 117. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) Table 118. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode to 0xFF, the falling edge of OUTB is leading tB. Table 119. Register 0x48—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) [3:0] Reserved R/W Reserved.

Table 120. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode the rising edge of OUTC is leading tB. Table 121. Register 0x4A—Burst Mode Operation in Resonant Mode [7:6] Burst mode enable R/W These bits are used to enable or disable burst mode operation. Operation (Burst Mode) section. Table 122. Register 0x4B—OUTC Falling Edge Dead Time in Resonant Mode switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Table 123. Register 0x4D—OUTD Rising Edge Dead Time in Resonant Mode 0xFF, the rising edge of OUTD is leading tB.

Table 124. Register 0x4F—OUTD Falling Edge Dead Time in Resonant Mode switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Table 125. Register 0x51—SR1 Rising Edge Dead Time in Resonant Mode edge, tD. Each LSB corresponds to 5 ns of resolution. Table 126. Register 0x53—SR1 Falling Edge Dead Time in Resonant Mode falling edge, tE. Each LSB corresponds to 5 ns of resolution. Table 127. Register 0x55—SR2 Rising Edge Dead Time in Resonant Mode edge, tE. Each LSB corresponds to 5 ns of resolution. Table 128. Register 0x57—SR2 Falling Edge Dead Time in Resonant Mode edge, tF. Each LSB corresponds to 5 ns of resolution.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. A | Page 72 of 72 NOTES ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are t he property of their respective owners. D08501-0-5/17(A)