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Three-Channel, Isolated Micropower Management Unit with Seven Digital Isolators Data Sheet ADP1031 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Wide input supply voltage range: 4.5 V to 60 V Integrated flyback power switch Generates isolated, independent bipolar outputs and factory programmable buck output VOUT1: 21 V, 24 V or 6 V to 28 V VOUT2: 5.15 V, 5.0 V, or 3.3 V VOUT3: −24 V to −5 V Uses a 1:1 ratio transformer for simplified transformer design Peak current limiting and OVP for flyback, buck, and inverting regulators Precision enable input and power-good output Adjustable switching frequency via SYNC input Internal compensation and soft start control per regulator High speed, low propagation delay, SPI signal isolation channels Three, 100 kbps general-purpose isolated data channels 9 mm × 7 mm LFCSP form factor enables small overall solution size −40°C to +125°C operating junction temperature range Conforms to CISPR11 Class B radiated emission limits Safety and regulatory approvals (pending) UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A

300 V rms basic insulation between slave, master, and

field power domains (IEC 61010-1, pending) VDE certificate of conformity DIN V VDE 0884-10 (VDE 0884-10):2006-12 V IORM = 565 VPEAK

APPLICATIONS

Industrial automation and process control Instrumentation and data acquisition systems Data and power isolation GENERAL DESCRIPTION The ADP1031 is a high performance, isolated micropower management unit (PMU) that combines an isolated flyback dc-to-dc regulator, an inverting dc-to-dc regulator, and a buck dc-to-dc regulator, providing three isolated power rails. Additionally, the ADP1031 contains four, high speed, serial peripheral interface (SPI) isolation channels and three general- purpose isolators for channel to channel applications where low power dissipation and small solution size is required. TYPICAL APPLICATION CIRCUIT VOUT1 6V TO 28V VOUT2 3.3V, 5V, 5.15V VOUT3 –24V TO –5V MVDD 2.3V TO 5.5V SVDD 1.8V TO 5.5V ISOLATED GPIO CHANNELS AND SPI INTERFACE ISOLATED GPIO CHANNELS AND SPI INTERFACE Tx1 VINP 4.5V TO 60V PGNDP SW2 FB1 VOUT1 VOUT2 SYNC SW3 FB3 PGNDP VINP SLEW SWP VOUT3 CIN CFLYBK CBUCK CINV GNDP MGND SGND1 MVDD SGND2 SVDD1 EN SVDD2 RFT1 RFB1 RFB3 RFT3 SGND2 ADP1031 1:1 PWRGD 16434-101 F igure 1. Operating over an input voltage range of +4.5 V to +60 V, t h e ADP1031 generates isolated output voltages of +6 V to +28 V (adjustable version) or+ 21 V and +24 V (fixed versions) for VOUT1, factory programmable voltages of +5.15 V, +5.0 V , or +3.3 V for VOUT2, and an adjustable output voltages of −24 V to −5 V for VOUT3. By default, the ADP1031 flyback regulator operates at a 250 kHz switching frequency and the buck and inverting regulators operate at 125 kHz. All three regulators are phase shifted relative to each other to reduce electromagnetic interference (EMI). The ADP1031 can be driven by an external oscillator in the range of 350 kHz to 750 kHz to ease noise filtering in sensitive applications. The digital isolators integrated in the ADP1031 use Analog Devices, Inc., iCoupler® chip scale transformer technology, optimized for low power and low radiated emissions. The ADP1031 is available in a 9 mm × 7 mm, 41-lead LFCSP and is rated for a −40°C to +125°C operating junction temperature range. COMPANION PRODUCTS Analog Output DAC: AD5758 Precision Data Acquisition Subsystem: AD7768-1 Additional companion products on the ADP1031 product page

Rev. A | Page 2 of 38 TABLE OF CONTENTS DIN V VDE 0884-10 (VDE V 0884-10) Insulation

REVISION HISTORY

12/2019—Rev. 0 to Rev. A Added Surface Tracking Section, Insulation Wear Out Section, Equation 1 and Equation 2; Renumbered Sequentially, Calculation and Use of Parameters Example Section, and Figure 75; 1/2019—Revision 0: Initial Version

Rev. A | Page 3 of 38 SPECIFICATIONS VINP voltage (VINP) = 24 V , MVDD voltage (VMVDD) = 3.3 V , SVDDx voltage (VSVDDx) = 3.3 V , VOUT1 voltage (VOUT1) = 24 V, VOUT2 voltage (VOUT2) = 5.15 V, VOUT3 voltage (VOUT3) = −15 V , and TA = 25°C for typical specifications. Minimum and maximum specification unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE RANGE VINP VINP 4.5 60 V MVDD VMVDD 2.3 5.5 V SVDDx VSVDDx 1.8 5.5 V Applies to SVDD1 and SVDD2 OUTPUT POWER AND EFFICIENCY Transformer = 750316743 Total Output Power 1720 mW VOUT1 current (IOUT1) = 70 mA, VOUT2 current (IOUT2) = 7 mA, VOUT3 current (IOUT3) = −0.3 mA 520 mW IOUT1 = 20 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA Efficiency 88.8 % IOUT1 = 70 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA 84.8 % IOUT1 = 20 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA Power Dissipation 216.5 mW IOUT1 = 70 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA 93.1 mW IOUT1 = 20 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA QUIESCENT CURRENT VINP Operating Current IQ_VINP 1.77 mA Normal operation, VOUT1, VOUT2, VOUT3 = no load Shutdown Current ISHDN_VINP 125 175 µA EN voltage (VEN) = 0 V MVDD SPI Active Mode IQ_MVDD (SPI_ACTIVE) 4.1 6.5 mA VIx1 = logic low, MSS = logic low 9.2 14 mA VIx1 = logic high, MSS = logic low SPI Low Power Mode IQ_MVDD (SPI_LOWPWR) 1.6 2.5 mA VIx1 = logic low, MSS = logic high 1.6 2.5 mA VIx1 = logic high, MSS = logic high SVDD1 SPI Active Mode IQ_SVDD1 (SPI_ACTIVE) 1.8 2.7 mA VIx1 = logic low, SSS = logic low 5.7 8.6 mA VIx1 = logic high, SSS = logic low SPI Low Power Mode IQ_SVDD1 (SPI_LOWPWR) 1.8 2.7 mA VIx1 = logic low, SSS = logic high 1.8 2.7 mA VIx1 = logic high, SSS = logic high SVDD2 IQ_SVDD2 39 85 µA VIx1 = logic low 2 2.5 mA VIx1 = logic high UVLO VINP Relative to PGNDP Rising Threshold VUVLO_FLYBACK (RISE) 4.44 4.49 V Falling Threshold VUVLO_FLYBACK (FALL) 4.29 4.34 V Hysteresis 100 mV MVDD Relative to MGND Rising Threshold VUVLO_MVDD (RISE) 2.14 2.28 V Falling Threshold VUVLO_MVDD (FALL) 1.9 2 V Hysteresis 140 mV

Rev. A | Page 4 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments THERMAL SHUTDOWN Threshold TSHDN 150 °C Hysteresis THYS 15 °C PRECISION ENABLE Rising Input Threshold VEN_RISING 1.10 1.135 1.20 V Input Hysteresis VEN_HYST 100 mV Leakage Current 0.03 0.5 µA VEN = VINP POWER GOOD Power-Good Threshold Flyback Regulator Lower Limit VPG_FLYBACK_LL 87.5 90 92.5 % Fixed and adjustable output versions Upper Limit VPG_FYLBACK_UL 107.5 110 112.5 % Fixed and adjustable output versions Buck Regulator Lower Limit VPG_BUCK_LL 87.5 90 92.5 % Upper Limit VPG_BUCK_UL 107.5 110 112.5 % Inverting Regulator Lower Limit VPG_INVERTER_LL 87.5 90 92.5 % Upper Limit VPG_INVERTER_UL 107.5 110 112.5 % Glitch Rejection 1.36 µs Glitch of ±15% of the typical output Output Voltage Logic High VPWRGD_OH VMVDD − 0.4 V PWRGD current (IPWRGD) = −1 mA Logic Low VPWRGD_OL 0.4 V IPWRGD = 1 mA SLEW Voltage Level Threshold Slow Slew Rate 0.8 V Normal Slew Rate 2 V Input Current Slow Slew Rate −10 µA Slew voltage (VSLEW) = 0 V to 0.8 V Normal Slew Rate 10 µA VSLEW = 2 V to VINP Fast Slew Rate −1 +1 µA SLEW pin not connected CLOCK SYNCHRONIZATION SYNC Input Input Clock Range fSYNC 350 750 kHz Minimum On Pulse Width tSYNC_MIN_ON 100 ns Minimum Off Pulse Width tSYNC_MIN_OFF 150 ns High Logic VH (SYNC) 1.3 V Low Logic VL (SYNC) 0.4 V Leakage Current −1 0.005 1 µA SYNC voltage (VSYNC) = VSVDDx FLYBACK REGULATOR Output Voltage Range VOUT1 (ADJ) 6 28 V ADP1031ACPZ-1, ADP1031ACPZ-2, and ADP1031ACPZ-3 VOUT1 (FIXED) 24 V ADP1031ACPZ-4 VOUT1 (FIXED) 21 V ADP1031ACPZ-5 Output Voltage Accuracy −1.5 +1.5 % Fixed output options

Rev. A | Page 5 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Feedback Voltage VFB1 0.8 V Feedback Voltage Accuracy −1.5 +1.5 % Adjustable output options Feedback Bias Current IFB1 0.05 µA Load Regulation (ΔVFB1/VFB1)/ΔIOUT1 −0.0005 %/mA IOUT1 = 4 mA to 24 mA, IOUT2 = 10 mA, IOUT3 = −1 mA Line Regulation (ΔVOUT1/VOUT1)/ΔVINP 0.0003 %/V VINP = 16 V to 32 V, IOUT1 = 20 mA, IOUT2 = 10 mA, IOUT3 = −1 mA Power Field Effect Transistor (FET) On Resistance RON (FLYBACK) 3 Ω SWP current (ISWP) = 100 mA Current-Limit Threshold ILIM (FLYBACK) 280 300 320 mA SWP Leakage Current 0.03 0.5 µA SWP voltage (VSWP) = 60 V SWP Capacitance CSWP 50 pF Switching Frequency fSW (FLYBACK) 235 250 265 kHz SYNC = low or high fSYNC/2 kHz SYNC = external clock Minimum On Time 425 ns Minimum Off Time 220 ns Soft Start Timer tSS (FLYBACK) 8 ms Severe Overvoltage Threshold SOVPFLYBACK 29.4 30 30.6 V Flyback regulator stops switching until the overvoltage is removed Severe Overvoltage Hysteresis SOVPFLYBACK_HYST 500 mV BUCK REGULATOR Output Voltage VOUT2 5.15 V ADP1031ACPZ-1, ADP1031ACPZ-4, and ADP1031ACPZ-5

5.0 V ADP1031ACPZ-2

3.3 V ADP1031ACPZ-3

Output Voltage Accuracy −1.5 +1.5 % IOUT2 = 10 mA, applies to all models Load Regulation (ΔVOUT2/VOUT2)/ΔIOUT2 −0.0005 %/mA IOUT2 = 2 mA to 50 mA Line Regulation (ΔVOUT2/VOUT2)/ΔVOUT1 0.0004 %/V VOUT1 = 6 V to 28 V, IOUT2 = 7 mA Power FET On Resistance RON_NFET (BUCK) 1 Ω SW2 current (ISW2) = 100 mA RON_PFET (BUCK) 2.5 Ω ISW2 = 100 mA Current-Limit Threshold ILIM (BUCK) 280 300 320 mA SW2 Leakage Current P Type Metal-Oxide Semiconductor (PMOS) 0.03 0.5 µA VSW2 = 0 V N Type Metal-Oxide Semiconductor (NMOS) 0.03 0.5 µA VSW2 = 28 V Switching Frequency fSW (BUCK) 117.5 125 132.5 kHz SYNC = low or high fSYNC/4 kHz SYNC = external clock Minimum On Time 200 ns Soft Start Timer tSS (BUCK) 8 ms Active Pull-Down Resistor RPD (BUCK) 1.7 kΩ 1.23 V < VOUT1 < 4.5 V INVERTING REGULATOR Output Voltage Range VOUT3 −24 −5 V Feedback Voltage VFB3 0.8 V In reference to VOUT3 Feedback Voltage Accuracy −1.5 +1.5 % Adjustable output option Feedback Bias Current IFB3 0.05 µA Load Regulation (ΔVFB3/VFB3)/ΔIOUT3 −0.01 %/mA IOUT3 = 1 mA to 15 mA Line Regulation (ΔVOUT3/VOUT3)/ΔVOUT1 0.0005 %/V VOUT1 = 6 V to 28 V, IOUT3 = −15 mA Power FET On Resistance RON_NFET (INVERTER) 1.45 Ω SW3 current (ISW3) = 100 mA RON_PFET (INVERTER) 2.2 Ω ISW3 = 100 mA

Rev. A | Page 6 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Current-Limit Threshold ILIM (INVERTER) 280 300 320 mA SW3 Leakage Current PMOS 0.03 0.5 µA VSW3 = −24 V NMOS 0.03 0.5 µA VSW3 = 24 V Switching Frequency fSW (INVERTER) 117.5 125 132.5 kHz SYNC = low or high fSYNC/4 kHz SYNC = external clock Minimum On Time 178 ns Soft Start Timer tSS (INVERTER) 8 ms Active Pull-Down Resistor RPD (INVERTER) 350 Ω 1.23 V < VOUT1 < 4.5 V ISOLATORS, DC SPECIFICATIONS MCK, MSS, MO, SO, MGPI1, MGPI2, SGPI3 Input Threshold Logic High VIH 0.7 × VxVDD V VxVDD = VMVDD or VSVDDx Logic Low VIL 0.3 × VxVDD V VxVDD = VMVDD or VSVDDx Input Current II −1 +1 µA 0 V ≤ VINPUT ≤ VxVDD SCK, SSS, SI, MI Output Voltage Logic High VOH VxVDD − 0.1 V IOx2 = −20 µA, VIx = VIxH3 VxVDD − 0.4 V IOx2 = −2 mA, VIx = VIxH3 Logic Low VOL 0.1 V IOx2 = 20 µA, VIx = VIxL4 0.15 0.4 V IOx2 = 2 mA, VIx = VIxL4 SGPO1, SGPO2, MGPO3 Output Voltage Logic High VOH VxVDD − 0.1 V IOx2 = −20 µA, VIx = VIxH3 VxVDD − 0.4 V IOx2 = −500 µA, VIx = VIxH3 Logic Low VOL 0.1 V IOx2 = 20 µA, VIx = VIxL4 0.15 0.4 V IOx2 = 500 µA, VIx = VIxL4 SCK, SI, MI Tristate Leakage −1 0.01 1 µA MSS = logic high −1 0.01 1 µA VOx5 = VxVDD ISOLATORS, SWITCHING SPECIFICATION MCK, MSS, MO, SO SPI Clock Rate SPIMCK 16.6 MHz Latency 100 125 ns Delay from MSS going low to the first data out is valid Input Pulse Width tPW 17 ns Within PWD limit Input Pulse Width Distortion tPWD 0.25 6.5 ns |tPLH − tPHL| Channel Matching Codirectional tPSKCD 0.5 5.5 ns Opposing Direction tPSKOD 0.5 4 ns

1 VIx is the Channel x logic input, where Channel x can be MCK, MO, SO, MGPI1, MGPI2, or MGPI3. 2 IOx is the output current of the pin. 3 VIxH is the input side, logic high. 4 VIxL is the input side, logic low. 5 VOx is the voltage where the output is pulled. rates apply to both rising and falling common-mode voltage edges. Table 2. Safety Certifications

2500 V rms Single Protection CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition,

Rev. A | Page 8 of 38 ELECTROMAGNECTIC COMPATIBILITY Table 3. Regulatory Body Standard Comment SGS-CCSR CISPR11 Class B Tested using the system board with the AD5758 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) Field Power Domain to Master Domain 2.15 mm min Measured from field power pins and pads to master pins and pads, shortest distance through air Field Power Domain to Slave Domain 2.15 mm min Measured from field power pins and pads to slave pins and pads, shortest distance through air Master Domain to Slave Domain 2.15 mm min Measured from master pins and pads to slave pins and pads, shortest distance through air Minimum External Tracking (Creepage) Field Power Domain to Master Domain 2.15 mm min Measured from field power pins and pads to master pins and pads, shortest distance path along body Field Power Domain to Slave Domain 2.15 mm min Measured from field power pins and pads to slave pins and pads, shortest distance path along body Master Domain to Slave Domain 2.15 mm min Measured from master pins and pads to slave pins and pads, shortest distance path along body Minimum Internal Gap (Internal Clearance) 18 µm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303, Part 1 Material Group II Material group (DIN VDE 0110, 1/89, Table 1)

678 VPEAK

Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884 -10

1 Power dissipated on chip must be derated to keep the junction temperature

PCB thermal design is required. case temperature in the application. Table 7. Thermal Resistance 1 9 mm × 7 mm LFCSP with omitted pins for isolation purposes.

2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with 19 thermal vias. See JEDEC JESD-51. 3 Case temperature was measured at the center of the package. 4 Board temperature was measured near Pin 1. Table 8. Maximum Continuous Working Voltage1 1 See the Insulation Lifetime section for more details. 2 Other pollution degree and material group requirements yield a different limit. 3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.

  1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
  2. EPGNDP IS INTERNALLY CONNECTED TO PGNDP,

AND EPGND2 IS INTERNALLY CONNECTED TO SGND.

25 DNC

26 DNC

27 SGND2

28 PGNDP

29 SWP

30 VINPFPM

32 SLEW

33 GNDP

34 MGND

35 PWRGD

36 MGPI1

37 MGPI2

38 MGPO3

39 MVDD

40 MCK

41 MOSI

Figure 3. Pin Configuration Table 9. Pin Function Descriptions 1 MI Master Output SPI Data Output from the Slave MI and SO Line. This pin is paired with SO. On the slave domain, SO drives this pin. 2 MSS Master Input SPI Slave Select Input from the Master Controller. This pin is paired with SSS. On the slave domain, this pin drives SSS. This signal uses an active low logic. 3 MGND Master Return Master Domain Signal Ground Connection. 4 SGND2 Slave Return Slave Domain Ground Connection. This pin can be left unconnected. 5 SGND1 Slave Return Slave Domain SPI Isolator Ground. domain, MSS drives this pin. MI. On the master domain, this pin drives MI. MO. On the master domain, MO drives this pin. master domain, MCK drives this pin. 11 FB3 Slave Not applicable Inverting Regulator Feedback Pin. 12 VOUT3 Slave Power Inverting Regulator Output and Overvoltage Sense. 13 SW3 Slave Not applicable Inverting Regulator Switch Node. leave this pin floating. Connect a 100 kΩ pull-down resistor to SGND2. 15 VOUT2 Slave Power Buck Regulator Output Feedback. 17 SW2 Slave Not applicable Buck Regulator Switch Node. the buck and inverting regulators. 19 FB1 Slave Feedback Node for the Flyback Regulator.

Rev. A | Page 12 of 38 Pin No. Mnemonic Isolation Domain Direction Description 21 SGPI3 Slave Input General-Purpose Input 3. This pin is paired with MGPO3. 22 SGPO2 Slave Output General-Purpose Output 2. This pin is paired with MGPI2. 23 SGPO1 Slave Output General-Purpose Output 1. This pin is paired with MGPI1. 24 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. 25 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. 26 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. 27 SGND2 Slave Return Slave Domain Ground Connection. This pin can be left unconnected. 28 PGNDP Field power Return Ground Return for Flyback Regulator Power Supply. 29 SWP Field power Not applicable Flyback Regulator Switching Node. Primary side transformer connection. 30 VINP Field power Power Flyback Regulator Supply Voltage. Connect a minimum of 3.3 µF capacitor from VINP to PGNDP . 31 EN Field power Input Precision Enable. Compare the EN pin to an internal precision reference to enable the flyback regulator output. 32 SLEW Field power Input Flyback Regulator Slew Rate Control. The SLEW pin sets the slew rate for the SWP driver. For the fastest slew rate (best efficiency), leave the SLEW pin open. For the normal slew rate, connect the SLEW pin to VINP . For the slowest slew rate (best EMI performance), connect the SLEW pin to GNDP . 33 GNDP Field power Return Field Power Signal Ground Connection. 34 MGND Master Return Master Domain Power Ground Connection. 35 PWRGD Master Return Power Good. This pin indicates when the secondary side supplies are within their programmed range. 36 MGPI1 Master Input General-Purpose Input 1. This pin is paired with SGPO1. 37 MGPI2 Master Input General-Purpose Input 2. This pin is paired with SGPO2. 38 MGPO3 Master Output General-Purpose Output 3. This pin is paired with SGPI3. 39 MVDD Master Power Master Domain Power. Connect a 100 nF decoupling capacitor from MVDD to MGND. 40 MCK Master Input SPI Clock Input from the Master Controller. Paired with SCK. On the slave domain, this pin drives SCK. 41 MO Master Input SPI Data Input Going to Slave MO and SI Line. Paired with SI. On the slave domain, this pin drives SI. EPGNDP Field power Return PGNDP Exposed Pad. This pad is internally connected to PGNDP . EPGNDM Master Return MGND Exposed Pad. This pad is internally connected to MGND. EPGND2 Slave Return SGND Exposed Pad. This pad is internally connected to SGND.

Figure 10. Overall Efficiency using Various Transformers, TA = +25°C, Figure 11. Overall Efficiency using Various Transformers, TA = +125°C,

0 PWRGD

Figure 12. Power-Up Sequence at VINP Rising, TA = +25°C, VINP = +24 V, Figure 13. Power Dissipation using Various Transformers, TA = +25°C, Figure 14. Power Dissipation using Various Transformers, TA = +125°C, Figure 15. Power-Up Sequence at EN Rising, TA = +25°C, VINP = +24 V,

and a buck regulator, providing three isolated power rails.

  1. CFLYBK IS THE FLYBACK REGULATOR OUTPUT CAPACITOR VALUE.
  2. CBUCK IS THE BUCK REGULATOR OUTPUT CAPACITOR VALUE.
  3. CINV IS THE INVERTING REGULATOR OUTPUT CAPACITOR VALUE.

Figure 64. Simplified Block Diagram

transformer is transferred to the load. reliability without the issue of CTR degradation.

  • A smaller transformer solution size due to a lower number of turns required on the core and a fewer number of pins.
  • Each output can be independently set—the multitap approach requires a custom multitap transformer for different output voltage combinations.
  • Outputs are more accurate because the outputs do not rely on the discrete ratios between the transformer windings.
  • Output accuracy is unaffected by load changes on each rail. Power Saving Mode (PSM) During light load operation, the regulators can skip pulses to maintain output voltage regulation. Therefore, no minimum load is required. Skipping pulses increases the device efficiency but results in larger output ripple. Flyback Undervoltage Lockout (UVLO) The UVLO circuitry monitors the VINP pin voltage level. If the input voltage drops below the VUVLO_FLYBACK (FALL) threshold, the flyback regulator turns off. After the VINP pin voltage rises above the VUVLO_FLYBACK (RISE) threshold, the soft start period initiates, and the flyback regulator enables. Flyback Regulator Precision Enable Control The flyback regulator in the ADP1031 features a precision enable circuit with an accurate reference voltage. If the voltage at the EN pin rises above the VEN_RISING threshold, the flyback regulator soft start period initiates, and the regulator enables. If the EN pin voltage falls below the VEN_RISING − VEN_HYST threshold, the flyback regulator turns off. Flyback Regulator Soft Start The flyback regulator includes a soft start function that limits the inrush current from the supply and ramps up the output voltage in a controlled manner. The flyback regulator soft start period initiates when the voltage at the EN pin rises above the VEN_RISING threshold. Flyback Slew Rate Control The flyback regulator employs programmable output driver slew rate control circuitry. This circuitry adjusts the slew rate of the switching node as shown in Figure 65, where lower EMI and reduced ringing can be achieved at slightly lower efficiency operation and vice versa. To program the slew rate, connect the SLEW pin to the VINP pin for normal mode, to the GNDP pin for slow mode, or leave it open for fast mode. Note that slew rate control causes a trade-off between efficiency and low EMI. FASTEST SLOWEST 16434-051

Figure 65. Switching Node at Various Slew Rate Settings Table 10. Slew Rate Settings

Rev. A | Page 25 of 38 Flyback Regulator Overcurrent Protection The flyback regulator features a current-limit function that senses the forward current in the switching metal-oxide semiconductor field effect transistor (MOSFET) on a cycle by cycle basis. If the current exceeds the ILIM (FLYBACK) threshold, the switch turns off. Flyback Regulator Overvoltage Protection The flyback regulator of the ADP1031 implements a number of OVP methods to detect and prevent an overvoltage condition on the flyback regulator output, such as the following:

  • If the voltage on the FB1 pin exceeds VFB1 by 10% for the adjustable output version, or the VOUT1 pin exceeds the factory programmed VOUT1 by 10% for the fixed output version, an OVP fault will be detected, which prevents the flyback regulator switch from turning on. The flyback regulator primary switch stays off until the OVP condition is no longer present.
  • If communication across the isolation barrier from the secondary controller to the primary controller fails, the flyback regulator shuts down and a new soft start power-up cycle initiates.
  • If the voltage on the output of the flyback regulator exceeds the severe overvoltage threshold (SOVP FLYBACK), the primary controller does not turn on the primary side switch. The flyback regulator primary switch stays off until the voltage on the VOUT1 pin falls below the SOVPFLYBACK − SOVPFLYBACK_HYST threshold. BUCK REGULATOR Buck Regulator Operation The step-down, dc-to-dc (or buck) regulator in the ADP1031 uses a current mode controlled scheme, operating at a fixed frequency set by an internal oscillator. Current mode uses a fast inner current-controlled loop to regulate peak inductor current and a slower outer loop to adjust the current loop to regulate the output voltage. At the start of each oscillator cycle, the high- side MOSFET switch turns on, applying the input voltage to one end of the inductor, which normally causes the buck regulator inductor current (I L_BUCK) to increase until the current sense signal crosses the peak inductor current threshold that turns off the MOSFET switch. The error amplifier output sets this threshold. During the high-side MOSFET off time, the inductor current declines through the low-side MOSFET switch until either the next oscillator clock pulse starts a new cycle that results in continuous conduction mode (CCM) operation, or the inductor current reaches zero, the low-side MOSFET switch is turned off, and the control system waits for the next oscillator clock pulse to start a new cycle, resulting in discontinuous mode (DCM) operation. Under light load conditions, the regulator can skip pulses to maintain regulation and increase power conversion efficiency. Buck Regulator UVLO The step-down regulator of theADP1031 features an internal undervoltage lockout circuit that monitors the input voltage to the regulator or VOUT1. If the voltage at VOUT1 drops below the internal threshold level of 4.5 V, the regulator turns off. If the output at VOUT1 rises above the internal threshold, the regulator soft start period initiates, and the regulator enables. Buck Regulator Soft Start The step-down regulator in the ADP1031 includes soft start circuitry that ramps the output voltage in a controlled manner during start-up, thereby limiting the inrush current. Buck Regulator Current-Limit Protection The step-down regulator in the ADP1031 includes a current- limit protection circuit to limit the amount of forward current through the high-side MOSFET switch. The inductor peak current is monitored cycle by cycle to detect an overload condition. When the overload condition occurs, the current- limit protection limits the peak inductor current to ILIM (BUCK), resulting in a drop in the output voltage. Buck Regulator OVP The step-down regulator of the ADP1031 features an OVP circuit that monitors the output voltage. If the voltage on the VOUT2 pin exceeds the nominal output voltage by 10%, the step-down, dc-to-dc regulator stops switching until the voltage falls below the threshold again. Buck Regulator Active Pull-Down Resistor The buck regulator has an active pull-down resistor that discharges the output capacitor when the output of VOUT1 is between 1.23 V and 4.5 V. The pull-down resistor connects between VOUT2 and SGND2.

outer loop to adjust the current loop to regulate the output voltage. clock pulse to start a new cycle, resulting in DCM operation. maintain regulation and increase power conversion efficiency. regulator soft start period initiates, and the regulator enables. manner during startup, thereby limiting the inrush current. current is monitored cycle by cycle to detect an overload condition. stops switching until the voltage rises above the threshold again. indicate when the three isolated output voltage rails are valid. supplies are within the respective power-good threshold limits.

  1. The flyback regulator powers up first (see 1 in Figure 66).
  2. When VOUT1 rises above the lower power-good threshold

(VPG_FLYBACK_LL), the buck regulator turns on (see 2 in Figure 66).

  1. When the buck regulator output (VOUT2) rises above the

regulator turns on (see 3 in Figure 66).

  1. PWRGD is driven high when the inverting regulator output

VPG_INVERTER_LL (see 4 in Figure 66).

  1. If any of the three analog supplies move outside the power-

deglitch delay (see 5 in Figure 66). Figure 66. Power-Up Sequencing and PWRGD internally generated frequency or external clock synchronization. Table 11. Sync Pin Functionality

Figure 69. Multichannel SPI Muxing Scheme ADP1031 devices can be connected together. Table 13. SPI MSS Gating pull these pins to the desired logic state when MSS is high. the inputs and sending these inputs back for similar processing. resembles 19.5 µs peak jitter. For proper operation of the GPIO channels, refer to Table 14. voltage range for these pins. Table 14. Truth Table for GPIO Channels

Rev. A | Page 30 of 38 FLYBACK REGULATOR COMPONENTS SELECTION Input Capacitor An input capacitor must be placed between the VINP pin and ground. Ceramic capacitors greater than or equal to 3.3 µF over temperature and voltage are recommended. The input capacitor reduces the input voltage ripple caused by the switching current. Place the input capacitor as close as possible to the VINP and PGNDP pins to reduce input voltage spikes. The voltage rating of the input capacitor must be greater than the maximum input voltage. Output Capacitor Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to the output voltage dc bias. A 4.7 µF capacitor is recommended as a balance between performance and size. Ripple Current vs. Capacitor Value The output capacitor value must be chosen to minimize the output voltage ripple while considering the increase in size and cost of a larger capacitor. Use the following equation to calculate the output capacitance: C OUT = (LPRI × ISWP2)/(2 × VOUT1 × ΔVOUT1) where: COUT is the capacitance of the flyback output capacitor. LPRI is the primary inductance of the transformer. ISWP is the peak switch current. VOUT1 is the flyback regulator output voltage. ΔVOUT1 is the allowable flyback regulator output ripple. Schottky Diode A Schottky diode with low junction capacitance is recommended for D1. At higher output voltages and especially at higher switching frequencies, the junction capacitance is a significant contributor to efficiency. Choose an output diode with a forward current rating (I F) that is greater than the maximum load requirement and with a reverse voltage rating (VR) that is greater than the summation of the maximum supply voltage INP (MAX)) and the maximum output voltage (VOUT1 (MAX)). Transformer The transformer used with the ADP1031 is an important component within the system, in terms of efficiency and maximum output power capability. Analog Devices worked with a number of leading magnetic component suppliers to develop a number of transformer designs for use with the ADP1031. These designs are listed in Table 16. A number of factors must be taken into account when designing a transformer for use with the ADP1031. Turn Ratio The ADP1031 requires the use of a transformer with a primary to secondary turn ratio of 1:1 to start up properly. Primary Inductance The ADP1031 operates with a transformer with an inductance in the 80 µH to 560 µH range. However, it is recommended to choose an inductance value that results in the flyback output voltage (VOUT1) divided by the transformer primary inductance being less than or equal to 140,000 to maintain control loop stability. VOUT1/LPRI ≤ 140,000 where: VOUT1 is the flyback regulator output voltage. LPRI is the primary side inductance of the transformer. Using a transformer at the lower end of the inductance range may result in a smaller transformer but also reduces the output power capabilities due to larger ac ripple current through the transformer. Conversely, operating at higher inductance can result in higher output power at the expense of a potentially larger transformer. Flyback Transformer Saturation Current Do not exceed the saturation current of the transformer in operation or this may lead to much higher losses and overall lower system efficiency. Choose a transformer with a saturation current rating that is greater than the expected peak switch current (I SWP) across line and load conditions. Series Winding Resistance In power loss sensitive applications, keep the series resistance of the primary and secondary windings as low as possible to improve overall efficiency. Leakage Inductance and Clamping Circuits When choosing a transformer to operate with the ADP1031, minimize transformer leakage inductance. Leakage inductance causes a voltage spike to appear on the SWP node when the flyback regulator switch is off due to energy storage in the leakage inductance that is not transferred to the output. The voltage spike is more prominent at higher load currents and increases with higher leakage inductance. It is important to keep the voltage spikes lower than the voltage rating of the flyback switch that drives the SWP pin. Margin must be built in to any design to avoid exceeding this limit if no clamp or snubber circuit is used to protect the flyback switch. To estimate the leading voltage spike at the SWP pin when the switch turns off, use the following equation: VPEAK = IPEAK × (LLEAK/(CP + CSWP))1/2 + VINP + VOUT1 + VD where: VPEAK is the voltage spike amplitude. IPEAK is the peak current on the flyback switch. LLEAK is the leakage inductance of the transformer. CP is the parasitic capacitance of the transformer. CSWP is the capacitance on the flyback switch. VINP is the input supply voltage. VOUT1 is the output voltage of the flyback regulator. VD is the forward voltage drop across the rectifier diode. A snubber or clamp circuit can protect the flyback switch for cases where the leakage inductance is too high for application conditions. Two common types of clamping circuit are the

Rev. A | Page 32 of 38 Diode Zener Diode Clamp A Zener diode can replace the resistor, capacitor (RC) network on the resistor, capacitor, diode clamp when the clamping level must be consistent and well defined. Choose the Zener diode breakdown voltage to balance power loss and switch voltage protection. Calculate the Zener voltage by using the following equation: VZENER (MAX) ≤ SWPVMAX − VINP (MAX) where: VZENER (MAX) is the maximum Zener diode breakdown voltage or the Zener voltage, which can be the same as the clamping voltage, VCLAMP. SWPVMAX is the absolute maximum rating of the SWP pin. VINP (MAX) is the maximum input supply voltage. The power loss in the clamp determines the power requirement for the Zener diode. Use the following equation to calculate the Zener diode power dissipation: PZENER = (VZENER × LLEAK × IPEAK2 × fSW)/(2 × (VZENER − VOUT1)) where: PZENER is the Zener diode power dissipation. Choose a Zener diode with power rating higher than the calculated value. VZENER is the Zener diode breakdown voltage or the Zener voltage. LLEAK is the leakage inductance of the transformer. IPEAK is the peak current on the flyback switch. fSW is the switching frequency of the flyback regulator. VOUT1 is the output voltage of the flyback regulator. Ripple Current (IAC) vs. Inductance Calculate the ripple current by first determining the duty cycle in continuous conduction mode. DCCM = (VOUT1 + VD)/(VOUT1 + VD + VINP) where: DCCM is the duty cycle of the flyback switch. VOUT1 is the output voltage of the flyback regulator. VD is the forward voltage drop across the rectifier diode. VINP is the input supply voltage. Then, from the duty cycle, calculate the IAC in the flyback switch and transformer primary. IAC = (VINP × DCCM)/(fSW × LPRI) where: IAC is the ripple current through the primary side of the transformer and flyback switch. VINP is the input supply voltage. DCCM is the duty cycle of the flyback switch. fSW is the switching frequency of the flyback regulator. LPRI is the primary side inductance of the transformer. Maximum Output Current Calculation The maximum output power and current that can be achieved from the flyback output depends on a number of variables within the regulator. These variables include the transformer choice, the operating frequency, and the rectifier diode choice. The flyback regulator output is the supply to the buck regulator that drives VOUT2 and the inverting regulator that drives VOUT3. Determine the maximum output power capability by PVOUT1 (MAX) = 0.5 × (IPEAK2 − (IPEAK − IAC/2)2) × LPRI × fSW × η where: PVOUT1 (MAX) is the maximum output power from VOUT1. IPEAK is the peak current on the flyback switch. IAC is the ripple current through the primary side of the transformer and flyback switch. LPRI is the primary side inductance of the transformer. fSW is the switching frequency of the flyback regulator. η is the expected efficiency of the flyback regulator. The lower limit of the flyback current-limit threshold, ILIM (FLYBACK), limits the maximum IPEAK. However, it is not recommended to operate at this level to avoid unwanted current-limit events due to variation in transformer inductance, efficiency, flyback switching frequency, and rectifier diode forward voltage drop. If the load on the flyback causes the current limit to trip, the output voltage may not regulate as expected. It is recommended to choose a peak operating current with built in margin for the variations mentioned or to calculate the maximum output power or output load using the worst case transformer inductance, efficiency, diode forward voltage drop, and flyback switching frequency. Calculate the maximum load current on VOUT1 by IVOUT1 (MAX) = PVOUT1 (MAX)/VOUT1 where: IVOUT1 (MAX) is the maximum output current from VOUT1. PVOUT1 (MAX) is the maximum output power from VOUT1. VOUT1 is the output voltage of the flyback regulator.

losses eventually have an increasing negative impact on efficiency. size, but a larger capacitor can be used to reduce output ripple. decrease the overall efficiency due to increased switching losses. stability across VOUT1 and output load. particularly for lower output voltages. Table 16. Transformer Selection 1 Turns ratio between the primary and secondary coils. Table 17. Buck Regulator and Inverting Regulator Recommended Inductors

insulation material cause long-term insulation degradation. for the ADP1031 isolators are shown in Table 4. specified in most standards. varying voltage stress causes insulation wear out.

60 Hz sinusoidal stress because this reflects isolation from line

of 60 Hz ac and dc across the barrier as shown in Equation 1. materials, the ac rms voltage determines the product lifetime. VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. Figure 75. Critical Voltage Example creepage required by a system standard.

Rev. A | Page 35 of 38

60 Hz sine wave, and it is well within the limit for a 20-year

service life. The dc working voltage limit is set by the creepage of the package as specified in IEC 60664-1. This value can differ for specific system level standards. THERMAL ANALYSIS For the purpose of thermal analysis, the ADP1031 die are treated as a thermal unit, with the highest junction temperature reflected in the θ JA values from Table 7. The value of θJA is based on measurements taken with the devices mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADP1031 operates at a full load across the full temperature range without derating the output current. However, following the recommendations in the PCB Layout Considerations section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures. Each switching regulator in the ADP1031 has a thermal shutdown circuit that turns off the dc- to-dc converter and the outputs when a die temperature of approximately 150°C is reached. When the die cools below approximately 135°C, the ADP1031 dc-to-dc converter outputs turn on again.

Figure 76. Typical Application Circuit for the ADP1031 Using the AD5758

0.02 NOM

0.203 REF

Figure 78. 41-Lead Lead Frame Chip Scale Package [LFCSP] 2 For other VOUT1 voltage options, contact Analog Devices local sales representatives for additional information. registered trademarks are t he property of their respective owners.