ADP-I2C-USB-Z

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Technical content

Digital Controller for Isolated Power Supply Applications Data Sheet ADP1046 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.

FEATURES

Integrates all typical PWM controller functions

7 PWM control signals

Integrated programmable loop filters Programmable voltage line feedforward Dedicated soft start filter Programmable dead time for improved efficiency Remote and local voltage sense Primary and secondary side current sense Synchronous rectifier control Current sharing OrFET control I 2C interface Extensive fault detection and protection Extensive programming and telemetry Fast digital calibration User accessible EEPROM

APPLICATIONS

Isolated dc-to-dc power supplies Redundant power supply systems Server, storage, network, and communications infrastructure GENERAL DESCRIPTION The ADP1046 is a flexible, digital secondary side controller designed for ac-to-dc and isolated dc-to-dc secondary side applications. The ADP1046 is pin-compatible with the ADP1043A and offers several enhancements and new features, including voltage feedforward, improved loop response, and programmable dead time control to maximize efficiency. The ADP1046 is optimized for minimal component count, maximum flexibility, and minimum design time. Features include local and remote voltage sense, primary and secondary side current sense, digital pulse-width modulation (PWM) generation, current sharing, and redundant OrFET control. The control loop digital filter and compensation terms are integrated and can be programmed over the I 2C interface. Programmable protection features include overcurrent protection (OCP), over- voltage protection (OVP), undervoltage lockout (UVLO), and overtemperature protection (OTP). The built-in EEPROM provides extensive programming of the integrated loop filter, PWM signal timing, inrush current, and soft start timing and sequencing. Reliability is improved through a built-in checksum and programmable protection circuits. A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features. The industry-standard I 2C bus provides access to the many monitoring and system test functions. The ADP1046 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. TYPICAL APPLICATION CIRCUIT RES RTDADD VCORE FLAGIN PSON PGOOD2 PGOOD1 SDA SCL VDD DGND AGND OUTA OUTB OUTC OUTD OUTAUX CS1 SR1 SR2 ACSNS VS1 GATE VS3+ VS3– SHAREo SHAREi DRIVER iCouplerDRIVER VS2 DRIVER DC INPUT LOAD MICROCONTROLLER CS2– CS2+ PGND VDD 10045-001 ADP1046 Figure 1.

Rev. 0 | Page 2 of 96 TABLE OF CONTENTS PWM and Sync Rect Outputs (OUTA, OUTB, OUTC,

Rev. 0 | Page 3 of 96

REVISION HISTORY

3/12—Revision 0: Initial Version

• Output voltage sense and feedback
• Voltage line feedforward control
• Digital loop filter compensation
• PWM generation
• Current sharing
• Current, voltage, and temperature sense
• OrFET control
• Housekeeping and I2C interface
• Calibration and trimming The main function of controlling the output voltage is performed using the feedback ADCs, the digital loop filter, and the PWM block. The feedback ADCs use a multipath approach (patent pending). The ADP1046 combines a high speed, low resolution (fast and coarse) ADC with a low speed, high resolution (slow and accurate) ADC. Loop compensation is implemented using the digital filter. This proportional, integral, derivative (PID) filter is implemented in the digital domain to allow easy programming of filter char- acteristics, which is of great value in customizing and debugging designs. The PWM block generates up to seven programmable PWM outputs for control of FET drivers and synchronous rectification FET drivers. This programmability allows many traditional and unique switching topologies to be realized. A current share bus interface is provided for paralleling multiple power supplies. The ADP1046 also has hot-swap OrFET sense and control for N + 1 redundant power supplies. Conventional power supply housekeeping features, such as remote and local voltage sense and primary and secondary side current sense, are included. An extensive set of protections is offered, including overvoltage protection (OVP), overcurrent protection (OCP), overtemperature protection (OTP), undervoltage protec- tion (UVP), ground continuity monitoring (voltage continuity), and ac sense. All these features are programmable through the I 2C bus inter- face. This bus interface is also used to calibrate the power supply. Other information that is useful for power monitoring, such as input current, output current, and fault flags, is also available through the I 2C bus interface. The internal EEPROM can store all programmed values and allows standalone control without a microcontroller. A free, downloadable GUI is available and provides all the necessary software to program the ADP1046. To obtain the latest software and a user guide, visit http://www.analog.com/digitalpower. The ADP1046 operates from a single 3.3 V supply and is specified from −40°C to +125°C. FUNCTIONAL BLOCK DIAGRAM RES VS3– VS3+ PGOOD1 VDD GATE PGND ACSNS VS1 OUTA OUTB SR1 SR2 OUTC OUTD CS1 PSON SCL SDA CS2– CS2+ VS2 VCORE AGND OUTAUX PGOOD2 SHAREi FLAGIN DGND RTDADD ADC ADC ADC ADC ADC UVLO PWM ENGINE VREF LDO ADC ADC 8kB EEPROM DIGITAL CORE I2C INTERFACE PWM OSC 1.2V 0.45V V_OVP SHAREo 10045-002 ADP1046

Figure 2. ADP1046 Simplified Block Diagram

Rev. 0 | Page 5 of 96 SPECIFICATIONS VDD = 3.0 V to 3.6 V , TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY Supply Voltage VDD 4.7 μF capacitor connected to AGND 3.0 3.3 3.6 V Supply Current IDD Normal operation (PSON is high or low) 20 mA During EEPROM programming (40 ms) IDD + 8 mA Shutdown (VDD below UVLO) 100 μA POWER-ON RESET Power-On Reset VDD rising 3.0 V UVLO VDD falling 2.75 2.85 2.97 V UVLO Hysteresis 40 mV OVLO 3.8 4.0 4.1 V OVLO Debounce When set to 2 μs 2.0 μs When set to 500 μs 500 μs VCORE PIN 0.33 μF capacitor connected to DGND Output Voltage TA = 25°C 2.4 2.5 2.7 V OSCILLATOR AND PLL PLL Frequency RES = 10 kΩ (±0.1%) 190 200 210 MHz OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2, GATE PINS Output Low Voltage VOL Source current = 10 mA 0.4 V Output High Voltage VOH Source current = 10 mA VDD − 0.4 V Rise Time CLOAD = 50 pF 3.5 ns Fall Time CLOAD = 50 pF 1.5 ns VS1, VS2, VS3 LOW SPEED ADCs Input Voltage Range VIN Differential voltage from VS1, VS2 to PGND, and from VS3+ to VS3− 0 1 1.6 V Usable Input Voltage Range 0 1.4 V ADC Clock Frequency 1.56 MHz Register Update Rate 10 ms Voltage Sense Measurement Accuracy Factory trimmed at 1.0 V 0% to 100% of usable input voltage range −3.0 +3.0 % FSR −48 +48 mV 10% to 90% of usable input voltage range −2.0 +2.0 % FSR −32 +32 mV 900 mV to 1.1 V −1.0 +1.0 % FSR −16 +16 mV Temperature Coefficient 65 ppm/°C Leakage Current 1.0 μA Voltage Sense Measurement Resolution

12 Bits

Common-Mode Voltage Offset −0.25 +0.25 % FSR Voltage Differential from VS3− to PGND −200 +200 mV VS1 Accurate OVP Speed Register 0x32[1:0] = 00; equivalent resolution is 7 bits 80 μs VS1 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS1 −2.0 +2.0 % FSR VS2 and VS3 OVP Speed Register 0x33[1:0] = 00; equivalent resolution is 7 bits 80 μs VS2 and VS3 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS2 and VS3 −2.0 +2.0 % FSR

Rev. 0 | Page 6 of 96 Parameter Symbol Test Conditions/Comments Min Typ Max Unit VS3 HIGH SPEED ADC Equivalent Sampling Frequency fSAMP fSW kHz Equivalent Resolution fSW = 390.6 kHz 6 Bits Dynamic Range ±30 mV VS1 FAST OVP COMPARATOR Threshold Accuracy Factory trimmed at 1.2 V 1 1.25 % Propagation Delay Does not include debounce time (Register 0x0A[7] = 1) 40 ns VS1 UVP DIGITAL COMPARATOR VS1 UVP Accuracy −2.0 +2.0 % FSR Propagation Delay Does not include debounce time (Register 0x0B[3] = 1) 80 ns AC SENSE COMPARATOR PWM and resonant mode Input Voltage Threshold 0.4 0.45 0.5 V Propagation Delay From ACSNS threshold to SRx rising edge (resonant mode only) 160 ns ADC Clock Frequency 1.56 MHz Input Voltage Range VACSNS 0 1 1.6 V Usable Input Voltage Range 0 1.4 V Sampling Frequency for I2C Reporting 100 Hz Sampling Period for Feedforward Equivalent resolution is 11 bits 10 μs Measurement Accuracy Factory trimmed at 1.0 V 0% to 100% of usable input voltage range −5.0 +3.0 % FSR 10% to 90% of usable input voltage range −2.0 +2.0 % FSR 900 mV to 1.1 V −1.0 +1.0 % FSR −16 +16 mV Leakage Current 1.0 μA CURRENT SENSE 1 (CS1 PIN) Input Voltage Range VIN 0 1 1.4 V Usable Input Voltage Range 0 1.3 V ADC Clock Frequency 1.56 MHz Register Update Rate 10 ms Current Sense Measurement Accuracy Factory trimmed at 0.7 V; tested under dc input conditions 10% to 50% of usable input voltage range −3.0 +3.0 % FSR −41.4 +41.4 mV 0% to 100% of usable input voltage range −6.0 +3.0 % FSR −84 +42 mV 40% to 60% of usable input voltage range −1.0 +1.0 % FSR Current Sense Measurement Resolution CS1 Fast OCP Threshold 1.18 1.2 1.21 V CS1 Fast OCP Speed 80 100 ns CS1 Accurate OCP DC Accuracy 10% to 90% of usable input voltage range −2.0 +2.0 % FSR −28 +28 mV CS1 Accurate OCP Speed 2.62 5.24 ms Leakage Current 1.0 μA

Rev. 0 | Page 7 of 96 Parameter Symbol Test Conditions/Comments Min Typ Max Unit CURRENT SENSE 2 (CS2+, CS2− PINS) Input Voltage Range VIN Differential voltage from CS2+ to CS2−, LSB = 29.297 μV 0 120 mV Usable Input Voltage Range 0 110 mV ADC Clock Frequency 1.56 MHz Temperature Coefficient 120 mV Range 0 mV to 100 mV 78 ppm/°C 0 mV to 50 mV 70 ppm/°C 60 mV Range 0 mV to 50 mV 156 ppm/°C 0 mV to 25 mV 140 ppm/°C Current Sense Measurement 120 mV Setting 0 mV to 110 mV −2.1 +2.1 % FSR −2.52 +2.52 mV 60 mV Setting 0 mV to 55 mV −4.2 +4.2 % FSR −5.04 +5.04 mV Current Sense Measurement Accuracy With 0.01% level shifting resistors 120 mV Setting 0 mV to 100 mV, VDD = 3.3 V −0.9 +0.9 % FSR −1.08 +1.08 mV 60 mV Setting 0 mV to 55 mV, VDD = 3.3 V −1.8 +1.8 % FSR −2.16 +2.16 mV Leakage Current 1.0 μA Current Sense Measurement Resolution CS2 Accurate OCP Speed 2.62 5.24 ms Current Sink (High Side) 2 mA Current Source (Low Side) 200 μA Common-Mode Voltage at the CS2+ and CS2− Pins To achieve CS2 measurement accuracy 0.8 1.0 1.4 V OrFET PROTECTION (CS2+, CS2−) Low-side and high-side current sensing Fast OrFET Accuracy −3 mV setting +3.5 −3.00 −9.5 mV −6 mV setting +0.29 −6.21 −12.71 mV −9 mV setting −2.68 −9.43 −16.18 mV −12 mV setting −5.89 −12.64 −19.39 mV −15 mV setting −9.01 −15.86 −22.71 mV −18 mV setting −12.22 −19.07 −25.92 mV −21 mV setting −15.29 −22.29 −29.29 mV −24 mV setting −18.50 −25.50 −32.50 mV Fast OrFET Speed Debounce = 40 ns 110 150 ns RTD TEMPERATURE SENSE ADC Clock Frequency 1.56 MHz Input Voltage Range RTD to AGND 0 1.6 V Usable Input Voltage Range 0 1.3 V Source Current Factory trimmed to 46 μA (Register 0x11 set to 0xE6) 44.35 46 47.65 μA Current source set to 10 μA 9.25 10.1 10.75 μA Current source set to 20 μA 18.35 20.1 21.85 μA Current source set to 30 μA 28.45 30.2 31.95 μA Current source set to 40 μA 38.45 40.3 41.95 μA Source Current Fine Setting See Register 0x11[5:0] 160 nA R T D A D C Register Update Rate 10 ms Resolution 12 Bits

Rev. 0 | Page 8 of 96 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Measurement Accuracy Factory trimmed at 1 V 0 mV to 160 mV −0.5 +0.5 % FSR −8 +8 mV 0% to 100% of usable input voltage range −3.0 +3.0 % FSR −42 +42 mV Temperature Readings According to Internal Linearization Scheme RTD source set to 46 μA (Register 0x11 set to 0xE6); NTC R0 = 100 kΩ, 1%, beta = 4250, 1%; R EXT = 16.5 kΩ, 1% 25°C to 100°C 7 °C 100°C to 125°C 5 °C O T P Threshold Accuracy T = 85°C with 100 kΩ||16.5 kΩ −0.9 +0.25 % FSR −14.4 +4 mV T = 100°C with 100 kΩ||16.5 kΩ −0.5 +1.1 % FSR −8 +17.6 mV Comparator Speed 10.5 ms OTP Threshold Hysteresis 16 mV PGOOD1, PGOOD2, SHAREo PINS (OPEN DRAIN) Output Low Voltage VOL 0.4 V PSON, FLAGIN, SHAREi PINS (DIGITAL INPUTS) Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.4 V FLAGIN Propagation Delay Does not include debounce time (Register 0x0A[3] = 1); flag action set to disable PSU 200 ns Leakage Current 1.0 μA GATE PIN Output Low Voltage VOL 0.4 V Output High Voltage VOH VDD − 0.4 V SDA/SCL PINS VDD = 3.3 V Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.4 V Output Low Voltage VOL 0.4 V Leakage Current 1.0 μA SERIAL BUS TIMING See F i g u r e 3 Clock Operating Frequency 10 100 400 kHz Bus-Free Time tBUF Between stop and start conditions 1.3 μs Start Hold Time tHD;STA Hold time after (repeated) start condition; after this period, the first clock is generated 0.6 μs Start Setup Time tSU;STA Repeated start condition setup time 0.6 μs Stop Setup Time tSU;STO 0.6 μs SDA Setup Time tSU;DAT 100 ns SDA Hold Time tHD;DAT For readback 125 ns For write 300 ns SCL Low Timeout tTIMEOUT 25 35 ms SCL Low Period tLOW 1.3 μs SCL High Period tHIGH 0.6 μs Clock Low Extend Time tLO;SEXT 25 ms SCL, SDA Fall Time tF 20 300 ns SCL, SDA Rise Time tR 20 300 ns

pending EEPROM qualification. temperature TJ = 125°C is 2.87 years and is subject to change pending EEPROM qualification. Figure 3. Serial Bus Timing Diagram

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance lines, see the AN-772 Application Note.

24 SHAREi

23 SHAREo

22 PGOOD1

21 PGOOD2

20 FLAGIN

19 PSON

18 SDA

17 SCL

1. THE ADP1046 HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE

THAT THE PAD BE SOLDERED TO THE PCB AGND PLANE. Figure 4. Pin Configuration Table 4. Pin Function Descriptions specification of 0.5% or better to allow for trimming. 2 AGND Analog Ground. This pin is the ground for the analog circuitry and the return for the VDD pin of the ADP1046. 3 VS1 Local Output Voltage Sense Input. This signal is referenced to PGND. Nominal voltage at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. 1000 pF capacitor be connected either across the resistor or from this pin to AGND. 5 CS2+ Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. high-side current sensing in a 12 V application, place a 5.5 kΩ resistor between the sense resistor and this pin. 500 pF to 1000 pF capacitor be connected either across the resistor or from this pin to AGND. ADC (nominal voltage 1 V). This signal is referenced to PGND. of 0.5% or better to allow for trimming. If this pin is not used, connect it to PGND. reference for all voltage and current sensing other than CS2± and VS3±. Star connect to AGND. when not in use. This signal is referenced to AGND. when not in use. This signal is referenced to AGND. 11 OUTA PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND. 12 OUTB PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.

Rev. 0 | Page 12 of 96 Pin No. Mnemonic Description 13 OUTC PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND. 14 OUTD PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND. 15 OUTAUX Auxiliary PWM Output. This pin can be disabled when not in use. This signal is referenced to AGND. 16 GATE OrFET Gate Drive Output. This signal is referenced to AGND. If this pin is not used, leave it floating. 17 SCL I2C Serial Clock Input. This signal is referenced to AGND. 18 SDA I2C Serial Data Input and Output (Open Drain). This signal is referenced to AGND. 19 PSON Power Supply On Input. This signal is referenced to AGND. This pin is the hardware PSON control signal. It is recommended that a 1 nF capacitor be connected from the PSON pin to AGND for noise debouncing and decoupling. 20 FLAGIN Flag Input. An external signal can be input at this pin to generate a flag condition. 21 PGOOD2 Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is controlled by the PGOOD2 flag. This pin is set by a programmable combination of internal flags. If this pin is not used, connect it to AGND. 22 PGOOD1 Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is controlled by the PGOOD1 flag. This pin is set by a programmable combination of internal flags. If this pin is not used, connect it to AGND. 23 SHAREo Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a pull-up resistor (typically 2.2 kΩ). When configured for a digital share bus, this pin is a digital output. This signal is referenced to AGND. If this pin is not used, connect it to AGND. 24 SHAREi Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referenced to AGND. If this pin is not used, connect it to AGND. 25 DGND Digital Ground. This pin is the ground reference for the digital circuitry of the ADP1046. Star connect to AGND. 26 VCORE Output of the 2.5 V Regulator. Connect a decoupling capacitor of at least 330 nF (1 μF maximum) from this pin to DGND as close to the IC as possible to minimize PCB trace length. It is recommended that the VCORE pin not be used as a reference or to generate other logic levels using resistive dividers. 27 VDD Positive Supply Input. This signal is referenced to AGND. Connect a 4.7 μF decoupling capacitor from this pin to AGND as close to the IC as possible to minimize PCB trace length. 28 RTD Thermistor Input. Place a thermistor (100 kΩ, 1%, beta = 4250, 1%) in parallel with a 16.5 kΩ, 1% resistor. This pin is referenced to AGND. If this pin is not used, connect it to AGND. 29 ADD Address Select Input. This pin is used to program the I2C address. Connect a resistor from ADD to AGND. This signal is referenced to AGND. 30 RES Resistor Input. This pin sets up the internal voltage reference for the ADP1046. Connect a 10 kΩ, ±0.1% resistor from RES to AGND. This signal is referenced to AGND. 31 VS3− Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. Connect a 0.1 μF capacitor from VS3− to AGND. 32 VS3+ Noninverting Remote Voltage Sense Input. This signal is referenced to VS3−, and the nominal input voltage at this pin is 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. This pin is the input to the high frequency Δ-Σ ADC. EP Exposed Pad. The ADP1046 has an exposed thermal pad on the underside of the package. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the PCB AGND plane.

monitoring, control, and protection of the power supply output. and Trim section for more information). least every 10 ms, a true average value is read. a local and remote voltage sense. filter to provide a high performance, cost competitive solution. Figure 16. Voltage Sense Configuration and a high frequency (HF) ADC that runs at 25 MHz. the noise is higher (see Figure 17). Figure 17. Noise Performance for Nyquist Rate and Σ-Δ ADCs frequencies is listed in Table 5. Table 5. Equivalent Resolutions for High Frequency ADC Register 0x15 every 10 ms. The VS1 signal is referenced to PGND. from the VS1 sense point instead of the VS3± sense point.

fC is the crossover frequency. fSW is the switching frequency. At one-tenth the switching frequency, the phase delay is 36°. The GUI incorporates this phase delay into its calculations. gate driver and propagation delays. Two sets of registers allow for two distinct filter responses. load current threshold (programmed using Register 0x3B[2:0]). filter. It is recommended that the GUI be used for this purpose. programmed using Register 0x7A[2:0]. must be taken to avoid shootthrough and cross-conduction. with synchronous rectification. Figure 20. PWM Pin Assignment for Full-Bridge, Phase-Shifted Topology outputs be disabled when not in use. be used as a clock reference signal. Rectifier Timing Registers section (Register 0x3F to Register 0x5C).

signals can be configured much like the other PWM outputs. duty cycle in steps of 40 ns per switching cycle. the voltage transient caused by a load step. the system enters or exits light load mode. SR delay can be applied separately as a constant dead time. offset at no load (zero current). in Register 0x70 to accommodate faster or slower adjustment. changing state within the programmed interval. prevent damage to the FETs that they are controlling. and falling edges based on the case with the least modulation. Figure 21. Modulation Limit Settings

Rev. 0 | Page 20 of 96 Fault Condition During Soft Start Each LSB in Register 0x2E corresponds to a different time step size, depending on the switching frequency (see Table 46). The modulated edges cannot extend beyond one switching cycle. If a fault condition occurs during soft start, the controller responds as programmed unless the flag is blanked. Flag blanking during soft start is programmed in Register 0x0F. The UVP and ACSNS flags are always blanked during soft start. The OTP , FLAGIN, OVP , and OCP fault flags can be blanked during soft start by setting the appropriate bits in Register 0x0F. The GUI provided with the ADP1046 is recommended for programming this feature (see Figure 22). 10045-119 Digital Compensation Filters During Soft Start Figure 22. Setting Modulation Limits (Modulation Range Shown by Arrows) The ADP1046 has a dedicated soft start filter (SSF) that can be used to fine-tune and optimize the dynamic response during the output voltage ramp-up. SOFT START The turning on and off of the ADP1046 is controlled by the hardware PSON pin and/or the software PSON register, depending on the configured settings in Register 0x2C. When the user turns on the power supply (enables PSON), the following soft start procedure occurs (see Figure 23). Before it ramps up the internal reference after the PSON signal is enabled, the ADP1046 evaluates whether the OrFET should be turned on or off by looking at the difference between VS1 and VS2. This step is done to determine whether the regulation point should be VS1 or VS3± (see Figure 23). 1. The PSON signal is enabled at Time t0. If the part is programmed to be always on (Register 0x2C[7:6] = 00), PSON is enabled as soon as VCORE is above UVLO. • If the regulation point is VS1, the soft start filter is used by default during the ramp-up. At the end of the soft start ramp, the part switches to the normal mode filter (NMF). 2. The ADP1046 waits for the programmed PS_ON delay (set in Register 0x2C[4:3]).

• If the regulation point is VS3±, the part starts the ramp using the normal mode filter (NMF). The soft start begins to ramp up the internal digital refer- ence. The total duration of the soft start ramp is program- mable from 5 ms to 100 ms using Register 0x5F[7:5]. In both cases, after the voltage reaches 12.5% of the nominal output voltage value, the load current is evaluated. 4. If the soft start from precharge function is enabled (Register 0x5F[4] = 1), the soft start ramp starts from the value of the output voltage sensed on VS1 or VS3± (depending on the OrFET status), and the soft start ramp time is reduced proportionally. If the soft start from pre- charge function is disabled, the soft start ramp time is the programmed value in Register 0x5F[7:5]. If the load current is below the light load mode threshold, the part switches to the light load mode filter (LLF).
• If the load current is above the light load mode threshold, the normal mode filter is used until the end of the soft start ramp, even if the system subsequently enters light load mode based on a change to the load current. 5. When the power supply voltage exceeds the VS1 under- voltage protection (UVP) limit (set in Register 0x34[6:0]), the UVP flag is reset. Register 0x2C can be programmed to configure the use of the different filters during soft start as follows: 6. The OrFET is turned on as soon as the OrFET enable thresh- old is met. (The OrFET enable threshold is programmed in Register 0x30[6:5].) The regulation point is switched from VS1 to VS3±. Force soft start filter (Bit 0). This option forces the part to use the soft start filter even when the regulation point is VS3. In some cases, this option allows better fine-tuning of the ramp-up voltage. This option can also be selected when an OrFET is not used. If no other fault conditions are present, the PGOODx signals wait for the programmed debounce time (set in Register 0x2D[7:4]) and are then enabled. The soft start flag must be unmasked in Register 0x7B and Register 0x7C (Bit 7 must be set to 0). Disable light load mode during soft start (Bit 1). This option prevents the use of the light load mode filter during soft start, even if the light load condition is met. The light load mode filter is available for use after the end of the soft start ramp. If no OrFET is used, the power supply must be configured to regulate using VS3 at all times (Register 0x33[2] = 1). VS2 can be used as a secondary OVP mechanism.

the unit can be hot-swapped. to turn the OrFET on or off. of the nominal output voltage.

• Fault flag. Any flag in a fault configuration register (Register 0x08 to Register 0x0D) can be programmed with an action to turn off the OrFET. The OrFET is kept off for as long as the flag is set. OrFET programmable comparator. If the reverse voltage present on CS2± exceeds the analog comparator threshold programmed in Register 0x30[4:2], the OrFET is turned off. This comparator can be disabled using Register 0x30[0]. GATE signal disable. When Register 0x5D[0] = 1, the GATE signal is disabled and has no effect on the VSx feedback point. OrFET GATE Control and Regulation Points The GATE signal is enabled when the threshold configured in Register 0x30[6:5]) is met. The GATE signal controls a very important function of output voltage regulation: the control loop sensing point.
• When the GATE signal is disabled, the OrFET is turned off and the voltage regulation sensing point is VS1.
• When the GATE signal is enabled, the OrFET is turned on and the voltage regulation sensing point is VS3±. Recommended Setup for a 12 V Application In normal operating mode, follow this procedure:
• When 12 V < VOUT < OVP , use the fast OrFET control circuit to turn off the OrFET.
• When VOUT > OVP , use load OVP to turn off the OrFET. In light load mode, follow this procedure:
• When 12 V < VOUT < OVP , use ACSNS to turn off the OrFET.
• When VOUT > OVP , use load OVP to turn off the OrFET. In a 12 V application, when an internal short circuit occurs, use CS1 OCP or VS1 UVP to shut down the unit and restart it. FAST OrFET COMPARATOR FAST OrFET THRESHOLD OrFET DISABLE CS2– CS2+ 12V 11kΩ11kΩ 1kΩ1kΩ VOUT VS2 VS1 RSENSE GATE FAST OrFET BYPASS FAST OrFET DEBOUNCE S R QOrFET ENABLE OrFET ENABLE THRESHOLD FLAGS DRIVER DEBOUNCE GATE DISABLE 10045-122

Figure 25. OrFET Control Circuit Internal Detailed Diagram

EEPROM download, the ADP1046 is ready for operation.

• CS1 fast OCP If the ADP1046 is programmed to power up at this time (PSON is enabled), the soft start ramp begins. Otherwise, the part waits for the PSON signal.
• CS1 accurate OCP
• CS2 accurate OCP
• UVP The proper amount of decoupling capacitance must be placed between VDD and AGND, as close as possible to the device to minimize the trace length. It is recommended that the VCORE pin not be used as a reference or to generate other logic levels using resistive dividers. Local OVP (fast and accurate)
• Load OVP
• OrFET (GATE pin) The masking of these flags is programmed in Register 0x7B (for PGOOD1) and Register 0x7C (for PGOOD2). When a flag is masked, it does not set PGOOD1 or PGOOD2. VDD/VCORE OVLO The ADP1046 has built-in overvoltage protection (OVP) on its supply rails. When the VDD or VCORE voltage rises above the OVLO threshold, the response can be programmed using Register 0x0E[7:5]. It is recommended that when a VDD/ VCORE OVP fault occurs, the response be set to download the EEPROM before restarting the part (set Register 0x0E[6] = 1). The following additional flags can also set the PGOOD2 pin either unconditionally or based on the flag response, as programmed in Register 0x2D[3] (see Figure 30 and Table 45). Voltage continuity
• OrFET disable
• ACSNS
• External flag (FLAGIN pin)
• OTP These additional flags can be programmed in Register 0x2D[3] to always set PGOOD2 or to set PGOOD2 only if the flag action is not set to “ignore” in the fault configuration register for that flag (see Table 12 and Table 13). PGOOD1 (FLAG AND PIN) PGOOD2 (FLAG AND PIN) ADDITIONAL FLAGS -VOLTAGE CONTINUITY -OrFET DISABLE -ACSNS -FLAGIN -OTP MASKED BY REG 0x7B MASKED BY REG 0x7C DEBOUNCE (REG 0x2D[7:6]) DEBOUNCE (REG 0x2D[5:4]) 10045-127 MAIN FLAGS -SOFT START -CS1 FAST OCP -CS1 ACCURATE OCP -CS2 ACCURATE OCP -UVP -LOCAL OVP (FAST AND ACCURATE) -LOAD OVP -OrFET (GATE PIN) IF REG 0x2D[3] = 0, THE ADDITIONAL FLAGS ALWAYS AFFECT PGOOD2, REGARDLESS OF THE PROGRAMMED ACTION. IF REG 0x2D[3] = 1, THE ADDITIONAL FLAGS AFFECT PGOOD2 ONLY IF THEY ARE NOT SET TO BE IGNORED.

Figure 30. PGOOD1, PGOOD2 Programming

(this setting is programmed in Register 0x29[3]). is proportional to the current delivered by this unit to the load. output voltage and, in turn, its current contribution to the load. providing (the higher the current, the larger the digital word). ration of the digital share bus. Figure 31. Digital Current Share Configuration zation with the other ADP1046 devices during the next start bit. The digital share bus frame is shown in Figure 33. Figure 32. Analog Current Share Configuration

2 STOP BITS

Figure 33. Digital Current Share Frame Timing Diagram

Figure 34 shows the possible signals on the share bus. Figure 34. Share Bus High, Low, and Idle Bits The bus is idle when it is high during the whole period of tBIT. with the digital words of all the other supplies on the bus. the value on the bus, it means that this supply must be a slave. because either of them may be the master. must be a slave and it stops communicating on the share bus. determine whether each unit is the master or a slave. width of the share bus loop is programmable in Register 0x29[2:0]. by programming Register 0x29[3].

1195 DEC

8 BITS

74 DEC

Figure 35. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus

Rev. 0 | Page 27 of 96 POWER SUPPLY SYSTEM AND FAULT MONITORING The ADP1046 has extensive system and fault monitoring capabilities. The system monitoring functions include voltage, current, power, and temperature readings. The fault conditions include out-of-limit values for current, voltage, power, and temperature. The limits for the fault conditions are programmable. The ADP1046 has an extensive set of flags that are set when certain programmed thresholds or limits are exceeded. These thresholds and limits are described in the Fault Registers section. FLAGS The ADP1046 has an extensive set of flags that are set when certain limits, conditions, and thresholds are exceeded. The real-time status of these flags can be read in Register 0x00 to Register 0x03. The response to these flags is individually programmable. Flags can be ignored or used to trigger actions such as turning off certain PWM outputs or the OrFET gate. Flags can also be used to turn off the power supply. The ADP1046 can be programmed to respond when these flags are reset. For more information, see the Fault Registers section. The ADP1046 also has a set of latched fault registers (Register 0x04 to Register 0x07). The latched fault registers have the same flags as Register 0x00 to Register 0x03, but the flags in the latched registers remain set so that intermittent faults can be detected. Reading a latched fault register resets all the flags in that register. MONITORING FUNCTIONS The ADP1046 monitors and reports several signals, including voltages, currents, power, and temperature. All these values are stored in separate registers and can be read through the I2C interface. For more information, see the Value Registers section. VOLTAGE READINGS The VS1, VS2, and VS3 ADCs have an input range of 1.6 V . The outputs of the ADCs are 12-bit values, which means that the LSB size is 1.6 V/4096 = 390.625 μV . The user is limited to an input range of 1.4 V , which means that the ADC output code is limited to 1.4 V/390.6 μV = 3584. The equation to calculate the ADC code at a specified voltage (Vx) at the pin is given by the following formula: ADC Code = Vx/1.6 × 4096 For example, when there is 1 V on the input of the ADC, ADC Code = 1 V/1.6 × 4096 ADC Code = 2560 In a 12 V application, the 12 V reading is divided down using a resistor divider network to provide 1 V at the sense pin. Therefore, to convert the register value to a real voltage, use the following formula: V OUT = (LSB × 2560) × ((R1 + R2)/R2) In a 12 V system, this equates to VOUT = (390.625 μV × 2560) × (11 kΩ + 1 kΩ)/1 kΩ CURRENT READINGS CS1 Pin CS1 has an input range of 1.4 V . The ADC performs a 12-bit reading conversion of this value, which means that the LSB size is 1.4 V/4096 = 341.8 μV . When there is exactly 1 V on the CS1 pin, the value in the CS1 value register (Register 0x13[15:4]) reads 2926. The equation to calculate the ADC code at a specified CS1 input voltage (Vx) is given by the following formula: ADC Code = Vx/1.4 × 4096 For example, when there is 1 V on the CS1 input pin, ADC Code = 1 V/1.4 × 4096 ADC Code = 2926 CS2+, CS2− Pins The full-scale (FS) range for the CS2 ADC can be set to 60 mV or 120 mV using Register 0x27[5]. The CS2 ADC has an input range of 120 mV . The resolution is 12 bits, which means that the LSB size is 120 mV/4096 = 29.30 μV . The user is limited to an input range of 110 mV . The equation to calculate the ADC code at a specified voltage (VX) is given by the following formula: ADC Code = Vx/(120 mV) × 4096 For example, when there is 50 mV on the input of the ADC, ADC Code = 50 mV/120 mV × 4096 ADC Code = 1707 Therefore, to convert the CS2 register value to a real current, use the following formula: I OUT = (CS2_ADC_CODE/4096) × (FS/RSENSE) where: CS2_ADC_CODE is the value in Register 0x18[15:4]. FS is the full-scale voltage drop (60 mV or 120 mV). RSENSE is the sense resistor value. For example, if CS2_ADC_CODE = 1520, RSENSE = 10 mΩ, and FS = 120 mV , the real current is calculated as follows: IOUT = (1520/4096) × (120 mV/10 mΩ) IOUT = 4.453 A

to the OTP flag is programmable using Register 0x0B[7:4]. threshold (see the RTD/OTP Trim section). signal (leading edge blanking). immediately disabled for the remainder of the switching cycle. cycle. This function cannot be bypassed. response is programmed in Register 0x08. Figure 38. CS1 OCP Detailed Internal Schematic

12 ASYNCHRONOUS

Figure 39. CS2 OCP Detailed Internal Schematic the readings are averaged every 2.62 ms to make a fault decision. The flag response is programmed in Register 0x09. 3% current below the CS2 accurate OCP setting (see Figure 40). Figure 40. Constant Current Mode (VOUT vs. IOUT) the load increases to ensure that the current remains constant. can be used to program a shutdown action. The sampling time for the ADC based comparators is 80 μs. Bits[1:0] of Register 0x32 and Register 0x33. debounce time. These values are programmed in Register 0x37.

(see the Voltage Line Feedforward and ACSNS section). This ADC has an equivalent resolution of 11 bits at 10 μs. ADC has a resolution of 12 bits at 10 ms. synchronous rectifier stage (or rectifier diodes). to the ACSNS pin through an external RCD divider network. where Vx is the voltage at the ACSNS pin. where VSENSE is the filtered secondary voltage. action for the flag is executed. information, see the Resonant Mode Operation section. Figure 41. Voltage Sense Window in Simulation Mode (ADP1046 GUI)

Rev. 0 | Page 33 of 96 POWER SUPPLY CALIBRATION AND TRIM The ADP1046 allows the entire power supply to be calibrated and trimmed digitally in the production environment. It can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors and resistor dividers, as well as its own internal circuitry. The part is factory trimmed, but it can be retrimmed by the user to compensate for the errors intro- duced by external components. The ADP1046 GUI allows the user to automatically revert the trim settings to their factory default values. To unlock the trim registers for write access, write to the TRIM_PASSWORD register (Register 0x89). Write the trim password twice (the factory default password is 0xFF). The ADP1046 allows the user enough trim capability to trim for external components with a tolerance of 0.5% or better. If the ADP1046 is not trimmed in the production environment, it is recommended that components with a tolerance of 0.1% or better be used for the inputs to CS1, CS2, VS1, VS2, and VS3 to meet data sheet specifications. CS1 TRIM Using a DC Signal A known voltage (Vx) is applied at the CS1 pin. The CS1 ADC should output a digital code equal to Vx/1.4 × 4096. The CS1 gain trim register (Register 0x21) is adjusted until the CS1 ADC value in Register 0x13[15:4] reads the correct digital code. Using an AC Signal A known current (Ix) is applied to the PSU input. This current passes through a current transformer, a diode rectifier, and an external resistor (RCS1) to convert the current information to a voltage (Vx). This voltage is fed into the CS1 pin. The voltage (Vx) is calculated as follows: Vx = Ix × (N1/N2) × R CS1 where N1/N2 is the turns ratio of the current transformer. The CS1 ADC outputs a digital code equal to Vx/1.4 × 4096. The CS1 gain trim register (Register 0x21) is adjusted until the CS1 ADC value in Register 0x13[15:4] reads the correct digital code. CS2 TRIM The CS2 trim must compensate for offset and gain errors. The offset error requires both an analog trim and a digital trim. This error includes the mismatch of the level shifting resistors to the inputs of the CS2± differential amplifier and the tolerance of the current sense element. CS2 Offset Trim Offset errors can be introduced by the external level shifting resistors and the internal current sources. It is best to use two 0.1% matched resistors or matched resistors within the same package. It is important to perform the CS2 offset trim as described in the following steps: Set high-side or low-side current sensing using Register 0x27[2]. 2. Set the nominal full-scale sense resistor voltage drop in Register 0x27[5] to 1 for the 120 mV range or to 0 for the 60 mV range. Apply no-load current across the sense resistor. 4. Set the CS2 gain trim value to 0 (Register 0x23 = 0). 5. Set the CS2 digital offset trim value to 0 (Register 0x25 = 0). 6. Adjust the CS2 analog offset trim value in Register 0x24[6:0]. For the 120 mV range, adjust Register 0x24 until the CS2 value in Register 0x18[15:4] reads as close to 100 decimal (0x64) as possible; this value must be greater than 50 (0x32). For the 60 mV range, adjust Register 0x24 until the CS2 value in Register 0x18[15:4] reads as close to 200 decimal (0xC8) as possible; this value must be greater than 100 (0x64). Adjust the CS2 digital offset trim value in Register 0x25 until the CS2 value in Register 0x18[15:4] reads 0. The offset trim is now completed, and the ADC code reads 0 if there is a no-load current across the sense resistor. CS2 Gain Trim After performing the offset trim, perform the gain trim to remove any mismatch that is introduced by the sense resistor tolerance. The ADP1046 can trim for sense resistors with a tolerance of 1% or better. 1. Apply a known load current (IOUT) across the sense resistor. 2. Adjust the CS2 gain trim value in Register 0x23[5:0] until the CS2 value in Register 0x18[15:4] reads the value calculated by the following formula: CS2 Value = IOUT × RSENSE/FS × 4096 where: FS is the full-scale voltage drop (120 mV or 60 mV). RSENSE is the sense resistor value. If CS2 is programmed to the 120 mV range and IOUT = 10 A, RSENSE = 10 mΩ, and FS = 120 mV , CS2 Value = (10 A × 10 mΩ)/120 mV × 4096 CS2 Value = 3413 decimal If CS2 is programmed to the 60 mV range and IOUT = 5 A, RSENSE = 5 mΩ, and FS = 60 mV , CS2 Value = (5 A × 5 mΩ)/60 mV × 4096 CS2 Value = 1707 decimal The CS2 circuit is now trimmed. The OCP limits and settings should be configured after the current sense trim is performed.

Rev. 0 | Page 34 of 96 VOLTAGE CALIBRATION AND TRIM The voltage sense inputs are optimized for sensing signals at 1 V (the usable input range is 1.4 V). In a 12 V system, a 12:1 resistor divider is required to reduce the 12 V signal to below 1.4 V . It is recommended that the output voltage of the power supply be reduced to 1 V at this pin for best performance. The tolerance of the resistor divider introduces errors that need to be trimmed. The ADP1046 has enough trim range to trim out errors introduced by resistors with a tolerance of 0.5% or better. The VS1, VS2, and VS3 ADCs produce a digital code equal to VSx/1.6 × 4096. The ADCs output a digital word of 2560 decimal (0xA00) in Bits[15:4] of Register 0x15, Register 0x16, and Register 0x17 when there is exactly 1 V at their inputs. OUTPUT VOLTAGE SETTING (VS3+, VS3− TRIM) The VS3± inputs require a gain trim. Set the output regulation point to 100% of the nominal value (Register 0x31 = 0xA0). Enable the power supply with no-load current. The power supply output voltage is divided down by the VS3 resistor divider to give 1 V across the VS3+ and VS3− differential input pins. The VS3 trim register (Register 0x3A) is adjusted until the output voltage is at the desired value. This step should be performed before any other trim routine. The VS3 voltage value in Register 0x17[15:4] reads 2560 decimal (0xA00). VS1 TRIM The VS1 input requires a gain trim. Enable the power supply with no-load current. It is recommended that the VS1 voltage be divided down by the VS1 resistor divider to give 1 V at the VS1 pin. The VS1 trim register (Register 0x38) is adjusted until the VS1 value in Register 0x15[15:4] reads 2560 decimal (0xA00). VS2 TRIM The VS2 input requires a gain trim. Enable the power supply with no-load current. It is recommended that the VS2 voltage be divided down by the VS2 resistor divider to give 1 V at the VS2 pin. The VS2 trim register (Register 0x39) is adjusted until the VS2 value in Register 0x16[15:4] reads 2560 decimal (0xA00). RTD/OTP TRIM The RTD input requires two trims: one for the current source and one for the ADC. To use the internal linearization scheme, additional trimming procedures are required. Trimming the Current Source Bits[7:6] of Register 0x11 set the value of the current source to 10 μA, 20 μA, 30 μA, or 40 μA. Bits[5:0] of Register 0x11 can be used to fine-tune the current value. By fine-tuning the internal current source, component tolerance can be compensated for and errors can be minimized. One LSB in Bits[5:0] = 160 nA. A decimal value of 1 adds 160 nA to the current source set by Bits[7:6]; a decimal value of 63 adds 63 × 160 nA = 10.08 μA to the current source set by Bits[7:6]. To program a value for the current source, select the nearest possible option (10 μA, 20 μA, 30 μA, or 40 μA) using Register 0x11[7:6]. Then use Register 0x11[5:0] to achieve the finer step size. For example, to use a value of 46 μA as the current source, follow these steps: Place a known resistor (Rx) from RTD to AGND. 2. Set Register 0x11[7:6] to 11 (40 μA). 3. Increase the value of Register 0x11[5:0] one LSB at a time until the voltage at the RTD pin is VRTD = 46 μA × Rx. The current source is now calibrated and is set to the factory default value. Trimming the ADC Due to the nonlinear nature of the thermistor, two trimming options can be used. Using the Internal Linearization Scheme The first option uses the internal linearization scheme with 46 μA RTD current, which provides an accurate reading in °C read in Register 0x1B in decimal format. A 100 kΩ, 1% NTC thermistor with beta = 4250, 1% (such as the NCP15WF104F03RC) in parallel with an external resistor of 16.5 kΩ, 1%, should be used with the ADP1046. With this NTC thermistor and resistor combination, the ADP1046 default current source trim is set to 46 μA to achieve the best possible accuracy over temperatures ranging from 85°C to 125°C. If an external microcontroller is used, the RTD ADC code in Register 0x1A can be fed into the microcontroller and a different linearization scheme can be implemented in terms of a best-fit polynomial for the selected NTC characteristics.

temperatures of interest. The second option does not use the linearization scheme. tolerances of the thermistor being used. Vx is the voltage at the ACSNS pin. Figure 44. RTD Pin Voltage, ADC Code, and Temperature

1. Adjust the desired RTD current source, IRTD, as described

in the Trimming the Current Source section.

1. Set the temperature to the OTP threshold.

average voltage constant during the rectifier off time. Set the OTP threshold (Register 0x2F) to the value of V2.

1. Set the temperature to the hysteresis point where the OTP

until the correct voltage is seen in Register 0x1A.

Rev. 0 | Page 36 of 96 LAYOUT GUIDELINES This section explains best practices that should be followed to ensure optimal performance of the ADP1046. In general, all components should be placed as close to the ADP1046 as possible. All signals should be referenced to their respective grounds. CS2+ AND CS2− The routing of the traces from the sense resistor to the ADP1046 should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. VS3+ AND VS3− The routing of the traces from the remote voltage sense point to the ADP1046 should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. Place a 100 nF capacitor from VS3− to AGND to reduce common-mode noise. VDD Place decoupling capacitors as close to the part as possible. A 4.7 μF capacitor from VDD to AGND is recommended. SDA AND SCL The routing of the traces should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. CS1 Run the traces from the current sense transformer to the ADP1046 in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. EXPOSED PAD The exposed pad underneath the ADP1046 should be soldered to the PCB AGND plane. VCORE Place a 330 nF decoupling capacitor from this pin to DGND as close to the part as possible. RES Place a 10 kΩ, ±0.1% resistor from this pin to AGND as close to the part as possible. RTD Route a single trace to the ADP1046 from the thermistor using a dedicated trace to AGND. Place the thermistor close to the hottest part of the power supply. AGND, DGND, AND PGND Create an AGND ground plane and make a single-point (star) connection to the power supply system ground. Connect DGND to AGND with a very short trace using a star connection. Connect PGND to AGND using a star connection.

Rev. 0 | Page 39 of 96 GENERAL CALL SUPPORT The ADP1046 is capable of decoding and acknowledging a general call address. The general call address is supported for send, write, and read commands that use Address 0x00 as the slave address. The I 2C slave responds to both its own address and to the general call address (0x00). Note that all commands start with a slave address with the R/W bit cleared (set to 0), followed by the command code. This is also true when using the general call address to communicate with the I 2C slave device. 10-BIT ADDRESSING The ADP1046 does not support 10-bit addressing as defined in the I2C specification. FAST MODE Fast mode (400 kB/sec) uses essentially the same mechanics as the standard mode of operation; the electrical specifications and timing are most affected. The I2C slave is capable of commu- nicating with a master device operating in standard mode (100 kB/sec) or fast mode. REPEATED START CONDITION In general, a repeated start condition is the absence of a stop condition between two transfers. The two transfers can be of any direction type, for example, a transmit followed by a receive or a receive followed by a transmit. However, the ADP1046 I2C communication protocol uses the repeated start condition only when performing a read access (read byte, read word, and block read). Other uses of the repeated start condition are not allowed. ELECTRICAL SPECIFICATIONS All logic complies with the electrical specifications outlined in the Philips I2C Bus Specification, Version 2.1, dated January 2000. FAULT CONDITIONS The I2C protocol provides a very comprehensive set of fault conditions that are monitored during communication. These communication faults are error conditions associated with the data transfer mechanism of the I 2C protocol and are explained in the following sections. TIMEOUT CONDITION A timeout condition occurs if any single SCL clock pulse is held low for longer than the tTIMEOUT, MIN of 25 ms. Upon detecting the timeout condition, the I2C slave device has 10 ms to abort the transfer, release the bus lines, and be ready to accept a new start condition. The device initiating the timeout is required to hold the SCL clock line low for a minimum of t TIMEOUT, MAX = 35 ms, guaranteeing that the slave device is given enough time to reset its communication protocol. DATA TRANSMISSION FAULTS Data transmission faults occur when two communicating devices violate the I2C communication protocol. Sending Too Few Bits Transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been sent. Not supported; any transmitted data is ignored. Reading Too Few Bits Transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been read. Not supported; any received data is ignored. Host Sends or Reads Too Few Bytes If a host ends a packet with a stop condition before the required bytes are sent/received, it is assumed that the host intended to stop the transfer. Therefore, the I2C slave does not consider this to be an error and takes no action, except to flush any remain- ing bytes in the transmit FIFO. Host Sends Too Many Bytes If a host sends more bytes than are expected for the corre- sponding command, the I2C slave considers this a data transmission fault and responds as follows:  NACKs all unexpected bytes as they are received  Flushes and ignores the received command and data Host Reads Too Many Bytes If a host reads more bytes than are expected for the corre- sponding command, the I2C slave considers this a data transmission fault and sends all 1s (0xFF) as long as the host continues to request data. Device Busy The I2C slave device is too busy to respond to a request from the master device. Typically SCL clock stretching is involved until the device is free to communicate. DATA CONTENT FAULTS Data content faults occur when data transmission is successful, but the I2C slave device cannot process the data that is received from the master device. Improperly Set Read Bit in the Address Byte All I2C commands start with a slave address with the R/W bit cleared (set to 0), followed by the command code. If a host starts an I2C transaction with R/W set in the address phase (equivalent to an I2C read), the I2C slave considers this a data content fault and responds as follows:  ACKs the address byte  NACKs the command and data bytes  Sends all 1s (0xFF) as long as the host continues to request data

Rev. 0 | Page 40 of 96 Invalid or Unsupported Command Code If an invalid or unsupported command code is sent to the I2C slave, the I2C slave considers this a data content fault and responds as follows:

• NACKs the illegal/unsupported command byte and data bytes
• Flushes and ignores the received command and data Reserved Bits Accesses to reserved bits are not a fault. Writes to reserved bits are ignored, and reads from reserved bits return undefined data. Write to Read-Only Commands If a host performs a write to a read-only command, the I2C slave considers this a data content fault and responds as follows:
• NACKs all unexpected data bytes as they are received
• Flushes and ignores the received command and data Note that this is the same error described in the Host Sends Too Many Bytes section. Read from Write-Only Commands If a host performs a read from a write-only command, the I2C slave considers this a data content fault and send all 1s (0xFF) as long as the host continues to request data. Note that this is the same error described in the Host Reads Too Many Bytes section.

to communicate with the embedded 8K × 8-byte EEPROM. partitioned into 16 pages, each page containing 512 bytes. the different operations to the EEPROM. I2C Bus Specification, Version 2.1, dated January 2000. use, and their contents should not be erased. unlock the EEPROM, see the Unlock the EEPROM section. using the EEPROM_PAGE_ERASE command (Register 0x87). Figure 54. Example Erase Command In this example, command code = 0x87 and data byte = 0x0A. operation to complete before executing the next I2C command. must first be erased (set high) for that byte to be writable. as that byte has not been written to a logic low previously. Page 0 or Page 1 returns invalid data. the EEPROM_ADDR_OFFSET command (Register 0x85). the EEPROM, starting from the fifth byte of that page. Set the number of return bytes = 3.

1. Read three bytes from Page 4.

Rev. 0 | Page 42 of 96 WRITE OPERATION (BYTE WRITE AND BLOCK WRITE) Write to Main Block, Page 0 and Page 1 Page 0 and Page 1 of the main block are reserved for storing the default settings and user settings, respectively. The user cannot perform a direct write operation to Page 0 or Page 1 using the EEPROM_DATA_00 and EEPROM_DATA_01 commands. A user write to Page 0 or Page 1 returns a no acknowledge. To program the register contents of Page 1 of the main block, it is recommended that the STORE_USER_ALL command be used (Register 0x82). See the Save Register Settings to User Settings section. Write to Main Block, Page 2 and Page 3 Page 2 and Page 3 of the main block are reserved for internal use and their contents should not be written to. Only Page 4 to Page 15 should be used to store data. Write to Main Block, Page 4 to Page 15 Before performing a write to Page 4 through Page 15 of the main block, the user must first unlock the EEPROM (see the Unlock the EEPROM section). Data in Page 4 to Page 15 of the EEPROM main block can be programmed (written to) one byte at a time or in multiple bytes in series using the EEPROM_DATA_xx commands (Register 0x8B to Register 0x9A). Before executing this command, the user can program the offset from the page boundary where the first byte is written using the EEPROM_ADDR_OFFSET command (Register 0x85). If the targeted page has not yet been erased, the user can erase the page as described in the Page Erase Operation section. In the following example, four bytes are written to Page 9, starting from the 256 th byte of that page. 1. Set address offset = 256. 10045-204 S 7-BIT SLAVE ADDRESS W A A 0x00AA P0x85 0x01 = MASTER-TO-SLAVE = SLAVE-TO-MASTER 2. Write four bytes to Page 9. 10045-205 S 7-BIT SLAVE ADDRESS BYTE COUNT = 4W A A A0x94 DATA BYTE 1 DATA BYTE 4A A P... = MASTER-TO-SLAVE = SLAVE-TO-MASTER Note that the block write command can write a maximum of 256 bytes for any single transaction (set the byte count = 0). EEPROM PASSWORD On power-up, the EEPROM is locked and protected from accidental writes or erases. Only reads from Page 2 to Page 15 of the main block are allowed when the EEPROM is locked. Before any data can be written (programmed) to the EEPROM, the EEPROM must be unlocked for write access. After it is unlocked, the EEPROM is opened for reading, writing, and erasing. Unlock the EEPROM To unlock the EEPROM, perform two consecutive writes with the correct password (default = 0xFF) using the EEPROM_ PASSWORD command (Register 0x88). The EEPROM unlocked flag (Bit 0 of Register 0x03) is set to indicate that the EEPROM is unlocked for write access. Lock the EEPROM To lock the EEPROM, write any byte other than the correct pass- word using the EEPROM_PASSWORD command (Register 0x88). The EEPROM unlocked flag (Bit 0 of Register 0x03) is cleared to indicate that the EEPROM is locked from write access. Change the EEPROM Password To change the EEPROM password, first write the correct password using the EEPROM_PASSWORD command (Register 0x88). Immediately write the new password using the same command. The password is now changed to the new password. DOWNLOADING EEPROM SETTINGS TO INTERNAL REGISTERS Download User Settings to Registers The user settings are stored in Page 1 of the EEPROM main block. These settings are downloaded from the EEPROM into the registers under the following conditions:  On power-up. The user settings are automatically down- loaded into the internal registers, powering the part up in a state previously saved by the user.  On execution of the RESTORE_USER_ALL command (Register 0x83). This command allows the user to force a download of the user settings from Page 1 of the EEPROM main block into the internal registers. Download Factory Default Settings to Registers The factory default settings are stored in Page 0 of the EEPROM main block. The factory default settings can be downloaded from the EEPROM into the internal registers using the RESTORE_ DEFAULT_ALL command (Register 0x81). When this command is executed, the EEPROM password is also reset to the factory default setting of 0xFF.

Rev. 0 | Page 43 of 96 SAVING REGISTER SETTINGS TO THE EEPROM The register settings cannot be saved to the factory default set- tings located in Page 0 of the EEPROM main block. This is to prevent the user from accidentally overriding the factory trim settings and default register settings. Save Register Settings to User Settings The register settings can be saved to the user settings located in Page 1 of the EEPROM main block using the STORE_USER_ALL command (Register 0x82). Before this command can be executed, the EEPROM must first be unlocked for writing (see the Unlock the EEPROM section). After the register settings are saved to the user settings, any subsequent power cycle automatically downloads the latest stored user information from the EEPROM into the internal registers. Note that execution of the STORE_USER_ALL command auto- matically performs a page erase to Page 1 of the EEPROM main block, after which the register settings are stored in the EEPROM. Therefore, it is important to wait at least 40 ms for the operation to complete before executing the next I 2C command. EEPROM CRC CHECKSUM As a simple method of checking that the values downloaded from the EEPROM are consistent with the internal registers, a CRC checksum is implemented.  When the data from the internal registers is saved to the EEPROM (Page 1 of the main block), the total number of 1s from all the registers is counted and written into the EEPROM as the last byte of information. This is called the CRC checksum.  When the data is downloaded from the EEPROM into the internal registers, a similar counter that sums all 1s from the values loaded into the registers is saved. This value is compared with the CRC checksum from the previous upload operation. If the values match, the download operation was successful. If the values differ, the EEPROM download operation failed, and the EEPROM CRC fault flag is set (Bit 1 of Register 0x03). To read the EEPROM CRC checksum value, execute the EEPROM_CRC_CHKSUM command (Register 0x84). This command returns the CRC checksum accumulated in the counter during the download operation. Note that the CRC checksum is an 8-bit cyclical accumulator that wraps around to 0 when 255 is reached.

also available by contacting Analog Devices. Figure 55. ADP1046 GUI

Table 7. Register List

Rev. 0 | Page 46 of 96 Address Register Name 0x2F OTP threshold 0x30 OrFET Voltage Sense Registers 0x31 VS3 voltage setting (remote voltage) 0x32 VS1 overvoltage limit (OVP) 0x33 VS2 and VS3 overvoltage limit (OVP) 0x34 VS1 undervoltage limit (UVP) 0x35 Line impedance limit 0x36 Load line impedance 0x37 Fast OVP comparator 0x38 VS1 trim 0x39 VS2 trim 0x3A VS3 trim 0x3B Light load mode disable settings ID Registers 0x3C Silicon revision ID 0x3D Manufacturer ID 0x3E Device ID PWM and Synchronous Rectification Timing Registers 0x3F OUTAUX switching frequency setting 0x40 PWM switching frequency setting and PWM switching frequency setting in resonant mode 0x41 OUTA rising edge timing (OUTA pin) and OUTA rising edge dead time in resonant mode 0x42 OUTA rising edge setting (OUTA pin) and lowest switching frequency limit setting in resonant mode 0x43 OUTA falling edge timing (OUTA pin) and OUTA falling edge dead time in resonant mode 0x44 OUTA falling edge setting (OUTA pin) and lowest switching frequency limit setting in resonant mode 0x45 OUTB rising edge timing (OUTB pin) and OUTB rising edge dead time in resonant mode 0x46 OUTB rising edge setting (OUTB pin) and highest switching frequency limit setting in resonant mode 0x47 OUTB falling edge timing (OUTB pin) and OUTB falling edge dead time in resonant mode 0x48 OUTB falling edge setting (OUTB pin) and highest switching frequency limit setting in resonant mode 0x49 OUTC rising edge timing (OUTC pin) and OUTC rising edge dead time in resonant mode 0x4A OUTC rising edge setting (OUTC pin) and burst mode operation in resonant mode 0x4B OUTC falling edge timing (OUTC pin) and OUTC falling edge dead time in resonant mode 0x4C OUTC falling edge setting (OUTC pin) 0x4D OUTD rising edge timing (OUTD pin) and OUTD rising edge dead time in resonant mode 0x4E OUTD rising edge setting (OUTD pin) 0x4F OUTD falling edge timing (OUTD pin) and OUTD falling edge dead time in resonant mode 0x50 OUTD falling edge setting (OUTD pin) 0x51 SR1 rising edge timing (SR1 pin) and SR1 rising edge dead time in resonant mode 0x52 SR1 rising edge setting (SR1 pin) 0x53 SR1 falling edge timing (SR1 pin) and SR1 falling edge dead time in resonant mode 0x54 SR1 falling edge setting (SR1 pin) 0x55 SR2 rising edge timing (SR2 pin) and SR2 rising edge dead time in resonant mode 0x56 SR2 rising edge setting (SR2 pin) 0x57 SR2 falling edge timing (SR2 pin) and SR2 falling edge dead time in resonant mode 0x58 SR2 falling edge setting (SR2 pin) 0x59 OUTAUX rising edge timing (OUTAUX pin) 0x5A OUTAUX rising edge setting (OUTAUX pin) 0x5B OUTAUX falling edge timing (OUTAUX pin) 0x5C OUTAUX falling edge setting (OUTAUX pin) 0x5D OUTx and SRx pin disable settings 0x5E ACSNS gain trim

Rev. 0 | Page 47 of 96 Address Register Name Digital Filter Programming Registers 0x5F Soft start and output voltage slew rate settings 0x60 Normal mode digital filter LF gain setting 0x61 Normal mode digital filter zero setting 0x62 Normal mode digital filter pole setting 0x63 Normal mode digital filter HF gain setting 0x64 Light load mode digital filter LF gain setting 0x65 Light load mode digital filter zero setting 0x66 Light load mode digital filter pole setting 0x67 Light load mode digital filter HF gain setting Adaptive Dead Time Registers 0x68 Adaptive dead time threshold 0x69 Dead Time 1 0x6A Dead Time 2 0x6B Dead Time 3 0x6C Dead Time 4 0x6D Dead Time 5 0x6E Dead Time 6 0x6F Dead Time 7 0x70 Dead time configuration Soft Start Filter Programming Registers 0x71 Soft start digital filter LF gain setting 0x72 Soft start digital filter zero setting 0x73 Soft start digital filter pole setting 0x74 Soft start digital filter HF gain setting Extended Functions Registers 0x75 Voltage line feedforward 0x76 Volt-second balance settings (OUTA and OUTB pins) 0x77 Volt-second balance settings (OUTC and OUTD pins) 0x78 Volt-second balance settings (SR1 and SR2 pins) 0x79 SR delay compensation 0x7A Filter transitions 0x7B PGOOD1 flag masking 0x7C PGOOD2 flag masking 0x7D Light load mode threshold settings 0x7E Reserved 0x7F GO byte 0x80 Reserved EEPROM Registers 0x81 RESTORE_DEFAULT_ALL 0x82 STORE_USER_ALL 0x83 RESTORE_USER_ALL 0x84 EEPROM_CRC_CHKSUM 0x85 EEPROM_ADDR_OFFSET 0x86 EEPROM_NUM_RD_BYTES 0x87 EEPROM_PAGE_ERASE 0x88 EEPROM_PASSWORD 0x89 TRIM_PASSWORD 0x8A EEPROM_INFO 0x8B EEPROM_DATA_00 0x8C EEPROM_DATA_01 0x8D EEPROM_DATA_02 0x8E EEPROM_DATA_03 0x8F EEPROM_DATA_04

Rev. 0 | Page 48 of 96 Address Register Name 0x90 EEPROM_DATA_05 0x91 EEPROM_DATA_06 0x92 EEPROM_DATA_07 0x93 EEPROM_DATA_08 0x94 EEPROM_DATA_09 0x95 EEPROM_DATA_10 0x96 EEPROM_DATA_11 0x97 EEPROM_DATA_12 0x98 EEPROM_DATA_13 0x99 EEPROM_DATA_14 0x9A EEPROM_DATA_15

fault register be read again after the faults disappear to ensure that the register is reset. Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation) stays high until the power supply is restarted. be masked using Register 0x7C. 1.2 V threshold on the CS1 pin. Fast OCP is a comparator. Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)

7 Voltage

(VS2 − VS3) > 50 mV at the pins.

5 CS2 reverse

toggle is required to restart the power supply.

Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)

4 Constant current R Power supply is operating in constant current mode (constant

Table 11. Register 0x03—Fault Register 4 and Register 0x07—Latched Fault Register 4 (1 = Fault, 0 = Normal Operation) Table 12. Register 0x08 to Register 0x0D—Fault Configuration Registers

Register 0x08 to Register 0x0D allow the user to program the response when each flag is set. Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions 7 Timing R/W This bit specifies when the flag is set. [6:4] Action R/W These bits specify the action that the part takes in response to the flag. [2:0] Action R/W Same as Bits[6:4]. Table 14. Register 0x0E—Flag Configuration Register

7 VDD OV/VCORE OV

R/W Setting this bit to 1 means that the VDD OV and VCORE OV flags are ignored.

6 VDD OV/VCORE OV

R/W This bit specifies whether the part downloads the EEPROM contents before it restarts. 1 = if the part shuts down, it downloads the EEPROM contents again before restarting. 0 = if the part shuts down, it does not download the EEPROM contents again before restarting.

5 VDD OV/VCORE OV

this bit to 0 means that there is a 2 μs debounce before the part shuts down. R/W When an accurate OCP flag is set, there is a debounce time before the flag action is performed. 2.62 ms to 5.24 ms to this debounce time. R/W These bits specify the time delay before restarting the power supply after a shutdown. SR1, SR2, and OrFET are reenabled immediately.

and ACSNS flags are always active during soft start. Table 15. Register 0x0F—Soft Start Blank Fault Flags Register 6 Blank OTP R/W Setting this bit means that the OTP flag is ignored until the end of the soft start ramp time. 5 Blank FLAGIN R/W Setting this bit means that the FLAGIN flag is ignored until the end of the soft start ramp time.

4 Blank local OVP

R/W Setting this bit means that the local OVP flag is ignored until the end of the soft start ramp time. 3 Blank load OVP R/W Setting this bit means that the load OVP flag is ignored until the end of the soft start ramp time.

2 Blank CS2 accurate

1 Blank CS1 accurate

0 Blank CS1 fast OCP R/W Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time. Table 16. Register 0x10—First Flag ID this register also resets the register. Table 17. Register 0x11—RTD Current Source These bits set the size of the current source on the RTD pin. independent of the RTD current setting selected in Register 0x11[7:6].

Table 18. Register 0x12—HF ADC Reading [7:0] HF ADC reading R This register contains the reading from the high frequency ADC. Table 19. Register 0x13—CS1 Value (Input Current) resolution, which results in an LSB size of 342 μV. At 0 V input, the value in this register is 0 (0x000). At 1 V input, the value in this register is 2926 (0xB6E). Table 20. Register 0x14—ACSNS Value [15:4] ACSNS voltage value R This register contains the 12-bit ACSNS slow ADC voltage information. Table 21. Register 0x15—VS1 Voltage Value recommended nominal voltage at this pin is 1 V. At 1 V input, these bits read 2560 (0xA00). Table 22. Register 0x16—VS2 Voltage Value recommended nominal voltage at this pin is 1 V. At 1 V input, these bits read 2560 (0xA00). Table 23. Register 0x17—VS3 Voltage Value (Output Voltage) input, the value in this register is 0 (0x000). The recommended nominal voltage at this pin is 1 V. At 1 V input, these bits read 2560 (0xA00).

Table 24. Register 0x18—CS2 Value (Output Current) resolution; the LSB step size depends on the input range value. a 30 mV input signal on CS2, the value in this register is 30 mV/29.30 μV = 1024 (0x400). a 30 mV input signal on CS2, the value in this register is 30 mV/14.65 μV = 2048 (0x800). Table 25. Register 0x19—CS2 × VS3 Value (Output Power) section for the formulas needed to convert this digital reading into power information. Table 26. Register 0x1A—RTD Temperature Value which results in an LSB size of 390.625 μV. At 0 V input, the value in this register is 0 (0x000). The recommended nominal voltage at this pin is 1 V. At 1 V input, these bits read 2560 (0xA00). Table 27. Register 0x1B—Read Temperature Register 0x11[7:6] and using the current trim (fine-trim) bits in Register 0x11[5:0]. Table 28. Register 0x1C—RTD Offset Trim (MSB) 1 Trim polarity R/W Setting this bit to 1 means that negative offset is introduced. Setting this bit to 0 means that positive offset is introduced. the amount of offset trim that is applied to the RTD ADC reading. Table 29. Register 0x1D—Share Bus Value master, this register outputs 0. Table 30. Register 0x1E—Modulation Value modulation from 0% to 100% that is being placed on the modulating edges. Table 31. Register 0x1F—Line Impedance Value [7:0] Line impedance value R This register contains the 8-bit line impedance information. This value is (VS2 − VS3)/CS2.

Table 32. Register 0x20—RTD Offset Trim (LSBs) is applied to the RTD ADC reading. Table 33. Register 0x21—CS1 Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. Table 34. Register 0x22—CS1 Accurate OCP Limit with the rising edge of OUTAUX. Table 35. Register 0x23—CS2 Gain Trim [7:6] Reserved R/W Reserved. 5 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. the sense resistor. See the CS2 Trim section for more information. Table 36. Register 0x24—CS2 Analog Offset Trim 6 Offset polarity R/W 1 = negative offset is introduced. 0 = positive offset is introduced.

Table 37. Register 0x25—CS2 Digital Offset Trim that is read in Register 0x18. See the CS2 Trim section for more information. Table 38. Register 0x26—CS2 Accurate OCP Limit Table 39. Register 0x27—CS1/CS2 Fast OCP Settings happens, all PWM outputs are disabled for the remainder of the switching cycle.

5 CS2 nominal voltage

section for more information. These bits set the LSB step size of the CS2 ADC. 4 CS1 fast OCP bypass R/W Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin. 3 Constant current mode R/W When this bit is set, constant current mode is enabled to 97% of the CS2 accurate OCP limit. 1 = constant current mode enabled. 0 = constant current mode disabled. sensing is used. See the CS2 Trim section for more information. cycles for the comparator before the CS1 fast OCP response is activated. Table 40. Register 0x28—Volt-Second Balance Settings

6 Volt-second balance

configurations). For more information, see the Volt-Second Balance section.

5 Volt-second balance

same value configured for CS1 fast OCP blanking in Register 0x22[7:5].

4 Volt-second disable

R/W 0 = do not blank volt-second balance control during soft start. 1 = blank volt-second balance control during soft start. R/W Setting this bit limits the sampling period for the current on CS1 to less than 50% of a half cycle.

2 Volt-second balance

R/W This bit specifies the maximum amount of modulation from volt-second balance.

1. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.

When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance. Table 41. Register 0x29—Share Bus Bandwidth [7:5] Reserved R/W Reserved. 3 Current share select R/W 1 = CS1 reading used for current share. 0 = CS2 reading used for current share. the lowest possible bandwidth, and the value 111 is the highest possible bandwidth. Table 42. Register 0x2A—Share Bus Setting higher the setting, the larger the voltage difference that satisfies the current sharing criteria. Table 43. Register 0x2B—Temperature Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] Gain trim R/W This register calibrates the RTD ADC gain. It calibrates for errors in the ADC. Table 44. Register 0x2C—PSON/Soft Start [7:6] PS_ON setting R/W These bits determine which signal is used by the ADP1046 as the PS_ON control. 0 0 The ADP1046 is always on. 0 1 Hardware PSON pin is used to enable or disable the power supply. 1 0 Software PS_ON bit (Bit 5) is us ed to enable or disable the power supply. before the ADP1046 is enabled. 5 PS_ON R/W Software PS_ON bit. [4:3] PS_ON delay R/W These bits set the time from when the PS_ON control signal is set to when the soft start begins.

2 Reserved R/W Set this bit to zero for normal operation.

1 Disable light load

R/W 0 = allow switching to light load mode filter during soft start. 1 = never switch to light load mode filter during soft start.

0 Force soft start

1 = use soft start filter as the initial filter regardless of OrFET status. Table 45. Register 0x2D—PGOOD Debounce and Pin Polarity Settings configuration register (see Table 12 and Table 13). 0 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags always set the PGOOD2 pin. 2 FLAGIN polarity R/W This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = 0 V = on). 1 GATE polarity R/W This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = 0 V = on). 0 PSON polarity R/W This bit sets the polarity of th e PSON input pin: 1 = inverted (low = 0 V = on). Table 46. Register 0x2E—Modulation Limit 7 Full-bridge mode R/W Enable this bit when operating in full-bridge mode. It affects the modulation high limit. resolution depends on the switching frequency range.

Table 47. Register 0x2F—OTP Threshold range are not allowed. The OTP flag has a hysteresis of 16 mV. Table 48. Register 0x30—OrFET

7 OrFET enable

R/W 0 = delay of 328 μs, equivalent to 9 bits of (VS1 − VS2) data. 1 = delay of 164 μs, equivalent to 8 bits of (VS1 − VS2) data. and VS2 input pins are used to control the OrFET enable function.

1 Fast OrFET

R/W These bits determine the debounce on the fast OrFET control before it disables the OrFET.

0 Fast OrFET

executed, unless the flag is programmed to be ignored.

Table 49. Register 0x31—VS3 Voltage Setting (Remote Voltage) setting into the state machine, the user must set the voltage reference GO bit (Register 0x7F[0]). After that, the voltage changes with a limited slew rate (programmed in Register 0x5F[2:0]). Table 50. Register 0x32—VS1 Overvoltage Limit (OVP) Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VS1 voltage. Setting these bits to 7 gives an OVP limit of 120% of the nominal VS1 voltage. Setting these bits to 15 gives an OVP limit of 130% of the nominal VS1 voltage. Setting these bits to 31 gives an OVP limit of 150% of the nominal VS1 voltage. voltage must be greater than the OVP threshold for both cycles. Table 51. Register 0x33—VS2 and VS3 Overvoltage Limit (OVP) Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VSx voltage. Setting these bits to 7 gives an OVP limit of 120% of the nominal VSx voltage. Setting these bits to 15 gives an OVP limit of 130% of the nominal VSx voltage. Setting these bits to 31 gives an OVP limit of 150% of the nominal VSx voltage.

voltage must be greater than the OVP threshold for both cycles. Table 52. Register 0x34—VS1 Undervoltage Limit (UVP)

7 End of cycle

1 = all other PWM outputs are shut down at the end of the switching cycle. 0 = all other PWM outputs are immediately shut down. Setting these bits to 0 gives a UVP limit of 0% of the nominal VS1 voltage. Setting these bits to 72 (0x48) gives a UVP limit of 90% of the nominal VS1 voltage. Setting these bits to 76 (0x4C) gives a UVP limit of 95% of the nominal VS1 voltage. Setting these bits to 80 (0x50) gives a UVP limit of 100% of the nominal VS1 voltage. Setting these bits to 127 (0x7F) gives a UVP limit of 158.75% of the nominal VS1 voltage. Table 53. Register 0x35—Line Impedance Limit value, the line impedance flag is set (Register 0x02, Bit 2). Table 54. Register 0x36—Load Line Impedance 7 Load line enable R/W Set this bit to enable the load line. the reference when adjusting the output load line value.

ROUT = 0.1 × VOUT_NOM × CS2 RSENSE/(CS2 Range × 2N). For more information, see the Digital Load Line and Slew Rate section. Table 55. Register 0x37—Fast OVP Comparator [7:6] Fast OVP debounce R/W These bits set the fast OVP debounce time. Table 56. Register 0x38—VS1 Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. is trimmed until the VS1 voltage value (Register 0x15[15:4]) reads 2560 (0xA00). Table 57. Register 0x39—VS2 Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. is trimmed until the VS2 voltage value (Register 0x16[15:4]) reads 2560 (0xA00). Table 58. Register 0x3A—VS3 Trim 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. trim must be performed before the load OVP and load UVP trims are performed.

Table 59. Register 0x3B—Light Load Mode Disable Settings Table 60. Register 0x3C—Silicon Revision ID manufacturer for tracking purposes. Table 61. Register 0x3D—Manufacturer ID (Power-On Default: 0x41) represent the Analog Devices ID code. Table 62. Register 0x3E—Device ID (Power-On Default: 0x46)

ADP1046. In general, it is recommended that t1 be set to 0 and that t1 be set as the reference point for the other signals. Figure 56. PWM Timing Diagram Table 63. Register 0x3F—OUTAUX Switching Frequency Setting the modulation low limit, pulse skipping is enabled.

6 Pulse skipping zero

R/W 0 = pulse skipping drives all modulated PWM outputs to 0 V. 1 = sets all modulated edges to t = 0 (the crossing rule set in Register 0x52[0] applies). [5:0] Switching frequency R/W This register sets the switching frequency of the OUTAUX signal.

Rev. 0 | Page 65 of 96 Bits Bit Name R/W Description [5:0] Switching frequency R/W Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz) 0 1 0 0 1 1 107.76 0 1 0 1 0 0 111.61 0 1 0 1 0 1 115.74 0 1 0 1 1 0 120.19 0 1 0 1 1 1 125.0 0 1 1 0 0 0 130.21 0 1 1 0 0 1 135.87 0 1 1 0 1 0 142.05 0 1 1 0 1 1 148.81 0 1 1 1 0 0 156.25 0 1 1 1 0 1 164.47 0 1 1 1 1 0 173.61 0 1 1 1 1 1 183.82 1 0 0 0 0 0 195.31 1 0 0 0 0 1 201.61 1 0 0 0 1 0 208.33 1 0 0 0 1 1 215.52 1 0 0 1 0 0 223.21 1 0 0 1 0 1 231.48 1 0 0 1 1 0 240.38 1 0 0 1 1 1 250 1 0 1 0 0 0 260.42 1 0 1 0 0 1 271.42 1 0 1 0 1 0 284.09 1 0 1 0 1 1 297.62 1 0 1 1 0 0 312.5 1 0 1 1 0 1 328.95 1 0 1 1 1 0 347.22 1 0 1 1 1 1 367.65 1 1 0 0 0 0 390.63 1 1 0 0 0 1 416.67 1 1 0 0 1 0 446.43 1 1 0 0 1 1 480.77 1 1 0 1 0 0 520.83 1 1 0 1 0 1 568.18 1 1 0 1 1 0 625

Table 64. Register 0x40—PWM Switching Frequency Setting [7:6] Reserved R/W Reserved. [5:0] Switching frequency R/W This register sets the switching frequency of all the PWM pins other than the OUTAUX pin.

Table 65. Register 0x41—OUTA Rising Edge Timing (OUTA Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 66. Register 0x42—OUTA Rising Edge Setting (OUTA Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t1 edge. 0 = no PWM modulation of the t1 edge. 2 t 1 sign R/W 1 = negative sign. Increase of PWM modulation moves t1 right. 0 = positive sign. Increase of PWM modulation moves t1 left.

0 Volt-second balance

Table 67. Register 0x43—OUTA Falling Edge Timing (OUTA Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 68. Register 0x44—OUTA Falling Edge Setting (OUTA Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t2 edge. 0 = no PWM modulation of the t2 edge. 2 t 2 sign R/W 1 = negative sign. Increase of PWM modulation moves t2 right. 0 = positive sign. Increase of PWM modulation moves t2 left. [1:0] Reserved R/W Reserved.

Table 69. Register 0x45—OUTB Rising Edge Timing (OUTB Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 70. Register 0x46—OUTB Rising Edge Setting (OUTB Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t3 edge. 0 = no PWM modulation of the t3 edge. 2 t 3 sign R/W 1 = negative sign. Increase of PWM modulation moves t3 right. 0 = positive sign. Increase of PWM modulation moves t3 left. Table 71. Register 0x47—OUTB Falling Edge Timing (OUTB Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 72. Register 0x48—OUTB Falling Edge Setting (OUTB Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. 3 Modulate enable R/W 1 = PWM modulation acts on the t4 edge. 0 = no PWM modulation of the t4 edge. 2 t 4 sign R/W 1 = negative sign. Increase of PWM modulation moves t4 right. 0 = positive sign. Increase of PWM modulation moves t4 left. [1:0] Reserved R/W Reserved. Table 73. Register 0x49—OUTC Rising Edge Timing (OUTC Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns.

Table 74. Register 0x4A—OUTC Rising Edge Setting (OUTC Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t5 edge. 0 = no PWM modulation of the t5 edge. 2 t 5 sign R/W 1 = negative sign. Increase of PWM modulation moves t5 right. 0 = positive sign. Increase of PWM modulation moves t5 left. Table 75. Register 0x4B—OUTC Falling Edge Timing (OUTC Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 76. Register 0x4C—OUTC Falling Edge Setting (OUTC Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. 3 Modulate enable R/W 1 = PWM modulation acts on the t6 edge. 0 = no PWM modulation of the t6 edge. 2 t 6 sign R/W 1 = negative sign. Increase of PWM modulation moves t6 right. 0 = positive sign. Increase of PWM modulation moves t6 left. [1:0] Reserved R/W Reserved. Table 77. Register 0x4D—OUTD Rising Edge Timing (OUTD Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.

Table 78. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t7 edge. 0 = no PWM modulation of the t7 edge. 2 t 7 sign R/W 1 = negative sign. Increase of PWM modulation moves t7 right. 0 = positive sign. Increase of PWM modulation moves t7 left. Table 79. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. Table 80. Register 0x50—OUTD Falling Edge Setting (OUTD Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t8 edge. 0 = no PWM modulation of the t8 edge. 2 t 8 sign R/W 1 = negative sign. Increase of PWM modulation moves t8 right. 0 = positive sign. Increase of PWM modulation moves t8 left. [1:0] Reserved R/W Reserved. Table 81. Register 0x51—SR1 Rising Edge Timing (SR1 Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. not be set between 80 ns and 115 ns when using the SR soft start.

Table 82. Register 0x52—SR1 Rising Edge Setting (SR1 Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. not be set between 80 ns and 115 ns when using the SR soft start. 3 Modulate enable R/W 1 = PWM modulation acts on the t9 edge. 0 = no PWM modulation of the t9 edge. 2 t 9 sign R/W 1 = negative sign. Increase of PWM modulation moves t9 right. 0 = positive sign. Increase of PWM modulation moves t9 left.

0 SR soft start edge

R/W 0 = always allow SR edge crossing. 1 = allow SR edge crossing only during SR soft start (recommended). Table 83. Register 0x53—SR1 Falling Edge Timing (SR1 Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 84. Register 0x54—SR1 Falling Edge Setting (SR1 Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t10 edge. 0 = no PWM modulation of the t10 edge. 2 t 10 sign R/W 1 = negative sign. Increase of PWM modulation moves t10 right. 0 = positive sign. Increase of PWM modulation moves t10 left. 1 SR soft start setting R/W 1 = SR signals perform a soft start every time that they are enabled. 0 = SR signals perform a soft start only the first time that they are enabled. 0 SR soft start enable R/W Setting this bit enables the soft start function for the SR signals. Table 85. Register 0x55—SR2 Rising Edge Timing (SR2 Pin) and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. not be set between 80 ns and 115 ns when using the SR soft start.

Table 86. Register 0x56—SR2 Rising Edge Setting (SR2 Pin) between 80 ns and 115 ns when using the SR soft start. 3 Modulate enable R/W 1 = PWM modulation acts on the t11 edge. 0 = no PWM modulation of the t11 edge. 2 t 11 sign R/W 1 = negative sign. Increase of PWM modulation moves t11 right. 0 = positive sign. Increase of PWM modulation moves t11 left. [1:0] Reserved R/W Reserved. Table 87. Register 0x57—SR2 Falling Edge Timing (SR2 Pin) absolute maximum pulse width is tPERIOD − 5 ns. Table 88. Register 0x58—SR2 Falling Edge Setting (SR2 Pin) 3 Modulate enable R/W 1 = PWM modulation acts on the t12 edge. 0 = no PWM modulation of the t12 edge. 2 t 12 sign R/W 1 = negative sign. Increase of PWM modulation moves t12 right. 0 = positive sign. Increase of PWM modulation moves t12 left. [1:0] Reserved R/W Reserved. Table 89. Register 0x59—OUTAUX Rising Edge Timing (OUTAUX Pin) again to synchronize the edges to the PWM edges for the new set of switching frequencies.

Table 90. Register 0x5A—OUTAUX Rising Edge Setting (OUTAUX Pin) adjusted again to synchronize the edges to the PWM edges for the new set of switching frequencies. 3 Modulate enable R/W 1 = PWM modulation acts on the t13 edge. 0 = no PWM modulation of the t13 edge. 2 t 13 sign R/W 1 = negative sign. Increase of PWM modulation moves t13 right. 0 = positive sign. Increase of PWM modulation moves t13 left. [1:0] Reserved R/W Reserved. Table 91. Register 0x5B—OUTAUX Falling Edge Timing (OUTAUX Pin) adjusted again to synchronize the edges to the PWM edges for the new set of switching frequencies. Table 92. Register 0x5C—OUTAUX Falling Edge Setting (OUTAUX Pin) adjusted again to synchronize the edges to the PWM edges for the new set of switching frequencies. 3 Modulate enable R/W 1 = PWM modulation acts on the t14 edge. 0 = no PWM modulation of the t14 edge. 2 t 14 sign R/W 1 = negative sign. Increase of PWM modulation moves t14 right. 0 = positive sign. Increase of PWM modulation moves t14 left.

1 Regulate with

signal is synchronized with OUTAUX. 0 Reserved R/W Reserved. Set this bit to 0 for normal operation.

Table 93. Register 0x5D—OUTx and SRx Pin Disable Settings 7 OUTAUX disable R/W Setting this bit disables the OUTAUX output. 6 SR2 disable R/W Setting this bit disables the SR2 output. 5 SR1 disable R/W Setting this bit disables the SR1 output. 4 OUTD disable R/W Setting this bit disables the OUTD output. 3 OUTC disable R/W Setting this bit disables the OUTC output. 2 OUTB disable R/W Setting this bit disables the OUTB output. 1 OUTA disable R/W Setting this bit disables the OUTA output. 0 GATE disable R/W Setting this bit disables the GATE output but does not affect the VSx feedback point. Table 94. Register 0x5E—ACSNS Gain Trim 7 Gain polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] ACSNS gain trim R/W These bits set the gain trim for the ACSNS ADC. Figure 57. Digital Filter Programmability Table 95. Register 0x5F—Soft Start and Output Voltage Slew Rate Settings [7:5] Soft start ramp R/W These bits determine the duration of the soft start ramp.

4 Soft start from

[2:0] Slew rate R/W These bits specify the slew rate at the VS3± pins for the change in the voltage reference setting. Table 96. Register 0x60—Normal Mode Digital Filter LF Gain Setting range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 97. Register 0x61—Normal Mode Digital Filter Zero Setting [7:0] Zero setting R/W This register determines the position of the final zero. See Figure 57. Table 98. Register 0x62—Normal Mode Digital Filter Pole Setting [7:0] Pole location R/W This register determines the position of the final pole. See Figure 57. Table 99. Register 0x63—Normal Mode Digital Filter HF Gain Setting range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 100. Register 0x64—Light Load Mode Digital Filter LF Gain Setting range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 101. Register 0x65—Light Load Mode Digital Filter Zero Setting [7:0] Zero setting R/W This register determines the position of the final zero. See Figure 57. Table 102. Register 0x66—Light Load Mode Digital Filter Pole Setting [7:0] Pole location R/W This register determines the position of the final pole. See Figure 57. Table 103. Register 0x67—Light Load Mode Digital Filter HF Gain Setting range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

used to program the adaptive dead time edges. Figure 58. Adaptive Dead Time Window in the GUI Table 104. Register 0x68—Adaptive Dead Time Threshold to Register 0x6F. When this register is programmed to 0x00, the ADT function is disabled. Table 105. Register 0x69—Dead Time 1 7 t 1 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 1 offset R/W This value multiplied by Register 0x70[2:0] determines the t1 offset from nominal timing at no load. 3 t 2 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 2 offset R/W This value multiplied by Register 0x70[2:0] determines the t2 offset from nominal timing at no load.

Table 106. Register 0x6A—Dead Time 2 7 t 3 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 3 offset R/W This value multiplied by Register 0x70[2:0] determines the t3 offset from nominal timing at no load. 3 t 4 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 4 offset R/W This value multiplied by Register 0x70[2:0] determines the t4 offset from nominal timing at no load. Table 107. Register 0x6B—Dead Time 3 7 t 5 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 5 offset R/W This value multiplied by Register 0x70[2:0] determines the t5 offset from nominal timing at no load. 3 t 6 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 6 offset R/W This value multiplied by Register 0x70[2:0] determines the t6 offset from nominal timing at no load.

Table 108. Register 0x6C—Dead Time 4 7 t 7 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 7 offset R/W This value multiplied by Register 0x70[2:0] determines the t7 offset from nominal timing at no load. 3 t 8 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 8 offset R/W This value multiplied by Register 0x70[2:0] determines the t8 offset from nominal timing at no load. Table 109. Register 0x6D—Dead Time 5 7 t 9 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 9 offset R/W This value multiplied by Register 0x70[2:0] determines the t9 offset from nominal timing at no load. 3 t 10 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 10 offset R/W This value multiplied by Register 0x70[2:0] determines the t10 offset from nominal timing at no load.

Table 110. Register 0x6E—Dead Time 6 7 t 11 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 11 offset R/W This value multiplied by Register 0x70[2:0] determines the t11 offset from nominal timing at no load. 3 t 12 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 12 offset R/W This value multiplied by Register 0x70[2:0] determines the t12 offset from nominal timing at no load. Table 111. Register 0x6F—Dead Time 7 7 t 13 polarity R/W 0 = positive polarity; 1 = negative polarity. [6:4] t 13 offset R/W This value multiplied by Register 0x70[2:0] determines the t13 offset from nominal timing at no load. 3 t 14 polarity R/W 0 = positive polarity; 1 = negative polarity. [2:0] t 14 offset R/W This value multiplied by Register 0x70[2:0] determines the t14 offset from nominal timing at no load.

Table 112. Register 0x70—Dead Time Configuration recommended that the averaging time be set to a value much greater than any transient condition. 26 + 1 = 65 switching cycles. [2:0] Multiplier R/W These bits specify the programming step for Register 0x69 to Register 0x6F , Bits[6:4] and Bits[2:0]. Table 113. Register 0x71—Soft Start Digital Filter LF Gain Setting range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 114. Register 0x72—Soft Start Digital Filter Zero Setting [7:0] Zero setting R/W This register determines the position of the final zero. See Figure 57. Table 115. Register 0x73—Soft Start Digital Filter Pole Setting [7:0] Pole location R/W This register determines the position of the final pole. See Figure 57. Table 116. Register 0x74—Soft Start Digital Filter HF Gain Setting range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

Table 117. Register 0x75—Voltage Line Feedforward [7:4] Reserved R/W Reserved.

3 Disable feedforward

start). This operation is gated by the filter GO bit (Register 0x7F[3]). 0 = feedforward enabled during soft start (recommended setting). 1 = feedforward disabled during soft start. These bits set the gain for the voltage feedforward function. Table 118. Register 0x76—Volt-Second Balance Settings (OUTA and OUTB Pins) 7 Modulate enable, t1 R/W Setting this bit enables modulation from balance control on the OUTA rising edge, t1. 6 t 1 sign R/W 0 = positive sign. Increase of balance control modulation moves t1 right. 1 = negative sign. Increase of balance control modulation moves t1 left. 5 Modulate enable, t2 R/W Setting this bit enables modulation from balance control on the OUTA falling edge, t2. 4 t 2 sign R/W 0 = positive sign. Increase of balance control modulation moves t2 right. 1 = negative sign. Increase of balance control modulation moves t2 left. 3 Modulate enable, t3 R/W Setting this bit enables modulation from balance control on the OUTB rising edge, t3. 2 t 3 sign R/W 0 = positive sign. Increase of balance control modulation moves t3 right. 1 = negative sign. Increase of balance control modulation moves t3 left. 1 Modulate enable, t4 R/W Setting this bit enables modulation from balance control on the OUTB falling edge, t4. 0 t 4 sign R/W 0 = positive sign. Increase of balance control modulation moves t4 right. 1 = negative sign. Increase of balance control modulation moves t4 left. Table 119. Register 0x77—Volt-Second Balance Settings (OUTC and OUTD Pins) 7 Modulate enable, t5 R/W Setting this bit enables modulation from balance control on the OUTC rising edge, t5. 6 t 5 sign R/W 0 = positive sign. Increase of balance control modulation moves t5 right. 1 = negative sign. Increase of balance control modulation moves t5 left. 5 Modulate enable, t6 R/W Setting this bit enables modulation from balance control on the OUTC falling edge, t6. 4 t 6 sign R/W 0 = positive sign. Increase of balance control modulation moves t6 right. 1 = negative sign. Increase of balance control modulation moves t6 left. 3 Modulate enable, t7 R/W Setting this bit enables modulation from balance control on the OUTD rising edge, t7. 2 t 7 sign R/W 0 = positive sign. Increase of balance control modulation moves t7 right. 1 = negative sign. Increase of balance control modulation moves t7 left. 1 Modulate enable, t8 R/W Setting this bit enables modulation from balance control on the OUTD falling edge, t8. 0 t 8 sign R/W 0 = positive sign. Increase of balance control modulation moves t8 right. 1 = negative sign. Increase of balance control modulation moves t8 left.

Table 120. Register 0x78—Volt-Second Balance Settings (SR1 and SR2 Pins) 7 Modulate enable, t9 R/W Setting this bit enables modulation from balance control on the SR1 rising edge, t9. 6 t 9 sign R/W 0 = positive sign. Increase of balance control modulation moves t9 right. 1 = negative sign. Increase of balance control modulation moves t9 left. 5 Modulate enable, t10 R/W Setting this bit enables modulation from balance control on the SR1 falling edge, t10. 4 t 10 sign R/W 0 = positive sign. Increase of balance control modulation moves t10 right. 1 = negative sign. Increase of balance control modulation moves t10 left. 3 Modulate enable, t11 R/W Setting this bit enables modulation from balance control on the SR2 rising edge, t11. 2 t 11 sign R/W 0 = positive sign. Increase of balance control modulation moves t11 right. 1 = negative sign. Increase of balance control modulation moves t11 left. 1 Modulate enable, t12 R/W Setting this bit enables modulation from balance control on the SR2 falling edge, t12. 0 t 12 sign R/W 0 = positive sign. Increase of balance control modulation moves t12 right. 1 = negative sign. Increase of balance control modulation moves t12 left. Table 121. Register 0x79—SR Delay Compensation [7:6] Reserved R/W Reserved. [5:0] SR driver delay R/W These bits specify the 6-bit representation of the SR delay in steps of 5 ns. Table 122. Register 0x7A—Filter Transitions [7:6] Reserved R/W Reserved. [5:3] HF ADC configuration R/W Set these bits to 001 at all times for proper operation. 2 Enable soft transition R/W Setting this bit enables a soft transition between filter settings to minimize output transients. All four parameters of each filter are linearly transitioned to the new value. each step is applied at the multiple of switching cycles (tSW) specified by these bits. Table 123. Register 0x7B—PGOOD1 Flag Masking debounce timing after the end of the soft start ramp. 6 CS1 fast OCP R/W If set to 1, this flag is ignored by PGOOD1. 5 CS1 accurate OCP R/W If set to 1, this flag is ignored by PGOOD1. 4 CS2 accurate OCP R/W If set to 1, this flag is ignored by PGOOD1. 3 UVP R/W If set to 1, this flag is ignored by PGOOD1.

2 Local OVP (fast and

R/W If set to 1, this flag is ignored by PGOOD1. 1 Load OVP R/W If set to 1, this flag is ignored by PGOOD1. 0 OrFET R/W If set to 1, this flag is ignored by PGOOD1.

Table 124. Register 0x7C—PGOOD2 Flag Masking debounce timing after the end of the soft start ramp. 6 CS1 fast OCP R/W If set to 1, this flag is ignored by PGOOD2. 5 CS1 accurate OCP R/W If set to 1, this flag is ignored by PGOOD2. 4 CS2 accurate OCP R/W If set to 1, this flag is ignored by PGOOD2. 3 UVP R/W If set to 1, this flag is ignored by PGOOD2. R/W If set to 1, this flag is ignored by PGOOD2. 1 Load OVP R/W If set to 1, this flag is ignored by PGOOD2. 0 OrFET R/W If set to 1, this flag is ignored by PGOOD2. Table 125. Register 0x7D—Light Load Mode Threshold Settings [7:6] Reserved R/W Reserved. cycles (tSW). For example, at 100 kHz, tSW = 10 μs, 64 × tSW = 640 μs. R/W These bits set the averaging speed and resolution used for the light load mode threshold. Faster speed corresponds to lower resolution and, therefore, to lower accuracy of the threshold. Table 126. Register 0x7F—GO Byte [7:4] Reserved R/W Reserved. settings from being temporarily incorrect.

Refer to the I2C communication protocol specification for more information about how to write these commands to the ADP1046. Table 127. Register 0x81—RESTORE_DEFAULT_ALL operating memory. The password is also reset to the default value (0xFF). Table 128. Register 0x82—STORE_USER_ALL block). The EEPROM must first be unlocked. Table 129. Register 0x83—RESTORE_USER_ALL memory. The EEPROM must first be unlocked. Table 130. Register 0x84—EEPROM_CRC_CHKSUM [7:0] EEPROM_CRC_CHKSUM R Return the CRC checksum value from the EEPROM download operation. Table 131. Register 0x85—EEPROM_ADDR_OFFSET [15:0] EEPROM_ADDR_OFFSET R/W Set the address offset of the current EEPROM page. Table 132. Register 0x86—EEPROM_NUM_RD_BYTES [7:0] EEPROM_NUM_RD_BYTES R/W Set the number of read bytes returned when using the EEPROM_DATA_xx command. Table 133. Register 0x87—EEPROM_PAGE_ERASE and their contents should not be erased. Table 134. Register 0x88—EEPROM_PASSWORD type any value other than the password to this register. Table 135. Register 0x89—TRIM_PASSWORD is the same as the EEPROM password.

Table 136. Register 0x8A—EEPROM_INFO Variable EEPROM_INFO Block read Block read from the EEPROM INFO block. Table 137. Register 0x8B—EEPROM_DATA_00 Variable EEPROM_DATA_00 Block read Block read from the EEPROM main block, Page 0. The EEPROM must first be unlocked. This page contains the factory default settings. Table 138. Register 0x8C—EEPROM_DATA_01 Variable EEPROM_DATA_01 Block read Block read from the EEPROM main block, Page 1. The EEPROM must first be unlocked. This page contains the user settings. Table 139. Register 0x8D—EEPROM_DATA_02 and should not be written to or erased. Table 140. Register 0x8E—EEPROM_DATA_03 and should not be written to or erased. Table 141. Register 0x8F—EEPROM_DATA_04 EEPROM must first be unlocked. This page is available to the user for storing data. Table 142. Register 0x90—EEPROM_DATA_05 EEPROM must first be unlocked. This page is available to the user for storing data. Table 143. Register 0x91—EEPROM_DATA_06 EEPROM must first be unlocked. This page is available to the user for storing data. Table 144. Register 0x92—EEPROM_DATA_07 EEPROM must first be unlocked. This page is available to the user for storing data. Table 145. Register 0x93—EEPROM_DATA_08 EEPROM must first be unlocked. This page is available to the user for storing data.

Table 146. Register 0x94—EEPROM_DATA_09 EEPROM must first be unlocked. This page is available to the user for storing data. Table 147. Register 0x95—EEPROM_DATA_10 EEPROM must first be unlocked. This page is available to the user for storing data. Table 148. Register 0x96—EEPROM_DATA_11 EEPROM must first be unlocked. This page is available to the user for storing data. Table 149. Register 0x97—EEPROM_DATA_12 EEPROM must first be unlocked. This page is available to the user for storing data. Table 150. Register 0x98—EEPROM_DATA_13 EEPROM must first be unlocked. This page is available to the user for storing data. Table 151. Register 0x99—EEPROM_DATA_14 EEPROM must first be unlocked. This page is available to the user for storing data. Table 152. Register 0x9A—EEPROM_DATA_15 EEPROM must first be unlocked. This page is available to the user for storing data.

Rev. 0 | Page 88 of 96 ADJUSTING THE TIMING OF THE PWM OUTPUTS To accurately adjust the timing of the PWM outputs, the following registers can be used to set the dead time and delays of the PWM outputs: Register 0x41, Register 0x43, Register 0x45, Register 0x47, Register 0x49, Register 0x4B, Register 0x4D, Register 0x4F, Register 0x51, Register 0x53, Register 0x55, and Register 0x57. The resolution for adjusting the dead time is 5 ns. Refer to the Resonant Mode Register Descriptions section for more information. The software GUI for the ADP1046 can be used to set the frequency limit registers, as well as all other settings related to the resonant mode of operation. FREQUENCY LIMIT SETTING The minimum frequency is set by Register 0x42 and the first four bits of Register 0x44. For example, Register 0x42 is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal). The maximum switching cycle is (160 × 16 + 15) × 5 ns = 12.875 μs The lowest switching frequency limit is 1/12.875 μs = 77.7 kHz The maximum frequency is set by Register 0x46 and by Bits[7:4] of Register 0x48. For example, Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal). The minimum switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs The highest switching frequency limit is 1/1.325 μs = 755 kHz FEEDBACK CONTROL IN RESONANT MODE In contrast to a traditional fixed frequency PWM converter, the output voltage of a resonant converter is regulated by changing the switching frequency. When the ADP1046 is operated in resonant mode, the switching frequency decreases when the sensed voltage is lower than the reference voltage. This makes the ADP1046 capable of controlling a resonant converter in zero-voltage switching (ZVS) mode. Although the switching frequency is variable, the high frequency feedback voltage sampling frequency (VS3± pins) is fixed at 400 kHz. The parameters of the feedback filter are based on this frequency. The method for calculating the filter parameters (gains, zeros, and poles) is the same as that for the fixed frequency PWM mode (see the Digital Filter section). SOFT START IN RESONANT MODE During soft start, the reference voltage of the ADP1046 ramps up. With the feedback loop closed, the switching frequency is reduced from the highest limit to a regulation value. The soft start timing settings and the filter settings are the same as those for the fixed frequency PWM mode (see the Soft Start section). LIGHT LOAD OPERATION (BURST MODE) To control the converter at very light load, the ADP1046 can operate in burst mode. Burst mode can be enabled or disabled using Bits[7:6] of Register 0x4A. When the desired switching frequency is higher than the burst mode threshold, the part enters burst mode. The threshold is determined by the maxi- mum frequency and the burst mode offset setting. The threshold value used to enter burst mode is determined as follows: Threshold value for burst mode = ((Register 0x46 × 16) + Register 0x48[7:4]) + (Register 0x4A[5:0] × 2) The threshold value used to exit burst mode is determined by the entrance value plus 0x10. For example, Register 0x46 is set to 0x10 (16 decimal), Bits[7:4] of Register 0x48 are set to 0, and Bits[5:0] of Register 0x4A are set to 0x8 (8 decimal). The minimum switching cycle is (16 × 16 + 0) × 5 ns = 1.28 μs The highest switching frequency limit is 1/1.28 μs = 781 kHz The threshold to enter burst mode is When the desired switching frequency is higher than 1/1.36 μs = 735 kHz, the PWM outputs are shut down and the part enters burst mode. The threshold to exit burst mode is Therefore, when the desired switching frequency becomes lower than 1/1.44 μs = 694 kHz, the PWM signals are reenabled, and the part exits burst mode. OUTAUX IN RESONANT MODE In resonant mode, the OUTAUX pin cannot be used as a control signal. However, OUTAUX can be used as a fixed frequency PWM signal with a fixed duty cycle. PROTECTIONS IN RESONANT MODE All of the flags and protections that are available in resonant mode behave in the same manner as in fixed frequency PWM mode.

Table 153. Register 0x40—PWM Switching Frequency Setting in Resonant Mode [7:6] Reserved R/W Reserved. enable resonant mode, set these bits to 0x3F (111111). Table 154. Register 0x41—OUTA Rising Edge Dead Time in Resonant Mode switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Table 155. Register 0x42—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode) frequency limit is 1/12.875 μs = 77.7 kHz. Table 156. Register 0x43—OUTA Falling Edge Dead Time in Resonant Mode to 0xFF, the falling edge of OUTA is leading tB. Table 157. Register 0x44—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode) [3:0] Reserved R/W Reserved.

Table 158. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Table 159. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) 1/1.325 μs = 755 kHz. It is recommended that the maximum frequency be limited 1 MHz. Table 160. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode to 0xFF, the falling edge of OUTB is leading tB. Table 161. Register 0x48—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) [3:0] Reserved R/W Reserved.

Table 162. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode to 0xFF, the rising edge of OUTC is leading tB. Table 163. Register 0x4A—Burst Mode Operation in Resonant Mode [7:6] Burst mode enable R/W These bits are used to enable or disable burst mode operation. frequency limit set in Register 0x46. Table 164. Register 0x4B—OUTC Falling Edge Dead Time in Resonant Mode switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Table 165. Register 0x4D—OUTD Rising Edge Dead Time in Resonant Mode to 0xFF , the rising edge of OUTD is leading tB.

Table 166. Register 0x4F—OUTD Falling Edge Dead Time in Resonant Mode switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Table 167. Register 0x51—SR1 Rising Edge Dead Time in Resonant Mode edge, tD. Each LSB corresponds to 5 ns of resolution. Table 168. Register 0x53—SR1 Falling Edge Dead Time in Resonant Mode falling edge, tE. Each LSB corresponds to 5 ns of resolution. Table 169. Register 0x55—SR2 Rising Edge Dead Time in Resonant Mode edge, tE. Each LSB corresponds to 5 ns of resolution. Table 170. Register 0x57—SR2 Falling Edge Dead Time in Resonant Mode edge, tF. Each LSB corresponds to 5 ns of resolution.

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Rev. 0 | Page 94 of 96 NOTES

Rev. 0 | Page 95 of 96 NOTES

Rev. 0 | Page 96 of 96 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10045-0-3/12(0)