ADN8833

ADN8833 (Rev.C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

Ultracompact, 1 A Thermoelectric Cooler (TEC) Driver for Digital Control Systems Rev. C DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Patented high efficiency single inductor architecture ►Integrated low RDSON MOSFETs for TEC driver ►TEC voltage and current operation monitoring ►No external sense resistor required ►Independent TEC heating and cooling current limit settings ►Programmable maximum TEC voltage ►2 MHz PWM driver switching frequency ►External synchronization ►Digital thermal control loop compatible ►2.50 V reference output with 1% accuracy ►Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a 24‑ lead, 4 mm × 4 mm LFCSP

APPLICATIONS

►TEC temperature control ►Optical modules ►Optical fiber amplifiers ►Optical networking systems ►Instruments requiring TEC temperature control FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram to the TEC module to the programmed target temperature. integral, derivative (PID) loop of temperature control system. an analog-to-digital converter (ADC). Table 1. TEC Family Models 1 Product is covered by US Patent No. 6,486,643.

analog.com Rev. C | 2 of 24 Typical Application With Digital PID Using a Guidelines for Reducing Noise and

REVISION HISTORY

10/2024—Rev. B to Rev. C

Table 2. Specifications

Table 2. Specifications (Continued)

1 This specification is guaranteed by design. 2 This specification is guaranteed by characterization.

analog.com Rev. C | 6 of 24 Table 3. Parameter Rating PVIN to PGNDL (WLCSP) −0.3 V to +5.75 V PVIN to PGNDS (WLCSP) −0.3 V to +5.75 V PVINL to PGNDL (LFCSP) −0.3 V to +5.75 V PVINS to PGNDS (LFCSP) −0.3 V to +5.75 V LDR to PGNDL (WLCSP) −0.3 V to VPVIN LDR to PGNDL (LFCSP) −0.3 V to VPVINL SW to PGNDS −0.3 V to +5.75 V SFB to AGND −0.3 V to VVDD AGND to PGNDL −0.3 V to +0.3 V AGND to PGNDS −0.3 V to +0.3 V VLIM/SD to AGND −0.3 V to VVDD ILIM to AGND −0.3 V to VVDD VREF to AGND −0.3 V to +3 V VDD to AGND −0.3 V to +5.75 V EN/SY to AGND −0.3 V to VVDD ITEC to AGND −0.3 V to +5.75 V VTEC to AGND −0.3 V to +5.75 V Maximum Current VREF to AGND 20 mA ITEC to AGND 50 mA VTEC to AGND 50 mA Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec)260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operat- ing conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages, and is based on a 4-layer standard JEDEC board. Table 4. Package Type θJA θJC θJB Unit 25-Ball WLCSP 48 0.6 5.65 °C/W 24-Lead LFCSP 37 1.65 13.68 °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devi- ces and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Figure 2. WLCSP Pin Configuration (Top View) Figure 3. LFCSP Pin Configuration (Top View) Table 5. Pin Function Descriptions A1, A2 18, 19 PGNDL Power Ground of the Linear TEC Driver. 1, 20 to 24DNC Do Not Connect. Do not connect to these pins. B1, B2 17 LDR Output of the Linear TEC Driver. C1, C2 N/A1 PVIN Power Input for the TEC Driver. C3 11 ITEC TEC Current Output. C4 2 CONT Control Input of the TEC Driver. Apply a control signal from the DAC to this pin to close the thermal loop. C5 4 ILIM Current Limit. This pin sets the TEC cooling and heating current limits. D1, D2 14 SW Switch Node Output of the PWM TEC Driver. D3 9 VTEC TEC Voltage Output. D4 8 EN/SY Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input can be applied to this pin. D5 5 VDD Power for the Driver Circuits. E1, E2 12, 13 PGNDS Power Ground of the PWM TEC Driver. E3 10 SFB Feedback of the PWM TEC Driver Output. E5 6 VREF 2.5 V Reference Output. N/A1 0 EP Exposed Pad. Solder to the analog ground plane on the board.

Figure 22. Zero Crossing TEC Current Zoom in from Cooling to Heating

Figure 23. Detailed Functional Block Diagram of the ADN8833 in the WLCSP

back to an ADC to close digital thermal control loop of the TEC. and one capacitor are required to filter out the switching frequency. external temperature measurement ADC. setpoint is applied to the CONT input pin. resistor values are typically 10 Ω and 100 nF, respectively. Figure 24. TEC Driver in a Digital Temperature Control Loop (WLCSP)

Table 6. Enable Pin Combinations

1 No effect means this signal has no effect in shutting down or in enabling the

the shutdown threshold of 0.07 V. EN/SY input pin as shown on Figure 25. Figure 25. Synchronize to an External Clock Figure 26. Multiple ADN8833 Devices Driven from a Controller Clock time. Figure 27 shows an example of the soft start in cooling mode.

1.25 V − V I L I M _ HE ATI NG

Figure 29. Using a Resistor Divider to Set the TEC Current Limit

Figure 30. TEC Driver with Digital PID Based on the ADuC7023 an application circuit with the ADuC7023 is shown in Figure 30. with the proper value of RX placed in series with the thermistor. RTH is a resistance at T (K). RR is a resistance at TR (K). VCONT is the voltage at CONT.

Table 7. Recommended Inductors (Continued) can increase overall regulation and efficiency performance. Table 8. Recommended Capacitors better noise rejection at high frequency bands. typically 10 Ω and 100 nF, respectively. PLOSS is the total power dissipation in the ADN8833. PLINEAR is the power dissipation in the linear regulator. can be neglected in approximation. (PCOND_L) and power switch conduction loss(PCOND_S). each of which has its own internal on resistance (RDSON). RDSON_HS is the on resistance of the high-side MOSFET. D is the duty cycle (D = VOUT/VIN). RDSON_LS is the on resistance of the low-side MOSFET. CGATE_HS is the gate capacitance of the high-side MOSFET. CGATE_LS is the gate capacitance of the low-side MOSFET.

analog.com Rev. C | 20 of 24 fSW is the switching frequency. For the ADN8833, the total of (CGATE_HS + CGATE_LS) is approxi- mately 1 nF. Transition Loss (PTRAN) Transition losses occur because the high-side MOSFET cannot turn on or off instantaneously. During a switch node transition, the MOS- FET provides all the inductor current. The source-to-drain voltage of the MOSFET is half the input voltage, resulting in power loss. Transition losses increase with both load and input voltage and occur twice for each switching cycle. Use the following equation to estimate the transition loss: PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW where: tR is the rise time of the switch node. tF is the fall time of the switch node. For the ADN8833, tR and tF are both approximately 1 ns. Linear Regulator Power Dissipation The power dissipation of the linear regulator is given by the follow- ing equation: PLINEAR = [(VIN − VOUT) × IOUT] + (VIN × IGND) where: VIN and VOUT are the input and output voltages of the linear regulator. IOUT is the load current of the linear regulator. IGND is the ground current of the linear regulator. Power dissipation due to the ground current is generally small and can be ignored for the purposes of this calculation.

Figure 34. System Block Diagram protection block, and a TEC driver power stage all in a single IC. es are minimized to obtain the best possible electrical efficiency. The system block diagram of the ADN8833 is shown in Figure 34. in parallel with it, placed between PVIN and PGNDS. to provide heat sink and to sustain high current flow. possible to PGNDS to minimize the ESL in the return path. like the PWM power stage, it does not generate noise currents.

Figure 37. Example PCB Layout Using Two Layers (Bottom Layer Only)

©2015-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. C | 24 of 24 Package Drawing (Option) Package Type Package Description CB-25-7 WLCSP 25-Ball Wafer Level Chip Scale Package CP-24-15 LFCSP 24-Lead Lead-frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1 Temperature Range2 Package Description Package Option ADN8833ACBZ-R7 −40°C to +125°C 25-Ball Wafer Level Chip Scale Package [WLCSP] CB-25-7 ADN8833ACPZ-R2 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15 ADN8833ACPZ-R7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15 1 Z = RoHS Compliant Part. 2 Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C. EVALUATION BOARDS Model1 Description ADN8833CP-EVALZ 24-Lead LFCSP Evaluation Board: ±1 A TEC Current Limit, 3 V TEC Voltage Limit ADN8833CB-EVALZ 25-Ball WLCSP Evaluation Board: ±1 A TEC Current Limit, 3 V TEC Voltage Limit 1 Z = RoHS Compliant Part.